From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Cc: guoren@linux.alibaba.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation Date: Mon, 9 Mar 2020 16:20:07 +0800 [thread overview] Message-ID: <20200309082042.12967-26-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20200309082042.12967-1-zhiwei_liu@c-sky.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 + target/riscv/vector_helper.c | 103 ++++++++++++++++++++++++ 4 files changed, 118 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d3837d2ca4..333eccca57 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -724,3 +724,12 @@ DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsmul_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0227a16b16..99f70924d6 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -417,6 +417,8 @@ vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm +vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm +vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 9988fad2fe..60e1e63b7b 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1528,3 +1528,7 @@ GEN_OPIVV_TRANS(vasub_vv, opivv_check) GEN_OPIVX_TRANS(vaadd_vx, opivx_check) GEN_OPIVX_TRANS(vasub_vx, opivx_check) GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check) + +/* Vector Single-Width Fractional Multiply with Rounding and Saturation */ +GEN_OPIVV_TRANS(vsmul_vv, opivv_check) +GEN_OPIVX_TRANS(vsmul_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index b0a7a3b6e4..74ad07743c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2420,3 +2420,106 @@ GEN_VEXT_VX_ENV(vasub_vx_b, 1, 1, clearb) GEN_VEXT_VX_ENV(vasub_vx_h, 2, 2, clearh) GEN_VEXT_VX_ENV(vasub_vx_w, 4, 4, clearl) GEN_VEXT_VX_ENV(vasub_vx_d, 8, 8, clearq) + +/* Vector Single-Width Fractional Multiply with Rounding and Saturation */ +static inline int8_t vsmul8(CPURISCVState *env, int8_t a, int8_t b) +{ + uint8_t round; + int16_t res; + + res = (int16_t)a * (int16_t)b; + round = get_round(env, res, 7); + res = (res >> 7) + round; + + if (res > INT8_MAX) { + env->vxsat = 0x1; + return INT8_MAX; + } else if (res < INT8_MIN) { + env->vxsat = 0x1; + return INT8_MIN; + } else { + return res; + } +} +static int16_t vsmul16(CPURISCVState *env, int16_t a, int16_t b) +{ + uint8_t round; + int32_t res; + + res = (int32_t)a * (int32_t)b; + round = get_round(env, res, 15); + res = (res >> 15) + round; + + if (res > INT16_MAX) { + env->vxsat = 0x1; + return INT16_MAX; + } else if (res < INT16_MIN) { + env->vxsat = 0x1; + return INT16_MIN; + } else { + return res; + } +} +static int32_t vsmul32(CPURISCVState *env, int32_t a, int32_t b) +{ + uint8_t round; + int64_t res; + + res = (int64_t)a * (int64_t)b; + round = get_round(env, res, 31); + res = (res >> 31) + round; + + if (res > INT32_MAX) { + env->vxsat = 0x1; + return INT32_MAX; + } else if (res < INT32_MIN) { + env->vxsat = 0x1; + return INT32_MIN; + } else { + return res; + } +} +static int64_t vsmul64(CPURISCVState *env, int64_t a, int64_t b) +{ + uint8_t round; + uint64_t hi_64, lo_64, Hi62; + uint8_t hi62, hi63, lo63; + + muls64(&lo_64, &hi_64, a, b); + hi62 = extract64(hi_64, 62, 1); + lo63 = extract64(lo_64, 63, 1); + hi63 = extract64(hi_64, 63, 1); + Hi62 = extract64(hi_64, 0, 62); + if (hi62 != hi63) { + env->vxsat = 0x1; + return INT64_MAX; + } + round = get_round(env, lo_64, 63); + if (round && (Hi62 == 0x3fffffff) && lo63) { + env->vxsat = 0x1; + return hi62 ? INT64_MIN : INT64_MAX; + } else { + if (lo63 && round) { + return (hi_64 + 1) << 1; + } else { + return (hi_64 << 1) | lo63 | round; + } + } +} +RVVCALL(OPIVV2_ENV, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8) +RVVCALL(OPIVV2_ENV, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16) +RVVCALL(OPIVV2_ENV, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32) +RVVCALL(OPIVV2_ENV, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64) +GEN_VEXT_VV_ENV(vsmul_vv_b, 1, 1, clearb) +GEN_VEXT_VV_ENV(vsmul_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vsmul_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vsmul_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2_ENV, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8) +RVVCALL(OPIVX2_ENV, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16) +RVVCALL(OPIVX2_ENV, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32) +RVVCALL(OPIVX2_ENV, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64) +GEN_VEXT_VX_ENV(vsmul_vx_b, 1, 1, clearb) +GEN_VEXT_VX_ENV(vsmul_vx_h, 2, 2, clearh) +GEN_VEXT_VX_ENV(vsmul_vx_w, 4, 4, clearl) +GEN_VEXT_VX_ENV(vsmul_vx_d, 8, 8, clearq) -- 2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Cc: wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com, guoren@linux.alibaba.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation Date: Mon, 9 Mar 2020 16:20:07 +0800 [thread overview] Message-ID: <20200309082042.12967-26-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20200309082042.12967-1-zhiwei_liu@c-sky.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 + target/riscv/vector_helper.c | 103 ++++++++++++++++++++++++ 4 files changed, 118 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d3837d2ca4..333eccca57 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -724,3 +724,12 @@ DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsmul_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0227a16b16..99f70924d6 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -417,6 +417,8 @@ vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm +vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm +vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 9988fad2fe..60e1e63b7b 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1528,3 +1528,7 @@ GEN_OPIVV_TRANS(vasub_vv, opivv_check) GEN_OPIVX_TRANS(vaadd_vx, opivx_check) GEN_OPIVX_TRANS(vasub_vx, opivx_check) GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check) + +/* Vector Single-Width Fractional Multiply with Rounding and Saturation */ +GEN_OPIVV_TRANS(vsmul_vv, opivv_check) +GEN_OPIVX_TRANS(vsmul_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index b0a7a3b6e4..74ad07743c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2420,3 +2420,106 @@ GEN_VEXT_VX_ENV(vasub_vx_b, 1, 1, clearb) GEN_VEXT_VX_ENV(vasub_vx_h, 2, 2, clearh) GEN_VEXT_VX_ENV(vasub_vx_w, 4, 4, clearl) GEN_VEXT_VX_ENV(vasub_vx_d, 8, 8, clearq) + +/* Vector Single-Width Fractional Multiply with Rounding and Saturation */ +static inline int8_t vsmul8(CPURISCVState *env, int8_t a, int8_t b) +{ + uint8_t round; + int16_t res; + + res = (int16_t)a * (int16_t)b; + round = get_round(env, res, 7); + res = (res >> 7) + round; + + if (res > INT8_MAX) { + env->vxsat = 0x1; + return INT8_MAX; + } else if (res < INT8_MIN) { + env->vxsat = 0x1; + return INT8_MIN; + } else { + return res; + } +} +static int16_t vsmul16(CPURISCVState *env, int16_t a, int16_t b) +{ + uint8_t round; + int32_t res; + + res = (int32_t)a * (int32_t)b; + round = get_round(env, res, 15); + res = (res >> 15) + round; + + if (res > INT16_MAX) { + env->vxsat = 0x1; + return INT16_MAX; + } else if (res < INT16_MIN) { + env->vxsat = 0x1; + return INT16_MIN; + } else { + return res; + } +} +static int32_t vsmul32(CPURISCVState *env, int32_t a, int32_t b) +{ + uint8_t round; + int64_t res; + + res = (int64_t)a * (int64_t)b; + round = get_round(env, res, 31); + res = (res >> 31) + round; + + if (res > INT32_MAX) { + env->vxsat = 0x1; + return INT32_MAX; + } else if (res < INT32_MIN) { + env->vxsat = 0x1; + return INT32_MIN; + } else { + return res; + } +} +static int64_t vsmul64(CPURISCVState *env, int64_t a, int64_t b) +{ + uint8_t round; + uint64_t hi_64, lo_64, Hi62; + uint8_t hi62, hi63, lo63; + + muls64(&lo_64, &hi_64, a, b); + hi62 = extract64(hi_64, 62, 1); + lo63 = extract64(lo_64, 63, 1); + hi63 = extract64(hi_64, 63, 1); + Hi62 = extract64(hi_64, 0, 62); + if (hi62 != hi63) { + env->vxsat = 0x1; + return INT64_MAX; + } + round = get_round(env, lo_64, 63); + if (round && (Hi62 == 0x3fffffff) && lo63) { + env->vxsat = 0x1; + return hi62 ? INT64_MIN : INT64_MAX; + } else { + if (lo63 && round) { + return (hi_64 + 1) << 1; + } else { + return (hi_64 << 1) | lo63 | round; + } + } +} +RVVCALL(OPIVV2_ENV, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8) +RVVCALL(OPIVV2_ENV, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16) +RVVCALL(OPIVV2_ENV, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32) +RVVCALL(OPIVV2_ENV, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64) +GEN_VEXT_VV_ENV(vsmul_vv_b, 1, 1, clearb) +GEN_VEXT_VV_ENV(vsmul_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vsmul_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vsmul_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2_ENV, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8) +RVVCALL(OPIVX2_ENV, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16) +RVVCALL(OPIVX2_ENV, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32) +RVVCALL(OPIVX2_ENV, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64) +GEN_VEXT_VX_ENV(vsmul_vx_b, 1, 1, clearb) +GEN_VEXT_VX_ENV(vsmul_vx_h, 2, 2, clearh) +GEN_VEXT_VX_ENV(vsmul_vx_w, 4, 4, clearl) +GEN_VEXT_VX_ENV(vsmul_vx_d, 8, 8, clearq) -- 2.23.0
next prev parent reply other threads:[~2020-03-09 8:27 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-09 8:19 [PATCH v3 00/60] target/riscv: support vector extension v0.7.1 LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 02/60] target/riscv: implementation-defined constant parameters LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 03/60] target/riscv: support vector extension csr LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 04/60] target/riscv: add vector configure instruction LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 05/60] target/riscv: add vector stride load and store instructions LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 06/60] target/riscv: add vector index " LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 07/60] target/riscv: add fault-only-first unit stride load LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 08/60] target/riscv: add vector amo operations LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 09/60] target/riscv: vector single-width integer add and subtract LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 10/60] target/riscv: vector widening " LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 12/60] target/riscv: vector bitwise logical instructions LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 13/60] target/riscv: vector single-width bit shift instructions LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 14/60] target/riscv: vector narrowing integer right " LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 15/60] target/riscv: vector integer comparison instructions LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 17/60] target/riscv: vector single-width integer multiply instructions LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 18/60] target/riscv: vector integer divide instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 19/60] target/riscv: vector widening integer multiply instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 20/60] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 21/60] target/riscv: vector widening " LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 22/60] target/riscv: vector integer merge and move instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 23/60] target/riscv: vector single-width saturating add and subtract LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 24/60] target/riscv: vector single-width averaging " LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei [this message] 2020-03-09 8:20 ` [PATCH v3 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 26/60] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 27/60] target/riscv: vector single-width scaling shift instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 28/60] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 29/60] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 30/60] target/riscv: vector widening " LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 31/60] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 32/60] target/riscv: vector widening floating-point multiply LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 34/60] target/riscv: vector widening " LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 35/60] target/riscv: vector floating-point square-root instruction LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 36/60] target/riscv: vector floating-point min/max instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 37/60] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 38/60] target/riscv: vector floating-point compare instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 39/60] target/riscv: vector floating-point classify instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 40/60] target/riscv: vector floating-point merge instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 41/60] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 42/60] target/riscv: widening " LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 43/60] target/riscv: narrowing " LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 45/60] target/riscv: vector wideing integer reduction instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 48/60] target/riscv: vector mask-register logical instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 12:13 [PATCH v3 00/60] target/riscv: support vector extension v0.7.1 LIU Zhiwei 2020-03-09 12:14 ` [PATCH v3 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei 2020-03-09 12:14 ` LIU Zhiwei
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