From: Francisco Jerez <currojerez@riseup.net> To: "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Pandruvada\, Srinivas" <srinivas.pandruvada@intel.com> Cc: linux-pm@vger.kernel.org, intel-gfx@lists.freedesktop.org, chris.p.wilson@intel.com, "Vivi\, Rodrigo" <rodrigo.vivi@intel.com>, Peter Zijlstra <peterz@infradead.org> Subject: [PATCHv2.99 09/11] cpufreq: intel_pstate: Enable VLP controller based on ACPI FADT profile and CPUID. Date: Mon, 27 Apr 2020 20:22:56 -0700 [thread overview] Message-ID: <20200428032258.2518-10-currojerez@riseup.net> (raw) In-Reply-To: <20200428032258.2518-1-currojerez@riseup.net> For the moment the VLP controller is only enabled on ICL platforms other than server FADT profiles in order to reduce the validation effort of the initial submission. It should work on any other processors that support HWP though (and soon enough on non-HWP too): In order to override the default behavior (e.g. to test on other platforms) the VLP controller can be forcefully enabled or disabled by selecting the "adaptive" or "powersave" CPUFREQ governors respectively via sysfs. v2: Handle HWP VLP controller. v3: Define generic CPUFREQ policy to control VLP governor (Rafael). Signed-off-by: Francisco Jerez <currojerez@riseup.net> --- drivers/cpufreq/intel_pstate.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 0a315f681c43..2458a821195f 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -396,6 +396,7 @@ static int hwp_active __read_mostly; static int hwp_mode_bdw __read_mostly; static bool per_cpu_limits __read_mostly; static bool hwp_boost __read_mostly; +static bool vlp __read_mostly; static struct cpufreq_driver *intel_pstate_driver __read_mostly; @@ -2724,7 +2725,8 @@ static int intel_pstate_cpu_init(struct cpufreq_policy *policy) * Set the policy to powersave to provide a valid fallback value in case * the default cpufreq governor is neither powersave nor performance. */ - policy->policy = CPUFREQ_POLICY_POWERSAVE; + policy->policy = (vlp ? CPUFREQ_POLICY_ADAPTIVE : + CPUFREQ_POLICY_POWERSAVE); return 0; } @@ -3209,6 +3211,16 @@ static const struct x86_cpu_id hwp_support_ids[] __initconst = { {} }; +#define X86_MATCH_VLP(model) \ + X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ + X86_FEATURE_APERFMPERF, 0) + +static const struct x86_cpu_id vlp_default_ids[] __initconst = { + X86_MATCH_VLP(ICELAKE), + X86_MATCH_VLP(ICELAKE_L), + {} +}; + static int __init intel_pstate_init(void) { const struct x86_cpu_id *id; @@ -3247,6 +3259,10 @@ static int __init intel_pstate_init(void) default_driver = &intel_cpufreq; hwp_cpu_matched: + /* Enable VLP controller by default. */ + vlp = !intel_pstate_acpi_pm_profile_server() && + x86_match_cpu(vlp_default_ids) && hwp_active; + /* * The Intel pstate driver will be ignored if the platform * firmware has its own power management modes. -- 2.22.1
WARNING: multiple messages have this Message-ID (diff)
From: Francisco Jerez <currojerez@riseup.net> To: "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Pandruvada\, Srinivas" <srinivas.pandruvada@intel.com> Cc: Peter Zijlstra <peterz@infradead.org>, intel-gfx@lists.freedesktop.org, chris.p.wilson@intel.com, linux-pm@vger.kernel.org Subject: [Intel-gfx] [PATCHv2.99 09/11] cpufreq: intel_pstate: Enable VLP controller based on ACPI FADT profile and CPUID. Date: Mon, 27 Apr 2020 20:22:56 -0700 [thread overview] Message-ID: <20200428032258.2518-10-currojerez@riseup.net> (raw) In-Reply-To: <20200428032258.2518-1-currojerez@riseup.net> For the moment the VLP controller is only enabled on ICL platforms other than server FADT profiles in order to reduce the validation effort of the initial submission. It should work on any other processors that support HWP though (and soon enough on non-HWP too): In order to override the default behavior (e.g. to test on other platforms) the VLP controller can be forcefully enabled or disabled by selecting the "adaptive" or "powersave" CPUFREQ governors respectively via sysfs. v2: Handle HWP VLP controller. v3: Define generic CPUFREQ policy to control VLP governor (Rafael). Signed-off-by: Francisco Jerez <currojerez@riseup.net> --- drivers/cpufreq/intel_pstate.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 0a315f681c43..2458a821195f 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -396,6 +396,7 @@ static int hwp_active __read_mostly; static int hwp_mode_bdw __read_mostly; static bool per_cpu_limits __read_mostly; static bool hwp_boost __read_mostly; +static bool vlp __read_mostly; static struct cpufreq_driver *intel_pstate_driver __read_mostly; @@ -2724,7 +2725,8 @@ static int intel_pstate_cpu_init(struct cpufreq_policy *policy) * Set the policy to powersave to provide a valid fallback value in case * the default cpufreq governor is neither powersave nor performance. */ - policy->policy = CPUFREQ_POLICY_POWERSAVE; + policy->policy = (vlp ? CPUFREQ_POLICY_ADAPTIVE : + CPUFREQ_POLICY_POWERSAVE); return 0; } @@ -3209,6 +3211,16 @@ static const struct x86_cpu_id hwp_support_ids[] __initconst = { {} }; +#define X86_MATCH_VLP(model) \ + X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ + X86_FEATURE_APERFMPERF, 0) + +static const struct x86_cpu_id vlp_default_ids[] __initconst = { + X86_MATCH_VLP(ICELAKE), + X86_MATCH_VLP(ICELAKE_L), + {} +}; + static int __init intel_pstate_init(void) { const struct x86_cpu_id *id; @@ -3247,6 +3259,10 @@ static int __init intel_pstate_init(void) default_driver = &intel_cpufreq; hwp_cpu_matched: + /* Enable VLP controller by default. */ + vlp = !intel_pstate_acpi_pm_profile_server() && + x86_match_cpu(vlp_default_ids) && hwp_active; + /* * The Intel pstate driver will be ignored if the platform * firmware has its own power management modes. -- 2.22.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-04-28 3:27 UTC|newest] Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-28 3:22 [RFC] GPU-bound energy efficiency improvements for the intel_pstate driver (v2.99) Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 01/11] PM: QoS: Add CPU_SCALING_RESPONSE global PM QoS limit Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 02/11] drm/i915: Adjust PM QoS scaling response frequency based on GPU load Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 03/11] OPTIONAL: drm/i915: Expose PM QoS control parameters via debugfs Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 04/11] cpufreq: Define ADAPTIVE frequency governor policy Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 05/11] cpufreq: intel_pstate: Reorder intel_pstate_clear_update_util_hook() and intel_pstate_set_update_util_hook() Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 06/11] cpufreq: intel_pstate: Call intel_pstate_set_update_util_hook() once from the setpolicy hook Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 07/11] cpufreq: intel_pstate: Implement VLP controller statistics and target range calculation Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 08/11] cpufreq: intel_pstate: Implement VLP controller for HWP parts Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` Francisco Jerez [this message] 2020-04-28 3:22 ` [Intel-gfx] [PATCHv2.99 09/11] cpufreq: intel_pstate: Enable VLP controller based on ACPI FADT profile and CPUID Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 10/11] OPTIONAL: cpufreq: intel_pstate: Add tracing of VLP controller status Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:22 ` [PATCHv2.99 11/11] OPTIONAL: cpufreq: intel_pstate: Expose VLP controller parameters via debugfs Francisco Jerez 2020-04-28 3:22 ` [Intel-gfx] " Francisco Jerez 2020-04-28 3:32 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [PATCHv2.99,01/11] PM: QoS: Add CPU_SCALING_RESPONSE global PM QoS limit Patchwork 2020-05-11 10:57 ` [RFC] GPU-bound energy efficiency improvements for the intel_pstate driver (v2.99) Peter Zijlstra 2020-05-11 10:57 ` [Intel-gfx] " Peter Zijlstra 2020-05-11 21:01 ` Francisco Jerez 2020-05-11 21:01 ` [Intel-gfx] " Francisco Jerez 2020-05-14 10:26 ` Rafael J. Wysocki 2020-05-14 10:26 ` [Intel-gfx] " Rafael J. Wysocki 2020-05-15 0:48 ` Francisco Jerez 2020-05-15 0:48 ` [Intel-gfx] " Francisco Jerez 2020-05-14 11:50 ` Valentin Schneider 2020-05-14 11:50 ` [Intel-gfx] " Valentin Schneider 2020-05-15 0:48 ` Francisco Jerez 2020-05-15 0:48 ` [Intel-gfx] " Francisco Jerez 2020-05-15 18:09 ` Valentin Schneider 2020-05-15 18:09 ` [Intel-gfx] " Valentin Schneider 2020-05-28 9:29 ` Lukasz Luba 2020-05-28 9:29 ` [Intel-gfx] " Lukasz Luba
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