[arm-tegra:for-5.8/clk 11/11] drivers/clk/tegra/clk-tegra210.c:3084:7: error: 'TEGRA210_CLK_CSI_TPG' undeclared; did you mean 'TEGRA210_CLK_CSITE'?

[arm-tegra:for-5.8/clk 11/11] drivers/clk/tegra/clk-tegra210.c:3084:7: error: 'TEGRA210_CLK_CSI_TPG' undeclared; did you mean 'TEGRA210_CLK_CSITE'?

[kbuild test robot]

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git for-5.8/clk
head:   e702de255e05f9d81d6cb9fd8f53a2abd51153fe
commit: e702de255e05f9d81d6cb9fd8f53a2abd51153fe [11/11] clk: tegra: Add Tegra210 CSI TPG clock gate
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        git checkout e702de255e05f9d81d6cb9fd8f53a2abd51153fe
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day GCC_VERSION=9.3.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/clk/tegra/clk-tegra210.c: In function 'tegra210_periph_clk_init':
>> drivers/clk/tegra/clk-tegra210.c:3084:7: error: 'TEGRA210_CLK_CSI_TPG' undeclared (first use in this function); did you mean 'TEGRA210_CLK_CSITE'?
    3084 |  clks[TEGRA210_CLK_CSI_TPG] = clk;
         |       ^~~~~~~~~~~~~~~~~~~~
         |       TEGRA210_CLK_CSITE
   drivers/clk/tegra/clk-tegra210.c:3084:7: note: each undeclared identifier is reported only once for each function it appears in

vim +3084 drivers/clk/tegra/clk-tegra210.c

  3034	
  3035	static struct tegra_clk_periph tegra210_la =
  3036		TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, NULL);
  3037	
  3038	static __init void tegra210_periph_clk_init(struct device_node *np,
  3039						    void __iomem *clk_base,
  3040						    void __iomem *pmc_base)
  3041	{
  3042		struct clk *clk;
  3043		unsigned int i;
  3044	
  3045		/* xusb_ss_div2 */
  3046		clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
  3047						1, 2);
  3048		clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
  3049	
  3050		clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
  3051						      1, 17, 222);
  3052		clks[TEGRA210_CLK_SOR_SAFE] = clk;
  3053	
  3054		clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
  3055						      1, 17, 181);
  3056		clks[TEGRA210_CLK_DPAUX] = clk;
  3057	
  3058		clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
  3059						      1, 17, 207);
  3060		clks[TEGRA210_CLK_DPAUX1] = clk;
  3061	
  3062		/* pll_d_dsi_out */
  3063		clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
  3064					clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
  3065		clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk;
  3066	
  3067		/* dsia */
  3068		clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
  3069						     clk_base, 0, 48,
  3070						     periph_clk_enb_refcnt);
  3071		clks[TEGRA210_CLK_DSIA] = clk;
  3072	
  3073		/* dsib */
  3074		clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
  3075						     clk_base, 0, 82,
  3076						     periph_clk_enb_refcnt);
  3077		clks[TEGRA210_CLK_DSIB] = clk;
  3078	
  3079		/* csi_tpg */
  3080		clk = clk_register_gate(NULL, "csi_tpg", "pll_d",
  3081					CLK_SET_RATE_PARENT, clk_base + PLLD_BASE,
  3082					23, 0, &pll_d_lock);
  3083		clk_register_clkdev(clk, "csi_tpg", NULL);
> 3084		clks[TEGRA210_CLK_CSI_TPG] = clk;
  3085	
  3086		/* la */
  3087		clk = tegra_clk_register_periph("la", la_parents,
  3088				ARRAY_SIZE(la_parents), &tegra210_la, clk_base,
  3089				CLK_SOURCE_LA, 0);
  3090		clks[TEGRA210_CLK_LA] = clk;
  3091	
  3092		/* cml0 */
  3093		clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
  3094					0, 0, &pll_e_lock);
  3095		clk_register_clkdev(clk, "cml0", NULL);
  3096		clks[TEGRA210_CLK_CML0] = clk;
  3097	
  3098		/* cml1 */
  3099		clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
  3100					1, 0, &pll_e_lock);
  3101		clk_register_clkdev(clk, "cml1", NULL);
  3102		clks[TEGRA210_CLK_CML1] = clk;
  3103	
  3104		clk = tegra_clk_register_super_clk("aclk", aclk_parents,
  3105					ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
  3106					0, NULL);
  3107		clks[TEGRA210_CLK_ACLK] = clk;
  3108	
  3109		clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
  3110						    CLK_SOURCE_SDMMC2, 9,
  3111						    TEGRA_DIVIDER_ROUND_UP, 0, NULL);
  3112		clks[TEGRA210_CLK_SDMMC2] = clk;
  3113	
  3114		clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
  3115						    CLK_SOURCE_SDMMC4, 15,
  3116						    TEGRA_DIVIDER_ROUND_UP, 0, NULL);
  3117		clks[TEGRA210_CLK_SDMMC4] = clk;
  3118	
  3119		for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {
  3120			struct tegra_periph_init_data *init = &tegra210_periph[i];
  3121			struct clk **clkp;
  3122	
  3123			clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks);
  3124			if (!clkp) {
  3125				pr_warn("clock %u not found\n", init->clk_id);
  3126				continue;
  3127			}
  3128	
  3129			clk = tegra_clk_register_periph_data(clk_base, init);
  3130			*clkp = clk;
  3131		}
  3132	
  3133		tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
  3134	
  3135		/* emc */
  3136		clk = tegra210_clk_register_emc(np, clk_base);
  3137		clks[TEGRA210_CLK_EMC] = clk;
  3138	
  3139		/* mc */
  3140		tegra210_clk_register_mc("mc", "emc");
  3141	}
  3142	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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