From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au, linux-nvdimm@lists.01.org Cc: alistair@popple.id.au, "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> Subject: [PATCH v2 1/5] powerpc/pmem: Add new instructions for persistent storage and sync Date: Wed, 13 May 2020 09:17:01 +0530 [thread overview] Message-ID: <20200513034705.172983-1-aneesh.kumar@linux.ibm.com> (raw) POWER10 introduces two new variants of dcbf instructions (dcbstps and dcbfps) that can be used to write modified locations back to persistent storage. Additionally, POWER10 also introduce phwsync and plwsync which can be used to establish order of these writes to persistent storage. This patch exposes these instructions to the rest of the kernel. The existing dcbf and hwsync instructions in P9 are adequate to enable appropriate synchronization with OpenCAPI-hosted persistent storage. Hence the new instructions are added as a variant of the old ones that old hardware won't differentiate. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> --- arch/powerpc/include/asm/ppc-opcode.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index c1df75edde44..45eccd842f84 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -216,6 +216,8 @@ #define PPC_INST_STWCX 0x7c00012d #define PPC_INST_LWSYNC 0x7c2004ac #define PPC_INST_SYNC 0x7c0004ac +#define PPC_INST_PHWSYNC 0x7c8004ac +#define PPC_INST_PLWSYNC 0x7ca004ac #define PPC_INST_SYNC_MASK 0xfc0007fe #define PPC_INST_ISYNC 0x4c00012c #define PPC_INST_LXVD2X 0x7c000698 @@ -281,6 +283,8 @@ #define PPC_INST_TABORT 0x7c00071d #define PPC_INST_TSR 0x7c0005dd +#define PPC_INST_DCBF 0x7c0000ac + #define PPC_INST_NAP 0x4c000364 #define PPC_INST_SLEEP 0x4c0003a4 #define PPC_INST_WINKLE 0x4c0003e4 @@ -529,6 +533,14 @@ #define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \ __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) +#define PPC_DCBFPS(a, b) stringify_in_c(.long PPC_INST_DCBF | \ + ___PPC_RA(a) | ___PPC_RB(b) | (4 << 21)) +#define PPC_DCBSTPS(a, b) stringify_in_c(.long PPC_INST_DCBF | \ + ___PPC_RA(a) | ___PPC_RB(b) | (6 << 21)) + +#define PPC_PHWSYNC stringify_in_c(.long PPC_INST_PHWSYNC) +#define PPC_PLWSYNC stringify_in_c(.long PPC_INST_PLWSYNC) + /* * Define what the VSX XX1 form instructions will look like, then add * the 128 bit load store instructions based on that. -- 2.26.2 _______________________________________________ Linux-nvdimm mailing list -- linux-nvdimm@lists.01.org To unsubscribe send an email to linux-nvdimm-leave@lists.01.org
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From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au, linux-nvdimm@lists.01.org Cc: alistair@popple.id.au, dan.j.williams@intel.com, oohall@gmail.com, "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> Subject: [PATCH v2 1/5] powerpc/pmem: Add new instructions for persistent storage and sync Date: Wed, 13 May 2020 09:17:01 +0530 [thread overview] Message-ID: <20200513034705.172983-1-aneesh.kumar@linux.ibm.com> (raw) POWER10 introduces two new variants of dcbf instructions (dcbstps and dcbfps) that can be used to write modified locations back to persistent storage. Additionally, POWER10 also introduce phwsync and plwsync which can be used to establish order of these writes to persistent storage. This patch exposes these instructions to the rest of the kernel. The existing dcbf and hwsync instructions in P9 are adequate to enable appropriate synchronization with OpenCAPI-hosted persistent storage. Hence the new instructions are added as a variant of the old ones that old hardware won't differentiate. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> --- arch/powerpc/include/asm/ppc-opcode.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index c1df75edde44..45eccd842f84 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -216,6 +216,8 @@ #define PPC_INST_STWCX 0x7c00012d #define PPC_INST_LWSYNC 0x7c2004ac #define PPC_INST_SYNC 0x7c0004ac +#define PPC_INST_PHWSYNC 0x7c8004ac +#define PPC_INST_PLWSYNC 0x7ca004ac #define PPC_INST_SYNC_MASK 0xfc0007fe #define PPC_INST_ISYNC 0x4c00012c #define PPC_INST_LXVD2X 0x7c000698 @@ -281,6 +283,8 @@ #define PPC_INST_TABORT 0x7c00071d #define PPC_INST_TSR 0x7c0005dd +#define PPC_INST_DCBF 0x7c0000ac + #define PPC_INST_NAP 0x4c000364 #define PPC_INST_SLEEP 0x4c0003a4 #define PPC_INST_WINKLE 0x4c0003e4 @@ -529,6 +533,14 @@ #define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \ __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) +#define PPC_DCBFPS(a, b) stringify_in_c(.long PPC_INST_DCBF | \ + ___PPC_RA(a) | ___PPC_RB(b) | (4 << 21)) +#define PPC_DCBSTPS(a, b) stringify_in_c(.long PPC_INST_DCBF | \ + ___PPC_RA(a) | ___PPC_RB(b) | (6 << 21)) + +#define PPC_PHWSYNC stringify_in_c(.long PPC_INST_PHWSYNC) +#define PPC_PLWSYNC stringify_in_c(.long PPC_INST_PLWSYNC) + /* * Define what the VSX XX1 form instructions will look like, then add * the 128 bit load store instructions based on that. -- 2.26.2
next reply other threads:[~2020-05-13 3:48 UTC|newest] Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-13 3:47 Aneesh Kumar K.V [this message] 2020-05-13 3:47 ` [PATCH v2 1/5] powerpc/pmem: Add new instructions for persistent storage and sync Aneesh Kumar K.V 2020-05-13 3:47 ` [PATCH v2 2/5] powerpc/pmem: Add flush routines using new pmem store and sync instruction Aneesh Kumar K.V 2020-05-13 3:47 ` Aneesh Kumar K.V 2020-05-13 3:47 ` [PATCH v2 3/5] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier Aneesh Kumar K.V 2020-05-13 3:47 ` Aneesh Kumar K.V 2020-05-13 16:14 ` Dan Williams 2020-05-13 16:14 ` Dan Williams 2020-05-19 5:30 ` Aneesh Kumar K.V 2020-05-19 5:30 ` Aneesh Kumar K.V 2020-05-19 7:09 ` Dan Williams 2020-05-19 7:09 ` Dan Williams 2020-05-19 13:52 ` Aneesh Kumar K.V 2020-05-19 13:52 ` Aneesh Kumar K.V 2020-05-19 18:59 ` Dan Williams 2020-05-19 18:59 ` Dan Williams 2020-05-20 18:43 ` Aneesh Kumar K.V 2020-05-20 18:43 ` Aneesh Kumar K.V 2020-05-21 14:38 ` Jeff Moyer 2020-05-21 14:38 ` Jeff Moyer 2020-05-21 17:02 ` Aneesh Kumar K.V 2020-05-21 17:02 ` Aneesh Kumar K.V 2020-05-21 18:25 ` Dan Williams 2020-05-21 18:25 ` Dan Williams 2020-05-21 18:52 ` Mikulas Patocka 2020-05-21 18:52 ` Mikulas Patocka 2020-05-22 9:31 ` Michal Suchánek 2020-05-22 9:31 ` Michal Suchánek 2020-05-22 10:08 ` Aneesh Kumar K.V 2020-05-22 10:08 ` Aneesh Kumar K.V 2020-05-22 13:01 ` Mikulas Patocka 2020-05-22 13:01 ` Mikulas Patocka 2020-06-26 10:20 ` Michal Suchánek 2020-06-26 10:20 ` Michal Suchánek 2020-05-21 18:34 ` Dan Williams 2020-05-21 18:34 ` Dan Williams 2020-05-13 3:47 ` [PATCH v2 4/5] powerpc/pmem/of_pmem: Update of_pmem to use the new barrier instruction Aneesh Kumar K.V 2020-05-13 3:47 ` Aneesh Kumar K.V 2020-05-13 6:44 ` kbuild test robot 2020-05-13 6:44 ` kbuild test robot 2020-05-13 6:44 ` kbuild test robot 2020-05-13 3:47 ` [PATCH v2 5/5] powerpc/pmem: Avoid the barrier in flush routines Aneesh Kumar K.V 2020-05-13 3:47 ` Aneesh Kumar K.V
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