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From: Andrew Lunn <andrew@lunn.ch>
To: Oleksij Rempel <o.rempel@pengutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>, Marek Vasut <marex@denx.de>,
	Florian Fainelli <f.fainelli@gmail.com>,
	devicetree@vger.kernel.org, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	David Jander <david@protonic.nl>,
	"David S. Miller" <davem@davemloft.net>,
	Heiner Kallweit <hkallweit1@gmail.com>
Subject: Re: [PATCH net-next v1] net: phy: tja11xx: add cable-test support
Date: Wed, 13 May 2020 21:30:56 +0200	[thread overview]
Message-ID: <20200513193056.GN499265@lunn.ch> (raw)
In-Reply-To: <20200513174011.kl6l767cimeo6dpy@pengutronix.de>

> > Do these registers all conform to the standard? Can we pull this code
> > out into a library which all standards conformant PHY drivers can use?
> 
> According to opensig, this functionality should be present on all new T1 PHYs.
> But the register/bit layout is no specified as standard. At least I was not able
> to find it. I assume, current layout is TJA11xx specific.

O.K. then:

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

  parent reply	other threads:[~2020-05-13 19:31 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-13 12:34 [PATCH net-next v1] net: phy: tja11xx: add cable-test support Oleksij Rempel
2020-05-13 13:39 ` Andrew Lunn
2020-05-13 17:40   ` Oleksij Rempel
2020-05-13 18:01     ` Andrew Lunn
2020-05-14 12:09       ` Oleksij Rempel
2020-05-14 13:38         ` Andrew Lunn
2020-05-14 15:47           ` [EXT] " Christian Herber
2020-05-14 16:01             ` Andrew Lunn
2020-05-14 17:27               ` Oleksij Rempel
2020-05-13 19:30     ` Andrew Lunn [this message]
2020-05-13 19:34 ` Florian Fainelli
2020-05-13 19:36 ` David Miller

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