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From: kbuild test robot <lkp@intel.com>
To: Lars Povlsen <lars.povlsen@microchip.com>,
	SoC Team <soc@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
	Stephen Boyd <sboyd@kernel.org>,
	Linus Walleij <linus.walleij@linaro.org>
Cc: kbuild-all@lists.01.org,
	Lars Povlsen <lars.povlsen@microchip.com>,
	Steen Hegelund <Steen.Hegelund@microchip.com>,
	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
	Olof Johansson <olof@lixom.net>,
	Michael Turquette <mturquette@baylibre.com>,
	devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 09/14] pinctrl: ocelot: Add Sparx5 SoC support
Date: Fri, 15 May 2020 02:09:07 +0800	[thread overview]
Message-ID: <202005150200.wnjISCrm%lkp@intel.com> (raw)
In-Reply-To: <20200513125532.24585-10-lars.povlsen@microchip.com>

[-- Attachment #1: Type: text/plain, Size: 1908 bytes --]

Hi Lars,

I love your patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on pinctrl/devel clk/clk-next linus/master v5.7-rc5 next-20200512]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Lars-Povlsen/Adding-support-for-Microchip-Sparx5-SoC/20200514-163536
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day GCC_VERSION=9.3.0 make.cross ARCH=powerpc 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>

All warnings (new ones prefixed by >>, old ones prefixed by <<):

>> drivers/pinctrl/pinctrl-ocelot.c:28: warning: "clrsetbits" redefined
28 | #define clrsetbits(addr, clear, set)          |
In file included from include/linux/io.h:13,
from include/linux/irq.h:20,
from include/linux/gpio/driver.h:7,
from drivers/pinctrl/pinctrl-ocelot.c:10:
arch/powerpc/include/asm/io.h:849: note: this is the location of the previous definition
849 | #define clrsetbits(type, addr, clear, set)          |

vim +/clrsetbits +28 drivers/pinctrl/pinctrl-ocelot.c

    27	
  > 28	#define clrsetbits(addr, clear, set) \
    29		writel((readl(addr) & ~(clear)) | (set), (addr))
    30	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 66031 bytes --]

WARNING: multiple messages have this Message-ID (diff)
From: kbuild test robot <lkp@intel.com>
To: Lars Povlsen <lars.povlsen@microchip.com>,
	SoC Team <soc@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
	Stephen Boyd <sboyd@kernel.org>,
	Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree@vger.kernel.org, kbuild-all@lists.01.org,
	Steen Hegelund <Steen.Hegelund@microchip.com>,
	linux-clk@vger.kernel.org,
	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
	linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Olof Johansson <olof@lixom.net>,
	Michael Turquette <mturquette@baylibre.com>,
	Lars Povlsen <lars.povlsen@microchip.com>
Subject: Re: [PATCH 09/14] pinctrl: ocelot: Add Sparx5 SoC support
Date: Fri, 15 May 2020 02:09:07 +0800	[thread overview]
Message-ID: <202005150200.wnjISCrm%lkp@intel.com> (raw)
In-Reply-To: <20200513125532.24585-10-lars.povlsen@microchip.com>

[-- Attachment #1: Type: text/plain, Size: 1908 bytes --]

Hi Lars,

I love your patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on pinctrl/devel clk/clk-next linus/master v5.7-rc5 next-20200512]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Lars-Povlsen/Adding-support-for-Microchip-Sparx5-SoC/20200514-163536
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day GCC_VERSION=9.3.0 make.cross ARCH=powerpc 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>

All warnings (new ones prefixed by >>, old ones prefixed by <<):

>> drivers/pinctrl/pinctrl-ocelot.c:28: warning: "clrsetbits" redefined
28 | #define clrsetbits(addr, clear, set)          |
In file included from include/linux/io.h:13,
from include/linux/irq.h:20,
from include/linux/gpio/driver.h:7,
from drivers/pinctrl/pinctrl-ocelot.c:10:
arch/powerpc/include/asm/io.h:849: note: this is the location of the previous definition
849 | #define clrsetbits(type, addr, clear, set)          |

vim +/clrsetbits +28 drivers/pinctrl/pinctrl-ocelot.c

    27	
  > 28	#define clrsetbits(addr, clear, set) \
    29		writel((readl(addr) & ~(clear)) | (set), (addr))
    30	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 66031 bytes --]

[-- Attachment #3: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: kbuild test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH 09/14] pinctrl: ocelot: Add Sparx5 SoC support
Date: Fri, 15 May 2020 02:09:07 +0800	[thread overview]
Message-ID: <202005150200.wnjISCrm%lkp@intel.com> (raw)
In-Reply-To: <20200513125532.24585-10-lars.povlsen@microchip.com>

[-- Attachment #1: Type: text/plain, Size: 1954 bytes --]

Hi Lars,

I love your patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on pinctrl/devel clk/clk-next linus/master v5.7-rc5 next-20200512]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Lars-Povlsen/Adding-support-for-Microchip-Sparx5-SoC/20200514-163536
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day GCC_VERSION=9.3.0 make.cross ARCH=powerpc 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>

All warnings (new ones prefixed by >>, old ones prefixed by <<):

>> drivers/pinctrl/pinctrl-ocelot.c:28: warning: "clrsetbits" redefined
28 | #define clrsetbits(addr, clear, set)          |
In file included from include/linux/io.h:13,
from include/linux/irq.h:20,
from include/linux/gpio/driver.h:7,
from drivers/pinctrl/pinctrl-ocelot.c:10:
arch/powerpc/include/asm/io.h:849: note: this is the location of the previous definition
849 | #define clrsetbits(type, addr, clear, set)          |

vim +/clrsetbits +28 drivers/pinctrl/pinctrl-ocelot.c

    27	
  > 28	#define clrsetbits(addr, clear, set) \
    29		writel((readl(addr) & ~(clear)) | (set), (addr))
    30	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 66031 bytes --]

  reply	other threads:[~2020-05-14 18:49 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-13 12:55 [PATCH 00/14] Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-05-13 12:55 ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 01/14] pinctrl: ocelot: Should register GPIO's even if not irq controller Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-18  7:29   ` Linus Walleij
2020-05-18  7:29     ` Linus Walleij
2020-05-13 12:55 ` [PATCH 02/14] pinctrl: ocelot: Remove instance number from pin functions Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-18  7:31   ` Linus Walleij
2020-05-18  7:31     ` Linus Walleij
2020-05-13 12:55 ` [PATCH 03/14] pinctrl: ocelot: Fix GPIO interrupt decoding on Jaguar2 Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-18  7:31   ` Linus Walleij
2020-05-18  7:31     ` Linus Walleij
2020-05-13 12:55 ` [PATCH 04/14] arm64: sparx5: Add support for Microchip 2xA53 SoC Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 05/14] dt-bindings: arm: sparx5: Add documentation for Microchip Sparx5 SoC Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-28  2:11   ` Rob Herring
2020-05-28  2:11     ` Rob Herring
2020-06-02  9:10     ` Lars Povlsen
2020-06-02  9:10       ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 06/14] arm64: dts: sparx5: Add basic cpu support Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-13 15:39   ` Marc Zyngier
2020-05-13 15:39     ` Marc Zyngier
2020-05-15 15:09     ` Lars Povlsen
2020-05-15 15:09       ` Lars Povlsen
2020-05-15 15:30       ` Robin Murphy
2020-05-15 15:30         ` Robin Murphy
2020-05-18  7:43         ` Lars Povlsen
2020-05-18  7:43           ` Lars Povlsen
2020-05-15 16:31       ` Marc Zyngier
2020-05-13 12:55 ` [PATCH 07/14] dt-bindings: pinctrl: ocelot: Add Sparx5 SoC support Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-18  7:33   ` Linus Walleij
2020-05-18  7:33     ` Linus Walleij
2020-05-13 12:55 ` [PATCH 08/14] arm64: dts: sparx5: Add pinctrl support Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 09/14] pinctrl: ocelot: Add Sparx5 SoC support Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-14 18:09   ` kbuild test robot [this message]
2020-05-14 18:09     ` kbuild test robot
2020-05-14 18:09     ` kbuild test robot
2020-05-15 15:52     ` Lars Povlsen
2020-05-15 15:52       ` Lars Povlsen
2020-05-15 15:52       ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 10/14] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-27  2:46   ` Stephen Boyd
2020-05-29 14:04     ` Lars Povlsen
2020-05-29 14:04       ` Lars Povlsen
2020-05-28  2:18   ` Rob Herring
2020-05-28  2:18     ` Rob Herring
2020-06-02  8:39     ` Lars Povlsen
2020-06-02  8:39       ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 11/14] dt-bindings: clock: sparx5: Add bindings include file Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-27  2:56   ` Stephen Boyd
2020-05-13 12:55 ` [PATCH 12/14] clk: sparx5: Add Sparx5 SoC DPLL clock driver Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-27  2:56   ` Stephen Boyd
2020-05-27 14:29     ` Lars Povlsen
2020-05-27 14:29       ` Lars Povlsen
2020-05-27 19:08       ` Stephen Boyd
2020-05-13 12:55 ` [PATCH 13/14] arm64: dts: sparx5: Add Sparx5 SoC DPLL clock Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 14/14] arm64: dts: sparx5: Add i2c devices, i2c muxes Lars Povlsen
2020-05-13 12:55   ` Lars Povlsen
2020-05-21 10:16 ` [PATCH 00/14] Adding support for Microchip Sparx5 SoC Arnd Bergmann
2020-05-21 10:16   ` Arnd Bergmann

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