* [PATCH] drm/i915: Include asm sources for {ivb,hsw}_clear_kernel.c
@ 2020-06-08 17:46 ` Rodrigo Vivi
0 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Vivi @ 2020-06-08 17:46 UTC (permalink / raw)
To: intel-gfx
Cc: Rodrigo Vivi, stable, Alexandre Oliva, Prathap Kumar Valsan,
Akeem G Abodunrin, Mika Kuoppala, Chris Wilson, Jani Nikula,
Joonas Lahtinen
Alexandre Oliva has recently removed these files from Linux Libre
with concerns that the sources weren't available.
The sources are available on IGT repository, and only open source
tools are used to generate the {ivb,hsw}_clear_kernel.c files.
However, the remaining concern from Alexandre Oliva was around
GPL license and the source not been present when distributing
the code.
So, it looks like 2 alternatives are possible, the use of
linux-firmware.git repository to store the blob or making sure
that the source is also present in our tree. Since the goal
is to limit the i915 firmware to only the micro-controller blobs
let's make sure that we do include the asm sources here in our tree.
Btw, I tried to have some diligence here and make sure that the
asms that these commits are adding are truly the source for
the mentioned files:
./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
igt$ ./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
Output file not specified - using default file "ivb-cb_assembled"
Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c" for i915 driver...
igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c ivb_clear_kernel.c
5c5
< * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC
---
> * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT
61c61
< };
---
> };
\ No newline at end of file
igt$ ./scripts/generate_clear_kernel.sh -g hsw -m /hom
e/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
Output file not specified - using default file "hsw-cb_assembled"
Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c" for i915 driver...
igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c hsw_clear_kernel.c
5c5
< * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC
---
> * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT
61c61
< };
---
> };
\ No newline at end of file
Used IGT and Mesa master repositories from Fri Jun 5 2020)
IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging the connector")
Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with RADV_DEBUG=shaderstats")
Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 -D gallium-drivers=iris -D prefix=/usr -D libdir=/usr/lib64/ -Dtools=intel -Dkulkan-drivers=intel && ninja -C build
Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003374.html
Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003375.html
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Cc: <stable@vger.kernel.org> # v5.7+
Cc: Alexandre Oliva <lxoliva@fsfla.org>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/gt/shaders/clear_kernel/hsw.asm | 141 ++++++++++++++++++
.../drm/i915/gt/shaders/clear_kernel/ivb.asm | 139 +++++++++++++++++
2 files changed, 280 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
new file mode 100644
index 000000000000..bc29baf22c61
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/**
+ * Kernel name: hsw_clear_buf.asm
+ *
+ * Kernel for PAVP buffer clear.
+ *
+ * 1. Clear all 64 GRF registers assigned to the kernel with designated value;
+ * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
+ * 512 bytes of Render Cache.
+ */
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/**
+ * Curbe Format
+ *
+ * DW 1.0 - Block Offset to write Render Cache
+ * DW 1.1 [15:0] - Clear Word
+ * DW 1.2 - Delay iterations
+ * DW 1.3 - Enable Instrumentation (only for debug)
+ * DW 1.4 - Rsvd (intended for context ID)
+ * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
+ * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
+ * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
+ *
+ * Binding Table
+ *
+ * BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
+ * BTI 1: Wait/Instrumentation Buffer
+ * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
+ * Expected to be initialized to 0 by driver/another kernel
+ * Layout:
+ * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
+ * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
+ */
+add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
+cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
+(+f0.0) jmpi(1) 352D { align1 WE_all 1N };
+
+/**
+ * State Register has info on where this thread is running
+ * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ */
+mov(8) g3<1>UD 0x00000000UD { align1 1Q };
+shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
+and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
+shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
+and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
+mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
+add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
+shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
+and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
+mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
+add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
+
+mov(8) g5<1>UD 0x00000000UD { align1 1Q };
+and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
+mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
+
+mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
+mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
+and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
+
+/* Media block read to fetch current value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
+
+ render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
+add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
+
+/* Media block write for updated value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
+
+/* Delay thread for specified parameter */
+add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
+(+f0.0) jmpi(1) -32D { align1 WE_all 1N };
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/* Initialize looping parameters */
+mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
+mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
+
+/* Write 32x16 all "0" block */
+mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
+mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
+mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
+mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
+and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
+mov(16) g3<1>UD 0x00000000UD { align1 1H };
+mov(16) g4<1>UD 0x00000000UD { align1 1H };
+mov(16) g5<1>UD 0x00000000UD { align1 1H };
+mov(16) g6<1>UD 0x00000000UD { align1 1H };
+mov(16) g7<1>UD 0x00000000UD { align1 1H };
+mov(16) g8<1>UD 0x00000000UD { align1 1H };
+mov(16) g9<1>UD 0x00000000UD { align1 1H };
+mov(16) g10<1>UD 0x00000000UD { align1 1H };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+
+/* Now, clear all GRF registers */
+add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
+mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
+add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
+(+f0.0) jmpi(1) -64D { align1 WE_all 1N };
+
+/* Terminante the thread */
+sendc(8) null<1>UD g127<8,8,1>F 0x82000010
+ thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
new file mode 100644
index 000000000000..b21bc9489061
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/**
+ * Kernel name: ivb_clear_buf.asm
+ *
+ * Kernel for PAVP buffer clear.
+ *
+ * 1. Clear all 64 GRF registers assigned to the kernel with designated value;
+ * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
+ * 512 bytes of Render Cache.
+ */
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/**
+ * Curbe Format
+ *
+ * DW 1.0 - Block Offset to write Render Cache
+ * DW 1.1 [15:0] - Clear Word
+ * DW 1.2 - Delay iterations
+ * DW 1.3 - Enable Instrumentation (only for debug)
+ * DW 1.4 - Rsvd (intended for context ID)
+ * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
+ * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
+ * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
+ *
+ * Binding Table
+ *
+ * BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
+ * BTI 1: Wait/Instrumentation Buffer
+ * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
+ * Expected to be initialized to 0 by driver/another kernel
+ * Layout :
+ * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
+ * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
+ */
+add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
+cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
+(+f0.0) jmpi(1) 44D { align1 WE_all 1N };
+
+/**
+ * State Register has info on where this thread is running
+ * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ */
+mov(8) g3<1>UD 0x00000000UD { align1 1Q };
+shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
+and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
+shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
+and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
+mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
+add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
+shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
+and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
+mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
+add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
+
+mov(8) g5<1>UD 0x00000000UD { align1 1Q };
+and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
+mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
+
+mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
+mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
+and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
+
+/* Media block read to fetch current value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
+ render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
+add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
+
+/* Media block write for updated value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
+/* Delay thread for specified parameter */
+add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
+(+f0.0) jmpi(1) -4D { align1 WE_all 1N };
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/* Initialize looping parameters */
+mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
+mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
+
+/* Write 32x16 all "0" block */
+mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
+mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
+mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
+mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
+and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
+mov(16) g3<1>UD 0x00000000UD { align1 1H };
+mov(16) g4<1>UD 0x00000000UD { align1 1H };
+mov(16) g5<1>UD 0x00000000UD { align1 1H };
+mov(16) g6<1>UD 0x00000000UD { align1 1H };
+mov(16) g7<1>UD 0x00000000UD { align1 1H };
+mov(16) g8<1>UD 0x00000000UD { align1 1H };
+mov(16) g9<1>UD 0x00000000UD { align1 1H };
+mov(16) g10<1>UD 0x00000000UD { align1 1H };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+
+/* Now, clear all GRF registers */
+add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
+mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
+add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
+(+f0.0) jmpi(1) -8D { align1 WE_all 1N };
+
+/* Terminante the thread */
+sendc(8) null<1>UD g127<8,8,1>F 0x82000010
+ thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
@ 2020-06-08 17:46 ` Rodrigo Vivi
0 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Vivi @ 2020-06-08 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Alexandre Oliva, Jani Nikula, stable, Chris Wilson
Alexandre Oliva has recently removed these files from Linux Libre
with concerns that the sources weren't available.
The sources are available on IGT repository, and only open source
tools are used to generate the {ivb,hsw}_clear_kernel.c files.
However, the remaining concern from Alexandre Oliva was around
GPL license and the source not been present when distributing
the code.
So, it looks like 2 alternatives are possible, the use of
linux-firmware.git repository to store the blob or making sure
that the source is also present in our tree. Since the goal
is to limit the i915 firmware to only the micro-controller blobs
let's make sure that we do include the asm sources here in our tree.
Btw, I tried to have some diligence here and make sure that the
asms that these commits are adding are truly the source for
the mentioned files:
./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
igt$ ./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
Output file not specified - using default file "ivb-cb_assembled"
Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c" for i915 driver...
igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c ivb_clear_kernel.c
5c5
< * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC
---
> * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT
61c61
< };
---
> };
\ No newline at end of file
igt$ ./scripts/generate_clear_kernel.sh -g hsw -m /hom
e/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
Output file not specified - using default file "hsw-cb_assembled"
Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c" for i915 driver...
igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c hsw_clear_kernel.c
5c5
< * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC
---
> * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT
61c61
< };
---
> };
\ No newline at end of file
Used IGT and Mesa master repositories from Fri Jun 5 2020)
IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging the connector")
Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with RADV_DEBUG=shaderstats")
Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 -D gallium-drivers=iris -D prefix=/usr -D libdir=/usr/lib64/ -Dtools=intel -Dkulkan-drivers=intel && ninja -C build
Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003374.html
Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003375.html
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Cc: <stable@vger.kernel.org> # v5.7+
Cc: Alexandre Oliva <lxoliva@fsfla.org>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/gt/shaders/clear_kernel/hsw.asm | 141 ++++++++++++++++++
.../drm/i915/gt/shaders/clear_kernel/ivb.asm | 139 +++++++++++++++++
2 files changed, 280 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
new file mode 100644
index 000000000000..bc29baf22c61
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/**
+ * Kernel name: hsw_clear_buf.asm
+ *
+ * Kernel for PAVP buffer clear.
+ *
+ * 1. Clear all 64 GRF registers assigned to the kernel with designated value;
+ * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
+ * 512 bytes of Render Cache.
+ */
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/**
+ * Curbe Format
+ *
+ * DW 1.0 - Block Offset to write Render Cache
+ * DW 1.1 [15:0] - Clear Word
+ * DW 1.2 - Delay iterations
+ * DW 1.3 - Enable Instrumentation (only for debug)
+ * DW 1.4 - Rsvd (intended for context ID)
+ * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
+ * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
+ * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
+ *
+ * Binding Table
+ *
+ * BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
+ * BTI 1: Wait/Instrumentation Buffer
+ * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
+ * Expected to be initialized to 0 by driver/another kernel
+ * Layout:
+ * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
+ * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
+ */
+add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
+cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
+(+f0.0) jmpi(1) 352D { align1 WE_all 1N };
+
+/**
+ * State Register has info on where this thread is running
+ * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ */
+mov(8) g3<1>UD 0x00000000UD { align1 1Q };
+shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
+and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
+shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
+and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
+mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
+add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
+shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
+and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
+mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
+add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
+
+mov(8) g5<1>UD 0x00000000UD { align1 1Q };
+and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
+mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
+
+mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
+mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
+and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
+
+/* Media block read to fetch current value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
+
+ render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
+add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
+
+/* Media block write for updated value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
+
+/* Delay thread for specified parameter */
+add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
+(+f0.0) jmpi(1) -32D { align1 WE_all 1N };
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/* Initialize looping parameters */
+mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
+mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
+
+/* Write 32x16 all "0" block */
+mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
+mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
+mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
+mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
+and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
+mov(16) g3<1>UD 0x00000000UD { align1 1H };
+mov(16) g4<1>UD 0x00000000UD { align1 1H };
+mov(16) g5<1>UD 0x00000000UD { align1 1H };
+mov(16) g6<1>UD 0x00000000UD { align1 1H };
+mov(16) g7<1>UD 0x00000000UD { align1 1H };
+mov(16) g8<1>UD 0x00000000UD { align1 1H };
+mov(16) g9<1>UD 0x00000000UD { align1 1H };
+mov(16) g10<1>UD 0x00000000UD { align1 1H };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+
+/* Now, clear all GRF registers */
+add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
+mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
+add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
+(+f0.0) jmpi(1) -64D { align1 WE_all 1N };
+
+/* Terminante the thread */
+sendc(8) null<1>UD g127<8,8,1>F 0x82000010
+ thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
new file mode 100644
index 000000000000..b21bc9489061
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/**
+ * Kernel name: ivb_clear_buf.asm
+ *
+ * Kernel for PAVP buffer clear.
+ *
+ * 1. Clear all 64 GRF registers assigned to the kernel with designated value;
+ * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
+ * 512 bytes of Render Cache.
+ */
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/**
+ * Curbe Format
+ *
+ * DW 1.0 - Block Offset to write Render Cache
+ * DW 1.1 [15:0] - Clear Word
+ * DW 1.2 - Delay iterations
+ * DW 1.3 - Enable Instrumentation (only for debug)
+ * DW 1.4 - Rsvd (intended for context ID)
+ * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
+ * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
+ * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
+ *
+ * Binding Table
+ *
+ * BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
+ * BTI 1: Wait/Instrumentation Buffer
+ * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
+ * Expected to be initialized to 0 by driver/another kernel
+ * Layout :
+ * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
+ * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
+ */
+add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
+cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
+(+f0.0) jmpi(1) 44D { align1 WE_all 1N };
+
+/**
+ * State Register has info on where this thread is running
+ * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ */
+mov(8) g3<1>UD 0x00000000UD { align1 1Q };
+shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
+and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
+shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
+and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
+mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
+add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
+shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
+and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
+mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
+add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
+
+mov(8) g5<1>UD 0x00000000UD { align1 1Q };
+and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
+mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
+
+mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
+mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
+and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
+
+/* Media block read to fetch current value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
+ render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
+add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
+
+/* Media block write for updated value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
+/* Delay thread for specified parameter */
+add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
+(+f0.0) jmpi(1) -4D { align1 WE_all 1N };
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/* Initialize looping parameters */
+mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
+mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
+
+/* Write 32x16 all "0" block */
+mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
+mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
+mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
+mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
+and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
+mov(16) g3<1>UD 0x00000000UD { align1 1H };
+mov(16) g4<1>UD 0x00000000UD { align1 1H };
+mov(16) g5<1>UD 0x00000000UD { align1 1H };
+mov(16) g6<1>UD 0x00000000UD { align1 1H };
+mov(16) g7<1>UD 0x00000000UD { align1 1H };
+mov(16) g8<1>UD 0x00000000UD { align1 1H };
+mov(16) g9<1>UD 0x00000000UD { align1 1H };
+mov(16) g10<1>UD 0x00000000UD { align1 1H };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+
+/* Now, clear all GRF registers */
+add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
+mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
+add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
+(+f0.0) jmpi(1) -8D { align1 WE_all 1N };
+
+/* Terminante the thread */
+sendc(8) null<1>UD g127<8,8,1>F 0x82000010
+ thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
2020-06-08 17:46 ` [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c Rodrigo Vivi
(?)
@ 2020-06-08 18:10 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2020-06-08 18:10 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
URL : https://patchwork.freedesktop.org/series/78126/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
62de4aea38dc drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
-:26: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#26:
./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
-:33: WARNING:USE_RELATIVE_PATH: use relative pathname instead of absolute in changelog text
#33:
igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c ivb_clear_kernel.c
-:38: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#38:
new file mode 100644
-:328: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 1 errors, 3 warnings, 0 checks, 280 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
2020-06-08 17:46 ` [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c Rodrigo Vivi
@ 2020-06-08 18:11 ` Chris Wilson
-1 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2020-06-08 18:11 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx; +Cc: Alexandre Oliva, Jani Nikula, stable
Quoting Rodrigo Vivi (2020-06-08 18:46:53)
> Alexandre Oliva has recently removed these files from Linux Libre
> with concerns that the sources weren't available.
>
> The sources are available on IGT repository, and only open source
> tools are used to generate the {ivb,hsw}_clear_kernel.c files.
>
> However, the remaining concern from Alexandre Oliva was around
> GPL license and the source not been present when distributing
> the code.
>
> So, it looks like 2 alternatives are possible, the use of
> linux-firmware.git repository to store the blob or making sure
> that the source is also present in our tree. Since the goal
> is to limit the i915 firmware to only the micro-controller blobs
> let's make sure that we do include the asm sources here in our tree.
>
> Btw, I tried to have some diligence here and make sure that the
> asms that these commits are adding are truly the source for
> the mentioned files:
>
> ./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
>
> igt$ ./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
> Output file not specified - using default file "ivb-cb_assembled"
>
> Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c" for i915 driver...
>
> igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c ivb_clear_kernel.c
> 5c5
> < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC
> ---
> > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT
> 61c61
> < };
> ---
> > };
> \ No newline at end of file
>
> igt$ ./scripts/generate_clear_kernel.sh -g hsw -m /hom
> e/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
> Output file not specified - using default file "hsw-cb_assembled"
>
> Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c" for i915 driver...
>
> igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c hsw_clear_kernel.c
> 5c5
> < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC
> ---
> > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT
> 61c61
> < };
> ---
> > };
> \ No newline at end of file
>
> Used IGT and Mesa master repositories from Fri Jun 5 2020)
> IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging the connector")
> Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with RADV_DEBUG=shaderstats")
> Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 -D gallium-drivers=iris -D prefix=/usr -D libdir=/usr/lib64/ -Dtools=intel -Dkulkan-drivers=intel && ninja -C build
>
> Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003374.html
> Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003375.html
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Cc: <stable@vger.kernel.org> # v5.7+
> Cc: Alexandre Oliva <lxoliva@fsfla.org>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> .../drm/i915/gt/shaders/clear_kernel/hsw.asm | 141 ++++++++++++++++++
> .../drm/i915/gt/shaders/clear_kernel/ivb.asm | 139 +++++++++++++++++
> 2 files changed, 280 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
> create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
>
> diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
> new file mode 100644
> index 000000000000..bc29baf22c61
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
> @@ -0,0 +1,141 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
You already said it was MIT, you don't need to duplicate the copyright
statement.
Should there not be instructions on how to generate the object code?
shaders/readme?
-Chris
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
@ 2020-06-08 18:11 ` Chris Wilson
0 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2020-06-08 18:11 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx; +Cc: Jani Nikula, Alexandre Oliva, stable
Quoting Rodrigo Vivi (2020-06-08 18:46:53)
> Alexandre Oliva has recently removed these files from Linux Libre
> with concerns that the sources weren't available.
>
> The sources are available on IGT repository, and only open source
> tools are used to generate the {ivb,hsw}_clear_kernel.c files.
>
> However, the remaining concern from Alexandre Oliva was around
> GPL license and the source not been present when distributing
> the code.
>
> So, it looks like 2 alternatives are possible, the use of
> linux-firmware.git repository to store the blob or making sure
> that the source is also present in our tree. Since the goal
> is to limit the i915 firmware to only the micro-controller blobs
> let's make sure that we do include the asm sources here in our tree.
>
> Btw, I tried to have some diligence here and make sure that the
> asms that these commits are adding are truly the source for
> the mentioned files:
>
> ./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
>
> igt$ ./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
> Output file not specified - using default file "ivb-cb_assembled"
>
> Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c" for i915 driver...
>
> igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c ivb_clear_kernel.c
> 5c5
> < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC
> ---
> > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT
> 61c61
> < };
> ---
> > };
> \ No newline at end of file
>
> igt$ ./scripts/generate_clear_kernel.sh -g hsw -m /hom
> e/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm
> Output file not specified - using default file "hsw-cb_assembled"
>
> Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c" for i915 driver...
>
> igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c hsw_clear_kernel.c
> 5c5
> < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC
> ---
> > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT
> 61c61
> < };
> ---
> > };
> \ No newline at end of file
>
> Used IGT and Mesa master repositories from Fri Jun 5 2020)
> IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging the connector")
> Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with RADV_DEBUG=shaderstats")
> Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 -D gallium-drivers=iris -D prefix=/usr -D libdir=/usr/lib64/ -Dtools=intel -Dkulkan-drivers=intel && ninja -C build
>
> Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003374.html
> Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003375.html
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Cc: <stable@vger.kernel.org> # v5.7+
> Cc: Alexandre Oliva <lxoliva@fsfla.org>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> .../drm/i915/gt/shaders/clear_kernel/hsw.asm | 141 ++++++++++++++++++
> .../drm/i915/gt/shaders/clear_kernel/ivb.asm | 139 +++++++++++++++++
> 2 files changed, 280 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
> create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
>
> diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
> new file mode 100644
> index 000000000000..bc29baf22c61
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
> @@ -0,0 +1,141 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
You already said it was MIT, you don't need to duplicate the copyright
statement.
Should there not be instructions on how to generate the object code?
shaders/readme?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
2020-06-08 17:46 ` [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c Rodrigo Vivi
` (2 preceding siblings ...)
(?)
@ 2020-06-08 18:32 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2020-06-08 18:32 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
URL : https://patchwork.freedesktop.org/series/78126/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8601 -> Patchwork_17910
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/index.html
Known issues
------------
Here are the changes found in Patchwork_17910 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] / [i915#95])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-glk-dsi/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-glk-dsi/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-byt-n2820: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-byt-n2820/igt@i915_module_load@reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-byt-n2820/igt@i915_module_load@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-whl-u: [DMESG-WARN][7] ([i915#95]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-byt-j1900/igt@i915_pm_rpm@basic-rte.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-byt-j1900/igt@i915_pm_rpm@basic-rte.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
#### Warnings ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: [SKIP][15] ([fdo#109271]) -> [FAIL][16] ([i915#665] / [i915#704])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][17] ([fdo#109271]) -> [DMESG-FAIL][18] ([i915#62])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#665]: https://gitlab.freedesktop.org/drm/intel/issues/665
[i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (49 -> 43)
------------------------------
Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8601 -> Patchwork_17910
CI-20190529: 20190529
CI_DRM_8601: c801ab3a923b2436d765bd7a97888715f68451cb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17910: 62de4aea38dc75f707a33f6e1efc4d2a07498d33 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
62de4aea38dc drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
2020-06-08 17:46 ` [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c Rodrigo Vivi
` (3 preceding siblings ...)
(?)
@ 2020-06-08 19:31 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2020-06-08 19:31 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
URL : https://patchwork.freedesktop.org/series/78126/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8601_full -> Patchwork_17910_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17910_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-mixed-process@rcs0:
- shard-apl: [PASS][1] -> [FAIL][2] ([i915#1528])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl8/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-apl6/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html
* igt@gem_exec_create@forked:
- shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk5/igt@gem_exec_create@forked.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-glk8/igt@gem_exec_create@forked.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][5] -> [FAIL][6] ([i915#454])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +7 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt@i915_suspend@sysfs-reader.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-apl4/igt@i915_suspend@sysfs-reader.html
* igt@kms_color@pipe-c-ctm-0-25:
- shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl3/igt@kms_color@pipe-c-ctm-0-25.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl5/igt@kms_color@pipe-c-ctm-0-25.html
* igt@kms_color@pipe-c-ctm-blue-to-red:
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#93] / [i915#95])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt@kms_color@pipe-c-ctm-blue-to-red.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-kbl7/igt@kms_color@pipe-c-ctm-blue-to-red.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([i915#61])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-hsw8/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-hsw8/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#95]) +11 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-apl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_rmfb@rmfb-ioctl:
- shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-snb1/igt@kms_rmfb@rmfb-ioctl.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-snb2/igt@kms_rmfb@rmfb-ioctl.html
#### Possible fixes ####
* {igt@gem_exec_reloc@basic-concurrent0}:
- shard-glk: [FAIL][23] ([i915#1930]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk6/igt@gem_exec_reloc@basic-concurrent0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-glk6/igt@gem_exec_reloc@basic-concurrent0.html
* igt@gem_exec_whisper@basic-queues-forked:
- shard-glk: [DMESG-WARN][25] ([i915#118] / [i915#95]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk9/igt@gem_exec_whisper@basic-queues-forked.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-glk5/igt@gem_exec_whisper@basic-queues-forked.html
* igt@gem_mmap_gtt@fault-concurrent:
- shard-skl: [CRASH][27] -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt@gem_mmap_gtt@fault-concurrent.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl5/igt@gem_mmap_gtt@fault-concurrent.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- shard-glk: [DMESG-FAIL][29] ([i915#118] / [i915#95]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-glk7/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding:
- shard-skl: [FAIL][31] ([i915#54]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* {igt@kms_flip@2x-blocking-wf_vblank@ab-hdmi-a1-hdmi-a2}:
- shard-glk: [FAIL][35] ([i915#1928]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk5/igt@kms_flip@2x-blocking-wf_vblank@ab-hdmi-a1-hdmi-a2.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-glk9/igt@kms_flip@2x-blocking-wf_vblank@ab-hdmi-a1-hdmi-a2.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1}:
- shard-kbl: [FAIL][37] ([i915#79]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
* {igt@kms_flip@flip-vs-suspend@a-edp1}:
- shard-skl: [INCOMPLETE][39] ([i915#198]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl4/igt@kms_flip@flip-vs-suspend@a-edp1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl2/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_flip_tiling@flip-y-tiled:
- shard-skl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +9 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl9/igt@kms_flip_tiling@flip-y-tiled.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl4/igt@kms_flip_tiling@flip-y-tiled.html
* igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
- shard-iclb: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb3/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-iclb8/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][45] ([i915#1188]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_lease@page_flip_implicit_plane:
- shard-snb: [TIMEOUT][47] ([i915#1958]) -> [PASS][48] +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-snb5/igt@kms_lease@page_flip_implicit_plane.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-snb2/igt@kms_lease@page_flip_implicit_plane.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-mid:
- shard-apl: [DMESG-WARN][49] ([i915#95]) -> [PASS][50] +16 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-apl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][51] ([fdo#108145] / [i915#265]) -> [PASS][52] +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +3 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-kbl: [INCOMPLETE][55] ([i915#155]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-kbl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* {igt@perf@blocking-parameterized}:
- shard-iclb: [FAIL][57] ([i915#1542]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb3/igt@perf@blocking-parameterized.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-iclb8/igt@perf@blocking-parameterized.html
* igt@syncobj_wait@multi-wait-all-for-submit-signaled:
- shard-tglb: [DMESG-WARN][59] ([i915#402]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb3/igt@syncobj_wait@multi-wait-all-for-submit-signaled.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-tglb8/igt@syncobj_wait@multi-wait-all-for-submit-signaled.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][61] ([i915#588]) -> [SKIP][62] ([i915#658])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_color@pipe-a-degamma:
- shard-tglb: [FAIL][63] ([i915#1149] / [i915#1897]) -> [DMESG-FAIL][64] ([i915#1149] / [i915#402])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb7/igt@kms_color@pipe-a-degamma.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-tglb8/igt@kms_color@pipe-a-degamma.html
* igt@kms_content_protection@atomic:
- shard-apl: [TIMEOUT][65] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][66] ([fdo#110321] / [i915#95])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl4/igt@kms_content_protection@atomic.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-apl7/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@legacy:
- shard-kbl: [TIMEOUT][67] ([i915#1319]) -> [TIMEOUT][68] ([i915#1319] / [i915#1958])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl1/igt@kms_content_protection@legacy.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-kbl4/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@srm:
- shard-apl: [TIMEOUT][69] ([i915#1319] / [i915#1635]) -> [TIMEOUT][70] ([i915#1319])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt@kms_content_protection@srm.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-apl8/igt@kms_content_protection@srm.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-skl: [FAIL][71] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][72] ([fdo#108145] / [i915#1982])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_psr@suspend:
- shard-snb: [TIMEOUT][73] ([i915#1958]) -> [SKIP][74] ([fdo#109271]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-snb5/igt@kms_psr@suspend.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-snb2/igt@kms_psr@suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519
[i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1897]: https://gitlab.freedesktop.org/drm/intel/issues/1897
[i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8601 -> Patchwork_17910
CI-20190529: 20190529
CI_DRM_8601: c801ab3a923b2436d765bd7a97888715f68451cb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17910: 62de4aea38dc75f707a33f6e1efc4d2a07498d33 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
2020-06-08 18:11 ` Chris Wilson
@ 2020-06-09 22:18 ` Alexandre Oliva
-1 siblings, 0 replies; 18+ messages in thread
From: Alexandre Oliva @ 2020-06-09 22:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: Rodrigo Vivi, intel-gfx, Jani Nikula, stable
On Jun 8, 2020, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Quoting Rodrigo Vivi (2020-06-08 18:46:53)
>> Alexandre Oliva has recently removed these files from Linux Libre
>> with concerns that the sources weren't available.
>>
>> The sources are available on IGT repository, and only open source
>> tools are used to generate the {ivb,hsw}_clear_kernel.c files.
>>
>> However, the remaining concern from Alexandre Oliva was around
>> GPL license and the source not been present when distributing
>> the code.
Thanks for looking into this, and for addressing the potential issues so
promptly.
>> let's make sure that we do include the asm sources here in our tree.
+1 having sources handy is good!
>> Btw, I tried to have some diligence here and make sure that the
>> asms that these commits are adding are truly the source for
>> the mentioned files:
Excellent!
> Should there not be instructions on how to generate the object code?
Considering that a script is used to generate it, to the point of adding
some of the comments in the output, it might be a good idea to include
it too, especially considering that scripts that control compilation are
part of the complete corresponding source code under the GNU GPL.
IMHO, a link to help users locate the assembler, as comments in the
script, would be welcome, though not mandatory IIUC. Even though such
links tend to rot over time, they at least offer encouragement to start
or carry on a search ;-)
Thanks again,
--
Alexandre Oliva, freedom fighter he/him https://FSFLA.org/blogs/lxo/
Free Software Evangelist Stallman was right, but he's left :(
GNU Toolchain Engineer Live long and free, and prosper ethically
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
@ 2020-06-09 22:18 ` Alexandre Oliva
0 siblings, 0 replies; 18+ messages in thread
From: Alexandre Oliva @ 2020-06-09 22:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: Jani Nikula, intel-gfx, stable
On Jun 8, 2020, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Quoting Rodrigo Vivi (2020-06-08 18:46:53)
>> Alexandre Oliva has recently removed these files from Linux Libre
>> with concerns that the sources weren't available.
>>
>> The sources are available on IGT repository, and only open source
>> tools are used to generate the {ivb,hsw}_clear_kernel.c files.
>>
>> However, the remaining concern from Alexandre Oliva was around
>> GPL license and the source not been present when distributing
>> the code.
Thanks for looking into this, and for addressing the potential issues so
promptly.
>> let's make sure that we do include the asm sources here in our tree.
+1 having sources handy is good!
>> Btw, I tried to have some diligence here and make sure that the
>> asms that these commits are adding are truly the source for
>> the mentioned files:
Excellent!
> Should there not be instructions on how to generate the object code?
Considering that a script is used to generate it, to the point of adding
some of the comments in the output, it might be a good idea to include
it too, especially considering that scripts that control compilation are
part of the complete corresponding source code under the GNU GPL.
IMHO, a link to help users locate the assembler, as comments in the
script, would be welcome, though not mandatory IIUC. Even though such
links tend to rot over time, they at least offer encouragement to start
or carry on a search ;-)
Thanks again,
--
Alexandre Oliva, freedom fighter he/him https://FSFLA.org/blogs/lxo/
Free Software Evangelist Stallman was right, but he's left :(
GNU Toolchain Engineer Live long and free, and prosper ethically
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH] drm/i915: Include asm sources for {ivb,hsw}_clear_kernel.c
2020-06-08 18:11 ` Chris Wilson
@ 2020-06-10 20:18 ` Rodrigo Vivi
-1 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Vivi @ 2020-06-10 20:18 UTC (permalink / raw)
To: intel-gfx
Cc: Rodrigo Vivi, stable, Alexandre Oliva, Prathap Kumar Valsan,
Akeem G Abodunrin, Mika Kuoppala, Chris Wilson, Jani Nikula,
Joonas Lahtinen
Alexandre Oliva has recently removed these files from Linux Libre
with concerns that the sources weren't available.
The sources are available on IGT repository, and only open source
tools are used to generate the {ivb,hsw}_clear_kernel.c files.
However, the remaining concern from Alexandre Oliva was around
GPL license and the source not been present when distributing
the code.
So, it looks like 2 alternatives are possible, the use of
linux-firmware.git repository to store the blob or making sure
that the source is also present in our tree. Since the goal
is to limit the i915 firmware to only the micro-controller blobs
let's make sure that we do include the asm sources here in our tree.
Btw, I tried to have some diligence here and make sure that the
asms that these commits are adding are truly the source for
the mentioned files:
igt$ ./scripts/generate_clear_kernel.sh -g ivb \
-m ~/mesa/build/src/intel/tools/i965_asm
Output file not specified - using default file "ivb-cb_assembled"
Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c"
for i915 driver...
igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c \
ivb_clear_kernel.c
< * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC
> * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT
61c61
< };
> };
\ No newline at end of file
igt$ ./scripts/generate_clear_kernel.sh -g hsw \
-m ~/mesa/build/src/intel/tools/i965_asm
Output file not specified - using default file "hsw-cb_assembled"
Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c"
for i915 driver...
igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c \
hsw_clear_kernel.c
5c5
< * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC
> * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT
61c61
< };
> };
\ No newline at end of file
Used IGT and Mesa master repositories from Fri Jun 5 2020)
IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging
the connector")
Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with
RADV_DEBUG=shaderstats")
Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 \
-D gallium-drivers=iris -D prefix=/usr \
-D libdir=/usr/lib64/ -Dtools=intel \
-Dkulkan-drivers=intel && ninja -C build
v2: Header clean-up and include build instructions in a readme (Chris)
Modified commit message to respect check-patch
Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003374.html
Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003375.html
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Cc: <stable@vger.kernel.org> # v5.7+
Cc: Alexandre Oliva <lxoliva@fsfla.org>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/shaders/README | 46 +++++++
.../drm/i915/gt/shaders/clear_kernel/hsw.asm | 119 ++++++++++++++++++
.../drm/i915/gt/shaders/clear_kernel/ivb.asm | 117 +++++++++++++++++
3 files changed, 282 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/shaders/README
create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
diff --git a/drivers/gpu/drm/i915/gt/shaders/README b/drivers/gpu/drm/i915/gt/shaders/README
new file mode 100644
index 000000000000..e7e96d7073c7
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/shaders/README
@@ -0,0 +1,46 @@
+ASM sources for auto generated shaders
+======================================
+
+The i915/gt/hsw_clear_kernel.c and i915/gt/ivb_clear_kernel.c files contain
+pre-compiled batch chunks that will clear any residual render cache during
+context switch.
+
+They are generated from their respective platform ASM files present on
+i915/gt/shaders/clear_kernel directory.
+
+The generated .c files should never be modified directly. Instead, any modification
+needs to be done on the on their respective ASM files and build instructions below
+needes to be followed.
+
+Building
+========
+
+Environment
+-----------
+
+IGT GPU tool scripts and the Mesa's i965 instruction assembler tool are used
+on building.
+
+Please make sure your Mesa tool is compiled with "-Dtools=intel" and
+"-Ddri-drivers=i965", and run this script from IGT source root directory"
+
+The instructions bellow assume:
+ * IGT gpu tools source code is located on your home directory (~) as ~/igt
+ * Mesa source code is located on your home directory (~) as ~/mesa
+ and built under the ~/mesa/build directory
+ * Linux kernel source code is under your home directory (~) as ~/linux
+
+Instructions
+------------
+
+~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm \
+ ~/igt/lib/i915/shaders/clear_kernel/ivb.asm
+~ $ cd ~/igt
+igt $ ./scripts/generate_clear_kernel.sh -g ivb \
+ -m ~/mesa/build/src/intel/tools/i965_asm
+
+~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm \
+ ~/igt/lib/i915/shaders/clear_kernel/hsw.asm
+~ $ cd ~/igt
+igt $ ./scripts/generate_clear_kernel.sh -g hsw \
+ -m ~/mesa/build/src/intel/tools/i965_asm
\ No newline at end of file
diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
new file mode 100644
index 000000000000..5fdf384bb621
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/*
+ * Kernel for PAVP buffer clear.
+ *
+ * 1. Clear all 64 GRF registers assigned to the kernel with designated value;
+ * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
+ * 512 bytes of Render Cache.
+ */
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/**
+ * Curbe Format
+ *
+ * DW 1.0 - Block Offset to write Render Cache
+ * DW 1.1 [15:0] - Clear Word
+ * DW 1.2 - Delay iterations
+ * DW 1.3 - Enable Instrumentation (only for debug)
+ * DW 1.4 - Rsvd (intended for context ID)
+ * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
+ * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
+ * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
+ *
+ * Binding Table
+ *
+ * BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
+ * BTI 1: Wait/Instrumentation Buffer
+ * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
+ * Expected to be initialized to 0 by driver/another kernel
+ * Layout:
+ * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
+ * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
+ */
+add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
+cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
+(+f0.0) jmpi(1) 352D { align1 WE_all 1N };
+
+/**
+ * State Register has info on where this thread is running
+ * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ */
+mov(8) g3<1>UD 0x00000000UD { align1 1Q };
+shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
+and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
+shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
+and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
+mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
+add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
+shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
+and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
+mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
+add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
+
+mov(8) g5<1>UD 0x00000000UD { align1 1Q };
+and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
+mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
+
+mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
+mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
+and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
+
+/* Media block read to fetch current value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
+
+ render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
+add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
+
+/* Media block write for updated value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
+
+/* Delay thread for specified parameter */
+add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
+(+f0.0) jmpi(1) -32D { align1 WE_all 1N };
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/* Initialize looping parameters */
+mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
+mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
+
+/* Write 32x16 all "0" block */
+mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
+mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
+mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
+mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
+and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
+mov(16) g3<1>UD 0x00000000UD { align1 1H };
+mov(16) g4<1>UD 0x00000000UD { align1 1H };
+mov(16) g5<1>UD 0x00000000UD { align1 1H };
+mov(16) g6<1>UD 0x00000000UD { align1 1H };
+mov(16) g7<1>UD 0x00000000UD { align1 1H };
+mov(16) g8<1>UD 0x00000000UD { align1 1H };
+mov(16) g9<1>UD 0x00000000UD { align1 1H };
+mov(16) g10<1>UD 0x00000000UD { align1 1H };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+
+/* Now, clear all GRF registers */
+add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
+mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
+add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
+(+f0.0) jmpi(1) -64D { align1 WE_all 1N };
+
+/* Terminante the thread */
+sendc(8) null<1>UD g127<8,8,1>F 0x82000010
+ thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
new file mode 100644
index 000000000000..97c7ac9e3854
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/*
+ * Kernel for PAVP buffer clear.
+ *
+ * 1. Clear all 64 GRF registers assigned to the kernel with designated value;
+ * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
+ * 512 bytes of Render Cache.
+ */
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/**
+ * Curbe Format
+ *
+ * DW 1.0 - Block Offset to write Render Cache
+ * DW 1.1 [15:0] - Clear Word
+ * DW 1.2 - Delay iterations
+ * DW 1.3 - Enable Instrumentation (only for debug)
+ * DW 1.4 - Rsvd (intended for context ID)
+ * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
+ * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
+ * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
+ *
+ * Binding Table
+ *
+ * BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
+ * BTI 1: Wait/Instrumentation Buffer
+ * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
+ * Expected to be initialized to 0 by driver/another kernel
+ * Layout :
+ * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
+ * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
+ */
+add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
+cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
+(+f0.0) jmpi(1) 44D { align1 WE_all 1N };
+
+/**
+ * State Register has info on where this thread is running
+ * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ */
+mov(8) g3<1>UD 0x00000000UD { align1 1Q };
+shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
+and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
+shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
+and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
+mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
+add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
+shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
+and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
+mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
+add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
+
+mov(8) g5<1>UD 0x00000000UD { align1 1Q };
+and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
+mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
+
+mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
+mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
+and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
+
+/* Media block read to fetch current value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
+ render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
+add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
+
+/* Media block write for updated value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
+/* Delay thread for specified parameter */
+add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
+(+f0.0) jmpi(1) -4D { align1 WE_all 1N };
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/* Initialize looping parameters */
+mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
+mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
+
+/* Write 32x16 all "0" block */
+mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
+mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
+mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
+mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
+and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
+mov(16) g3<1>UD 0x00000000UD { align1 1H };
+mov(16) g4<1>UD 0x00000000UD { align1 1H };
+mov(16) g5<1>UD 0x00000000UD { align1 1H };
+mov(16) g6<1>UD 0x00000000UD { align1 1H };
+mov(16) g7<1>UD 0x00000000UD { align1 1H };
+mov(16) g8<1>UD 0x00000000UD { align1 1H };
+mov(16) g9<1>UD 0x00000000UD { align1 1H };
+mov(16) g10<1>UD 0x00000000UD { align1 1H };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+
+/* Now, clear all GRF registers */
+add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
+mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
+add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
+(+f0.0) jmpi(1) -8D { align1 WE_all 1N };
+
+/* Terminante the thread */
+sendc(8) null<1>UD g127<8,8,1>F 0x82000010
+ thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
@ 2020-06-10 20:18 ` Rodrigo Vivi
0 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Vivi @ 2020-06-10 20:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Alexandre Oliva, Jani Nikula, stable, Chris Wilson
Alexandre Oliva has recently removed these files from Linux Libre
with concerns that the sources weren't available.
The sources are available on IGT repository, and only open source
tools are used to generate the {ivb,hsw}_clear_kernel.c files.
However, the remaining concern from Alexandre Oliva was around
GPL license and the source not been present when distributing
the code.
So, it looks like 2 alternatives are possible, the use of
linux-firmware.git repository to store the blob or making sure
that the source is also present in our tree. Since the goal
is to limit the i915 firmware to only the micro-controller blobs
let's make sure that we do include the asm sources here in our tree.
Btw, I tried to have some diligence here and make sure that the
asms that these commits are adding are truly the source for
the mentioned files:
igt$ ./scripts/generate_clear_kernel.sh -g ivb \
-m ~/mesa/build/src/intel/tools/i965_asm
Output file not specified - using default file "ivb-cb_assembled"
Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c"
for i915 driver...
igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c \
ivb_clear_kernel.c
< * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC
> * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT
61c61
< };
> };
\ No newline at end of file
igt$ ./scripts/generate_clear_kernel.sh -g hsw \
-m ~/mesa/build/src/intel/tools/i965_asm
Output file not specified - using default file "hsw-cb_assembled"
Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c"
for i915 driver...
igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c \
hsw_clear_kernel.c
5c5
< * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC
> * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT
61c61
< };
> };
\ No newline at end of file
Used IGT and Mesa master repositories from Fri Jun 5 2020)
IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging
the connector")
Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with
RADV_DEBUG=shaderstats")
Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 \
-D gallium-drivers=iris -D prefix=/usr \
-D libdir=/usr/lib64/ -Dtools=intel \
-Dkulkan-drivers=intel && ninja -C build
v2: Header clean-up and include build instructions in a readme (Chris)
Modified commit message to respect check-patch
Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003374.html
Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003375.html
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Cc: <stable@vger.kernel.org> # v5.7+
Cc: Alexandre Oliva <lxoliva@fsfla.org>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/shaders/README | 46 +++++++
.../drm/i915/gt/shaders/clear_kernel/hsw.asm | 119 ++++++++++++++++++
.../drm/i915/gt/shaders/clear_kernel/ivb.asm | 117 +++++++++++++++++
3 files changed, 282 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/shaders/README
create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
diff --git a/drivers/gpu/drm/i915/gt/shaders/README b/drivers/gpu/drm/i915/gt/shaders/README
new file mode 100644
index 000000000000..e7e96d7073c7
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/shaders/README
@@ -0,0 +1,46 @@
+ASM sources for auto generated shaders
+======================================
+
+The i915/gt/hsw_clear_kernel.c and i915/gt/ivb_clear_kernel.c files contain
+pre-compiled batch chunks that will clear any residual render cache during
+context switch.
+
+They are generated from their respective platform ASM files present on
+i915/gt/shaders/clear_kernel directory.
+
+The generated .c files should never be modified directly. Instead, any modification
+needs to be done on the on their respective ASM files and build instructions below
+needes to be followed.
+
+Building
+========
+
+Environment
+-----------
+
+IGT GPU tool scripts and the Mesa's i965 instruction assembler tool are used
+on building.
+
+Please make sure your Mesa tool is compiled with "-Dtools=intel" and
+"-Ddri-drivers=i965", and run this script from IGT source root directory"
+
+The instructions bellow assume:
+ * IGT gpu tools source code is located on your home directory (~) as ~/igt
+ * Mesa source code is located on your home directory (~) as ~/mesa
+ and built under the ~/mesa/build directory
+ * Linux kernel source code is under your home directory (~) as ~/linux
+
+Instructions
+------------
+
+~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm \
+ ~/igt/lib/i915/shaders/clear_kernel/ivb.asm
+~ $ cd ~/igt
+igt $ ./scripts/generate_clear_kernel.sh -g ivb \
+ -m ~/mesa/build/src/intel/tools/i965_asm
+
+~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm \
+ ~/igt/lib/i915/shaders/clear_kernel/hsw.asm
+~ $ cd ~/igt
+igt $ ./scripts/generate_clear_kernel.sh -g hsw \
+ -m ~/mesa/build/src/intel/tools/i965_asm
\ No newline at end of file
diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
new file mode 100644
index 000000000000..5fdf384bb621
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/*
+ * Kernel for PAVP buffer clear.
+ *
+ * 1. Clear all 64 GRF registers assigned to the kernel with designated value;
+ * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
+ * 512 bytes of Render Cache.
+ */
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/**
+ * Curbe Format
+ *
+ * DW 1.0 - Block Offset to write Render Cache
+ * DW 1.1 [15:0] - Clear Word
+ * DW 1.2 - Delay iterations
+ * DW 1.3 - Enable Instrumentation (only for debug)
+ * DW 1.4 - Rsvd (intended for context ID)
+ * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
+ * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
+ * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
+ *
+ * Binding Table
+ *
+ * BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
+ * BTI 1: Wait/Instrumentation Buffer
+ * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
+ * Expected to be initialized to 0 by driver/another kernel
+ * Layout:
+ * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
+ * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
+ */
+add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
+cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
+(+f0.0) jmpi(1) 352D { align1 WE_all 1N };
+
+/**
+ * State Register has info on where this thread is running
+ * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ */
+mov(8) g3<1>UD 0x00000000UD { align1 1Q };
+shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
+and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
+shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
+and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
+mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
+add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
+shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
+and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
+mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
+add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
+
+mov(8) g5<1>UD 0x00000000UD { align1 1Q };
+and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
+mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
+
+mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
+mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
+and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
+
+/* Media block read to fetch current value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
+
+ render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
+add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
+
+/* Media block write for updated value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
+
+/* Delay thread for specified parameter */
+add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
+(+f0.0) jmpi(1) -32D { align1 WE_all 1N };
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/* Initialize looping parameters */
+mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
+mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
+
+/* Write 32x16 all "0" block */
+mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
+mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
+mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
+mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
+and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
+mov(16) g3<1>UD 0x00000000UD { align1 1H };
+mov(16) g4<1>UD 0x00000000UD { align1 1H };
+mov(16) g5<1>UD 0x00000000UD { align1 1H };
+mov(16) g6<1>UD 0x00000000UD { align1 1H };
+mov(16) g7<1>UD 0x00000000UD { align1 1H };
+mov(16) g8<1>UD 0x00000000UD { align1 1H };
+mov(16) g9<1>UD 0x00000000UD { align1 1H };
+mov(16) g10<1>UD 0x00000000UD { align1 1H };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+
+/* Now, clear all GRF registers */
+add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
+mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
+add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
+(+f0.0) jmpi(1) -64D { align1 WE_all 1N };
+
+/* Terminante the thread */
+sendc(8) null<1>UD g127<8,8,1>F 0x82000010
+ thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
new file mode 100644
index 000000000000..97c7ac9e3854
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/*
+ * Kernel for PAVP buffer clear.
+ *
+ * 1. Clear all 64 GRF registers assigned to the kernel with designated value;
+ * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
+ * 512 bytes of Render Cache.
+ */
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/**
+ * Curbe Format
+ *
+ * DW 1.0 - Block Offset to write Render Cache
+ * DW 1.1 [15:0] - Clear Word
+ * DW 1.2 - Delay iterations
+ * DW 1.3 - Enable Instrumentation (only for debug)
+ * DW 1.4 - Rsvd (intended for context ID)
+ * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
+ * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
+ * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
+ *
+ * Binding Table
+ *
+ * BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
+ * BTI 1: Wait/Instrumentation Buffer
+ * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
+ * Expected to be initialized to 0 by driver/another kernel
+ * Layout :
+ * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
+ * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
+ */
+add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
+cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
+(+f0.0) jmpi(1) 44D { align1 WE_all 1N };
+
+/**
+ * State Register has info on where this thread is running
+ * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ */
+mov(8) g3<1>UD 0x00000000UD { align1 1Q };
+shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
+and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
+shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
+and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
+mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
+add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
+shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
+and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
+mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
+add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
+
+mov(8) g5<1>UD 0x00000000UD { align1 1Q };
+and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
+mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
+
+mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
+mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
+and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
+
+/* Media block read to fetch current value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
+ render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
+add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
+
+/* Media block write for updated value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
+/* Delay thread for specified parameter */
+add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
+(+f0.0) jmpi(1) -4D { align1 WE_all 1N };
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/* Initialize looping parameters */
+mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
+mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
+
+/* Write 32x16 all "0" block */
+mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
+mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
+mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
+mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
+and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
+mov(16) g3<1>UD 0x00000000UD { align1 1H };
+mov(16) g4<1>UD 0x00000000UD { align1 1H };
+mov(16) g5<1>UD 0x00000000UD { align1 1H };
+mov(16) g6<1>UD 0x00000000UD { align1 1H };
+mov(16) g7<1>UD 0x00000000UD { align1 1H };
+mov(16) g8<1>UD 0x00000000UD { align1 1H };
+mov(16) g9<1>UD 0x00000000UD { align1 1H };
+mov(16) g10<1>UD 0x00000000UD { align1 1H };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+
+/* Now, clear all GRF registers */
+add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
+mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
+add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
+(+f0.0) jmpi(1) -8D { align1 WE_all 1N };
+
+/* Terminante the thread */
+sendc(8) null<1>UD g127<8,8,1>F 0x82000010
+ thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c (rev2)
2020-06-08 17:46 ` [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c Rodrigo Vivi
` (4 preceding siblings ...)
(?)
@ 2020-06-10 20:47 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2020-06-10 20:47 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c (rev2)
URL : https://patchwork.freedesktop.org/series/78126/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fbdbc3448e1c drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
-:87: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#87:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 282 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c (rev2)
2020-06-08 17:46 ` [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c Rodrigo Vivi
` (5 preceding siblings ...)
(?)
@ 2020-06-10 21:08 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2020-06-10 21:08 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c (rev2)
URL : https://patchwork.freedesktop.org/series/78126/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8611 -> Patchwork_17924
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/index.html
Known issues
------------
Here are the changes found in Patchwork_17924 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-cml-s: [DMESG-WARN][1] ([i915#1982]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-cml-s/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-cml-s/igt@i915_pm_rpm@module-reload.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][3] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][9] ([fdo#109271]) -> [DMESG-FAIL][10] ([i915#62] / [i915#95])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +6 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#1982] / [i915#62] / [i915#92] / [i915#95])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (48 -> 42)
------------------------------
Additional (1): fi-kbl-7560u
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8611 -> Patchwork_17924
CI-20190529: 20190529
CI_DRM_8611: b87354483fa40fef86da19ade9bfe9349f0cf6d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17924: fbdbc3448e1c3c404e07c2aa64e972f31fad7652 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fbdbc3448e1c drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c (rev2)
2020-06-08 17:46 ` [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c Rodrigo Vivi
` (6 preceding siblings ...)
(?)
@ 2020-06-11 11:15 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2020-06-11 11:15 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c (rev2)
URL : https://patchwork.freedesktop.org/series/78126/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8611_full -> Patchwork_17924_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17924_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17924_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17924_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_endless@dispatch@rcs0:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb1/igt@gem_exec_endless@dispatch@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb7/igt@gem_exec_endless@dispatch@rcs0.html
Known issues
------------
Here are the changes found in Patchwork_17924_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-mixed-process@rcs0:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#1528])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl3/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl4/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl3/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl4/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_whisper@basic-fds-priority:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk9/igt@gem_exec_whisper@basic-fds-priority.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-glk1/igt@gem_exec_whisper@basic-fds-priority.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl8/igt@gem_workarounds@suspend-resume-context.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_dc@dc5-psr:
- shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#198])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl8/igt@i915_pm_dc@dc5-psr.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl2/igt@i915_pm_dc@dc5-psr.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl4/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl3/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#300])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-a-128x128-bottom-edge:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#93] / [i915#95])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl3/igt@kms_cursor_edge_walk@pipe-a-128x128-bottom-edge.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl4/igt@kms_cursor_edge_walk@pipe-a-128x128-bottom-edge.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][19] -> [FAIL][20] ([i915#72])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@all-pipes-torture-move:
- shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#128])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb2/igt@kms_cursor_legacy@all-pipes-torture-move.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb4/igt@kms_cursor_legacy@all-pipes-torture-move.html
* igt@kms_cursor_legacy@cursora-vs-flipa-varying-size:
- shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +7 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl1/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl2/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#95]) +25 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@perf@polling:
- shard-skl: [PASS][29] -> [FAIL][30] ([i915#1542])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl1/igt@perf@polling.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl2/igt@perf@polling.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-kbl: [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_exec_balancer@sliced:
- shard-tglb: [TIMEOUT][33] ([i915#1936]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb5/igt@gem_exec_balancer@sliced.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-tglb8/igt@gem_exec_balancer@sliced.html
* igt@gem_exec_reloc@basic-wc-cpu-active:
- shard-apl: [DMESG-WARN][35] ([i915#95]) -> [PASS][36] +18 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl4/igt@gem_exec_reloc@basic-wc-cpu-active.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl8/igt@gem_exec_reloc@basic-wc-cpu-active.html
* igt@gem_exec_schedule@implicit-read-write@rcs0:
- shard-snb: [INCOMPLETE][37] ([i915#82]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-snb2/igt@gem_exec_schedule@implicit-read-write@rcs0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-snb2/igt@gem_exec_schedule@implicit-read-write@rcs0.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [FAIL][39] ([fdo#103375]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl7/igt@i915_suspend@debugfs-reader.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl3/igt@i915_suspend@debugfs-reader.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-glk: [DMESG-FAIL][41] ([i915#118] / [i915#95]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk8/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-glk5/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen:
- shard-skl: [FAIL][43] ([i915#54]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
* igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge:
- shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl3/igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl4/igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge.html
* igt@kms_cursor_legacy@pipe-b-torture-move:
- shard-tglb: [DMESG-WARN][47] ([i915#128]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb2/igt@kms_cursor_legacy@pipe-b-torture-move.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-tglb2/igt@kms_cursor_legacy@pipe-b-torture-move.html
* igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled:
- shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +12 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl8/igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl10/igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html
* igt@kms_flip@busy-flip@b-edp1:
- shard-skl: [FAIL][51] ([i915#275]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl5/igt@kms_flip@busy-flip@b-edp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl3/igt@kms_flip@busy-flip@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-iclb: [FAIL][53] ([i915#79]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@plain-flip-ts-check@a-dp1:
- shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt@kms_flip@plain-flip-ts-check@a-dp1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl2/igt@kms_flip@plain-flip-ts-check@a-dp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][57] ([i915#1188]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [INCOMPLETE][59] ([i915#155]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-glk: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-glk5/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][65] ([fdo#109642] / [fdo#111068]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb8/igt@kms_psr2_su@page_flip.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@no_drrs:
- shard-iclb: [FAIL][67] ([i915#173]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb1/igt@kms_psr@no_drrs.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb7/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb4/igt@kms_psr@psr2_suspend.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb2/igt@kms_psr@psr2_suspend.html
* igt@perf_pmu@module-unload:
- shard-iclb: [DMESG-WARN][71] ([i915#1982]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb5/igt@perf_pmu@module-unload.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb5/igt@perf_pmu@module-unload.html
* igt@perf_pmu@other-init-3:
- shard-tglb: [DMESG-WARN][73] ([i915#402]) -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb6/igt@perf_pmu@other-init-3.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-tglb1/igt@perf_pmu@other-init-3.html
* igt@syncobj_wait@single-wait-all-for-submit-signaled:
- shard-tglb: [TIMEOUT][75] -> [PASS][76] +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb5/igt@syncobj_wait@single-wait-all-for-submit-signaled.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-tglb8/igt@syncobj_wait@single-wait-all-for-submit-signaled.html
#### Warnings ####
* igt@gem_exec_reloc@basic-concurrent16:
- shard-apl: [INCOMPLETE][77] ([i915#1635] / [i915#1958]) -> [TIMEOUT][78] ([i915#1635])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl7/igt@gem_exec_reloc@basic-concurrent16.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl2/igt@gem_exec_reloc@basic-concurrent16.html
- shard-glk: [TIMEOUT][79] ([i915#1958]) -> [INCOMPLETE][80] ([i915#1958] / [i915#58] / [k.org#198133])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk5/igt@gem_exec_reloc@basic-concurrent16.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-glk7/igt@gem_exec_reloc@basic-concurrent16.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [FAIL][81] ([i915#1515]) -> [WARN][82] ([i915#1515])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: [TIMEOUT][83] ([i915#1319]) -> [TIMEOUT][84] ([i915#1319] / [i915#1635])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl1/igt@kms_content_protection@atomic-dpms.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl3/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@legacy:
- shard-apl: [FAIL][85] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][86] ([i915#1319] / [i915#1635])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl6/igt@kms_content_protection@legacy.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl6/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@srm:
- shard-kbl: [TIMEOUT][87] ([i915#1319] / [i915#1958]) -> [TIMEOUT][88] ([i915#1319]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt@kms_content_protection@srm.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl6/igt@kms_content_protection@srm.html
- shard-apl: [DMESG-FAIL][89] ([fdo#110321] / [i915#95]) -> [TIMEOUT][90] ([i915#1319] / [i915#1635])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl4/igt@kms_content_protection@srm.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl3/igt@kms_content_protection@srm.html
* igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
- shard-apl: [DMESG-FAIL][91] ([i915#54] / [i915#95]) -> [DMESG-WARN][92] ([i915#95])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl1/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl3/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-apl: [FAIL][93] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][94] ([fdo#108145] / [i915#95])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515
[i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#275]: https://gitlab.freedesktop.org/drm/intel/issues/275
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8611 -> Patchwork_17924
CI-20190529: 20190529
CI_DRM_8611: b87354483fa40fef86da19ade9bfe9349f0cf6d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17924: fbdbc3448e1c3c404e07c2aa64e972f31fad7652 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
2020-06-10 20:18 ` [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c Rodrigo Vivi
@ 2020-06-12 21:15 ` Bloomfield, Jon
-1 siblings, 0 replies; 18+ messages in thread
From: Bloomfield, Jon @ 2020-06-12 21:15 UTC (permalink / raw)
To: Vivi, Rodrigo, intel-gfx
Cc: Alexandre Oliva, Nikula, Jani, stable, Chris Wilson
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Rodrigo Vivi
> Sent: Wednesday, June 10, 2020 1:18 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Alexandre Oliva <lxoliva@fsfla.org>; Nikula, Jani <jani.nikula@intel.com>;
> stable@vger.kernel.org; Chris Wilson <chris@chris-wilson.co.uk>
> Subject: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb,
> hsw}_clear_kernel.c
>
> Alexandre Oliva has recently removed these files from Linux Libre
> with concerns that the sources weren't available.
>
> The sources are available on IGT repository, and only open source
> tools are used to generate the {ivb,hsw}_clear_kernel.c files.
>
> However, the remaining concern from Alexandre Oliva was around
> GPL license and the source not been present when distributing
> the code.
>
> So, it looks like 2 alternatives are possible, the use of
> linux-firmware.git repository to store the blob or making sure
> that the source is also present in our tree. Since the goal
> is to limit the i915 firmware to only the micro-controller blobs
> let's make sure that we do include the asm sources here in our tree.
>
> Btw, I tried to have some diligence here and make sure that the
> asms that these commits are adding are truly the source for
> the mentioned files:
>
> igt$ ./scripts/generate_clear_kernel.sh -g ivb \
> -m ~/mesa/build/src/intel/tools/i965_asm
> Output file not specified - using default file "ivb-cb_assembled"
>
> Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c"
> for i915 driver...
>
> igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c \
> ivb_clear_kernel.c
>
> < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC
> > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT
> 61c61
> < };
> > };
> \ No newline at end of file
>
> igt$ ./scripts/generate_clear_kernel.sh -g hsw \
> -m ~/mesa/build/src/intel/tools/i965_asm
> Output file not specified - using default file "hsw-cb_assembled"
>
> Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c"
> for i915 driver...
>
> igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c \
> hsw_clear_kernel.c
> 5c5
> < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC
> > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT
> 61c61
> < };
> > };
> \ No newline at end of file
>
> Used IGT and Mesa master repositories from Fri Jun 5 2020)
> IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging
> the connector")
> Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with
> RADV_DEBUG=shaderstats")
> Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 \
> -D gallium-drivers=iris -D prefix=/usr \
> -D libdir=/usr/lib64/ -Dtools=intel \
> -Dkulkan-drivers=intel && ninja -C build
>
> v2: Header clean-up and include build instructions in a readme (Chris)
> Modified commit message to respect check-patch
>
> Reference: http://www.fsfla.org/pipermail/linux-libre/2020-
> June/003374.html
> Reference: http://www.fsfla.org/pipermail/linux-libre/2020-
> June/003375.html
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Cc: <stable@vger.kernel.org> # v5.7+
> Cc: Alexandre Oliva <lxoliva@fsfla.org>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Jon Bloomfield <jon.bloomfield@intel.com>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
@ 2020-06-12 21:15 ` Bloomfield, Jon
0 siblings, 0 replies; 18+ messages in thread
From: Bloomfield, Jon @ 2020-06-12 21:15 UTC (permalink / raw)
To: Vivi, Rodrigo, intel-gfx
Cc: Nikula, Jani, Alexandre Oliva, stable, Chris Wilson
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Rodrigo Vivi
> Sent: Wednesday, June 10, 2020 1:18 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Alexandre Oliva <lxoliva@fsfla.org>; Nikula, Jani <jani.nikula@intel.com>;
> stable@vger.kernel.org; Chris Wilson <chris@chris-wilson.co.uk>
> Subject: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb,
> hsw}_clear_kernel.c
>
> Alexandre Oliva has recently removed these files from Linux Libre
> with concerns that the sources weren't available.
>
> The sources are available on IGT repository, and only open source
> tools are used to generate the {ivb,hsw}_clear_kernel.c files.
>
> However, the remaining concern from Alexandre Oliva was around
> GPL license and the source not been present when distributing
> the code.
>
> So, it looks like 2 alternatives are possible, the use of
> linux-firmware.git repository to store the blob or making sure
> that the source is also present in our tree. Since the goal
> is to limit the i915 firmware to only the micro-controller blobs
> let's make sure that we do include the asm sources here in our tree.
>
> Btw, I tried to have some diligence here and make sure that the
> asms that these commits are adding are truly the source for
> the mentioned files:
>
> igt$ ./scripts/generate_clear_kernel.sh -g ivb \
> -m ~/mesa/build/src/intel/tools/i965_asm
> Output file not specified - using default file "ivb-cb_assembled"
>
> Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c"
> for i915 driver...
>
> igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c \
> ivb_clear_kernel.c
>
> < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC
> > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT
> 61c61
> < };
> > };
> \ No newline at end of file
>
> igt$ ./scripts/generate_clear_kernel.sh -g hsw \
> -m ~/mesa/build/src/intel/tools/i965_asm
> Output file not specified - using default file "hsw-cb_assembled"
>
> Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c"
> for i915 driver...
>
> igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c \
> hsw_clear_kernel.c
> 5c5
> < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC
> > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT
> 61c61
> < };
> > };
> \ No newline at end of file
>
> Used IGT and Mesa master repositories from Fri Jun 5 2020)
> IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging
> the connector")
> Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with
> RADV_DEBUG=shaderstats")
> Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 \
> -D gallium-drivers=iris -D prefix=/usr \
> -D libdir=/usr/lib64/ -Dtools=intel \
> -Dkulkan-drivers=intel && ninja -C build
>
> v2: Header clean-up and include build instructions in a readme (Chris)
> Modified commit message to respect check-patch
>
> Reference: http://www.fsfla.org/pipermail/linux-libre/2020-
> June/003374.html
> Reference: http://www.fsfla.org/pipermail/linux-libre/2020-
> June/003375.html
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Cc: <stable@vger.kernel.org> # v5.7+
> Cc: Alexandre Oliva <lxoliva@fsfla.org>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Jon Bloomfield <jon.bloomfield@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
2020-06-12 21:15 ` Bloomfield, Jon
@ 2020-06-15 18:54 ` Rodrigo Vivi
-1 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Vivi @ 2020-06-15 18:54 UTC (permalink / raw)
To: Bloomfield, Jon
Cc: intel-gfx, Alexandre Oliva, Nikula, Jani, stable, Chris Wilson
On Fri, Jun 12, 2020 at 02:15:02PM -0700, Bloomfield, Jon wrote:
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Rodrigo Vivi
> > Sent: Wednesday, June 10, 2020 1:18 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Alexandre Oliva <lxoliva@fsfla.org>; Nikula, Jani <jani.nikula@intel.com>;
> > stable@vger.kernel.org; Chris Wilson <chris@chris-wilson.co.uk>
> > Subject: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb,
> > hsw}_clear_kernel.c
> >
> > Alexandre Oliva has recently removed these files from Linux Libre
> > with concerns that the sources weren't available.
> >
> > The sources are available on IGT repository, and only open source
> > tools are used to generate the {ivb,hsw}_clear_kernel.c files.
> >
> > However, the remaining concern from Alexandre Oliva was around
> > GPL license and the source not been present when distributing
> > the code.
> >
> > So, it looks like 2 alternatives are possible, the use of
> > linux-firmware.git repository to store the blob or making sure
> > that the source is also present in our tree. Since the goal
> > is to limit the i915 firmware to only the micro-controller blobs
> > let's make sure that we do include the asm sources here in our tree.
> >
> > Btw, I tried to have some diligence here and make sure that the
> > asms that these commits are adding are truly the source for
> > the mentioned files:
> >
> > igt$ ./scripts/generate_clear_kernel.sh -g ivb \
> > -m ~/mesa/build/src/intel/tools/i965_asm
> > Output file not specified - using default file "ivb-cb_assembled"
> >
> > Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c"
> > for i915 driver...
> >
> > igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c \
> > ivb_clear_kernel.c
> >
> > < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC
> > > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT
> > 61c61
> > < };
> > > };
> > \ No newline at end of file
> >
> > igt$ ./scripts/generate_clear_kernel.sh -g hsw \
> > -m ~/mesa/build/src/intel/tools/i965_asm
> > Output file not specified - using default file "hsw-cb_assembled"
> >
> > Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c"
> > for i915 driver...
> >
> > igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c \
> > hsw_clear_kernel.c
> > 5c5
> > < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC
> > > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT
> > 61c61
> > < };
> > > };
> > \ No newline at end of file
> >
> > Used IGT and Mesa master repositories from Fri Jun 5 2020)
> > IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging
> > the connector")
> > Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with
> > RADV_DEBUG=shaderstats")
> > Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 \
> > -D gallium-drivers=iris -D prefix=/usr \
> > -D libdir=/usr/lib64/ -Dtools=intel \
> > -Dkulkan-drivers=intel && ninja -C build
> >
> > v2: Header clean-up and include build instructions in a readme (Chris)
> > Modified commit message to respect check-patch
> >
> > Reference: http://www.fsfla.org/pipermail/linux-libre/2020-
> > June/003374.html
> > Reference: http://www.fsfla.org/pipermail/linux-libre/2020-
> > June/003375.html
> > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> > Cc: <stable@vger.kernel.org> # v5.7+
> > Cc: Alexandre Oliva <lxoliva@fsfla.org>
> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> > Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Reviewed-by: Jon Bloomfield <jon.bloomfield@intel.com>
Thanks, pushed to dinq
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c
@ 2020-06-15 18:54 ` Rodrigo Vivi
0 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Vivi @ 2020-06-15 18:54 UTC (permalink / raw)
To: Bloomfield, Jon
Cc: Nikula, Jani, intel-gfx, Alexandre Oliva, stable, Chris Wilson
On Fri, Jun 12, 2020 at 02:15:02PM -0700, Bloomfield, Jon wrote:
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Rodrigo Vivi
> > Sent: Wednesday, June 10, 2020 1:18 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Alexandre Oliva <lxoliva@fsfla.org>; Nikula, Jani <jani.nikula@intel.com>;
> > stable@vger.kernel.org; Chris Wilson <chris@chris-wilson.co.uk>
> > Subject: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb,
> > hsw}_clear_kernel.c
> >
> > Alexandre Oliva has recently removed these files from Linux Libre
> > with concerns that the sources weren't available.
> >
> > The sources are available on IGT repository, and only open source
> > tools are used to generate the {ivb,hsw}_clear_kernel.c files.
> >
> > However, the remaining concern from Alexandre Oliva was around
> > GPL license and the source not been present when distributing
> > the code.
> >
> > So, it looks like 2 alternatives are possible, the use of
> > linux-firmware.git repository to store the blob or making sure
> > that the source is also present in our tree. Since the goal
> > is to limit the i915 firmware to only the micro-controller blobs
> > let's make sure that we do include the asm sources here in our tree.
> >
> > Btw, I tried to have some diligence here and make sure that the
> > asms that these commits are adding are truly the source for
> > the mentioned files:
> >
> > igt$ ./scripts/generate_clear_kernel.sh -g ivb \
> > -m ~/mesa/build/src/intel/tools/i965_asm
> > Output file not specified - using default file "ivb-cb_assembled"
> >
> > Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c"
> > for i915 driver...
> >
> > igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c \
> > ivb_clear_kernel.c
> >
> > < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC
> > > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT
> > 61c61
> > < };
> > > };
> > \ No newline at end of file
> >
> > igt$ ./scripts/generate_clear_kernel.sh -g hsw \
> > -m ~/mesa/build/src/intel/tools/i965_asm
> > Output file not specified - using default file "hsw-cb_assembled"
> >
> > Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c"
> > for i915 driver...
> >
> > igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c \
> > hsw_clear_kernel.c
> > 5c5
> > < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC
> > > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT
> > 61c61
> > < };
> > > };
> > \ No newline at end of file
> >
> > Used IGT and Mesa master repositories from Fri Jun 5 2020)
> > IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging
> > the connector")
> > Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with
> > RADV_DEBUG=shaderstats")
> > Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 \
> > -D gallium-drivers=iris -D prefix=/usr \
> > -D libdir=/usr/lib64/ -Dtools=intel \
> > -Dkulkan-drivers=intel && ninja -C build
> >
> > v2: Header clean-up and include build instructions in a readme (Chris)
> > Modified commit message to respect check-patch
> >
> > Reference: http://www.fsfla.org/pipermail/linux-libre/2020-
> > June/003374.html
> > Reference: http://www.fsfla.org/pipermail/linux-libre/2020-
> > June/003375.html
> > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> > Cc: <stable@vger.kernel.org> # v5.7+
> > Cc: Alexandre Oliva <lxoliva@fsfla.org>
> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> > Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Reviewed-by: Jon Bloomfield <jon.bloomfield@intel.com>
Thanks, pushed to dinq
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2020-06-15 18:56 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-08 17:46 [PATCH] drm/i915: Include asm sources for {ivb,hsw}_clear_kernel.c Rodrigo Vivi
2020-06-08 17:46 ` [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c Rodrigo Vivi
2020-06-08 18:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-06-08 18:11 ` [Intel-gfx] [PATCH] " Chris Wilson
2020-06-08 18:11 ` Chris Wilson
2020-06-09 22:18 ` Alexandre Oliva
2020-06-09 22:18 ` Alexandre Oliva
2020-06-10 20:18 ` [PATCH] drm/i915: Include asm sources for {ivb,hsw}_clear_kernel.c Rodrigo Vivi
2020-06-10 20:18 ` [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c Rodrigo Vivi
2020-06-12 21:15 ` Bloomfield, Jon
2020-06-12 21:15 ` Bloomfield, Jon
2020-06-15 18:54 ` Rodrigo Vivi
2020-06-15 18:54 ` Rodrigo Vivi
2020-06-08 18:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-06-08 19:31 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-06-10 20:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c (rev2) Patchwork
2020-06-10 21:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-11 11:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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