* [PATCHv2 00/10] pci: layerscape: Split EP mode code into a
@ 2020-07-09 15:31 Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 01/10] pci: layerscape: Split the EP and RC driver Zhiqiang Hou
` (9 more replies)
0 siblings, 10 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2020-07-09 15:31 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Hou Zhiqiang (1):
pci: layerscape: Add specific config entry for RC and EP mode driver
Xiaowei Bao (9):
pci: layerscape: Split the EP and RC driver
pci_ep: Add the init function
armv8: dts: ls1046a: Add the PCIe EP node
PCI_EP: layerscape: Add the multiple function support
pci_ep: layerscape: Add the workaround for errata A-009460
pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode
pci_ep: layerscape: Add the SRIOV VFs of PF support
pci: layerscaple: Modify the ls_pcie_dump_atu function
pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2
arch/arm/dts/fsl-ls1046a.dtsi | 33 ++
common/board_r.c | 12 +
configs/ls1012afrdm_qspi_defconfig | 2 +-
configs/ls1012afrdm_tfa_defconfig | 2 +-
.../ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls1012afrwy_qspi_defconfig | 2 +-
configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1012afrwy_tfa_defconfig | 2 +-
configs/ls1012aqds_qspi_defconfig | 2 +-
configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1012aqds_tfa_defconfig | 2 +-
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls1012ardb_qspi_defconfig | 2 +-
configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1012ardb_tfa_defconfig | 2 +-
configs/ls1021aiot_qspi_defconfig | 2 +-
configs/ls1021aiot_sdcard_defconfig | 2 +-
configs/ls1021aqds_ddr4_nor_defconfig | 2 +-
configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 2 +-
configs/ls1021aqds_nand_defconfig | 2 +-
configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 +-
configs/ls1021aqds_nor_defconfig | 2 +-
configs/ls1021aqds_nor_lpuart_defconfig | 2 +-
configs/ls1021aqds_qspi_defconfig | 2 +-
configs/ls1021aqds_sdcard_ifc_defconfig | 2 +-
configs/ls1021aqds_sdcard_qspi_defconfig | 2 +-
configs/ls1021atsn_qspi_defconfig | 2 +-
configs/ls1021atsn_sdcard_defconfig | 2 +-
configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 +-
configs/ls1021atwr_nor_defconfig | 2 +-
configs/ls1021atwr_nor_lpuart_defconfig | 2 +-
configs/ls1021atwr_qspi_defconfig | 2 +-
...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 +-
configs/ls1021atwr_sdcard_ifc_defconfig | 2 +-
configs/ls1021atwr_sdcard_qspi_defconfig | 2 +-
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1028aqds_tfa_defconfig | 2 +-
configs/ls1028aqds_tfa_lpuart_defconfig | 2 +-
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1028ardb_tfa_defconfig | 2 +-
configs/ls1043aqds_defconfig | 2 +-
configs/ls1043aqds_lpuart_defconfig | 2 +-
configs/ls1043aqds_nand_defconfig | 2 +-
configs/ls1043aqds_nor_ddr3_defconfig | 2 +-
configs/ls1043aqds_qspi_defconfig | 2 +-
configs/ls1043aqds_sdcard_ifc_defconfig | 2 +-
configs/ls1043aqds_sdcard_qspi_defconfig | 2 +-
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1043aqds_tfa_defconfig | 2 +-
configs/ls1043ardb_SECURE_BOOT_defconfig | 2 +-
configs/ls1043ardb_defconfig | 2 +-
configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 +-
configs/ls1043ardb_nand_defconfig | 2 +-
.../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 +-
configs/ls1043ardb_sdcard_defconfig | 2 +-
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1043ardb_tfa_defconfig | 2 +-
configs/ls1046afrwy_tfa_defconfig | 3 +-
configs/ls1046aqds_SECURE_BOOT_defconfig | 3 +-
configs/ls1046aqds_defconfig | 3 +-
configs/ls1046aqds_lpuart_defconfig | 3 +-
configs/ls1046aqds_nand_defconfig | 3 +-
configs/ls1046aqds_qspi_defconfig | 3 +-
configs/ls1046aqds_sdcard_ifc_defconfig | 3 +-
configs/ls1046aqds_sdcard_qspi_defconfig | 3 +-
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 3 +-
configs/ls1046aqds_tfa_defconfig | 3 +-
configs/ls1046ardb_emmc_defconfig | 3 +-
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 3 +-
configs/ls1046ardb_qspi_defconfig | 3 +-
configs/ls1046ardb_qspi_spl_defconfig | 3 +-
.../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 3 +-
configs/ls1046ardb_sdcard_defconfig | 3 +-
configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 3 +-
configs/ls1046ardb_tfa_defconfig | 3 +-
configs/ls1088aqds_defconfig | 2 +-
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls1088aqds_qspi_defconfig | 2 +-
configs/ls1088aqds_sdcard_ifc_defconfig | 2 +-
configs/ls1088aqds_sdcard_qspi_defconfig | 2 +-
configs/ls1088aqds_tfa_defconfig | 2 +-
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls1088ardb_qspi_defconfig | 2 +-
...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls1088ardb_sdcard_qspi_defconfig | 2 +-
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1088ardb_tfa_defconfig | 2 +-
configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +-
configs/ls2080aqds_defconfig | 2 +-
configs/ls2080aqds_nand_defconfig | 2 +-
configs/ls2080aqds_qspi_defconfig | 2 +-
configs/ls2080aqds_sdcard_defconfig | 2 +-
configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +-
configs/ls2080ardb_defconfig | 2 +-
configs/ls2080ardb_nand_defconfig | 2 +-
configs/ls2081ardb_defconfig | 2 +-
configs/ls2088aqds_tfa_defconfig | 2 +-
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls2088ardb_qspi_defconfig | 2 +-
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls2088ardb_tfa_defconfig | 2 +-
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 4 +-
configs/lx2160aqds_tfa_defconfig | 4 +-
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 4 +-
configs/lx2160ardb_tfa_defconfig | 4 +-
configs/lx2160ardb_tfa_stmm_defconfig | 4 +-
drivers/pci/Kconfig | 29 +-
drivers/pci/Makefile | 5 +-
drivers/pci/pcie_layerscape.c | 510 ++----------------
drivers/pci/pcie_layerscape.h | 73 ++-
drivers/pci/pcie_layerscape_ep.c | 332 ++++++++++++
drivers/pci/pcie_layerscape_fixup.c | 79 +--
drivers/pci/pcie_layerscape_rc.c | 379 +++++++++++++
drivers/pci_endpoint/pci_ep-uclass.c | 11 +
include/init.h | 1 +
115 files changed, 1073 insertions(+), 627 deletions(-)
create mode 100644 drivers/pci/pcie_layerscape_ep.c
create mode 100644 drivers/pci/pcie_layerscape_rc.c
--
2.17.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCHv2 01/10] pci: layerscape: Split the EP and RC driver
2020-07-09 15:31 [PATCHv2 00/10] pci: layerscape: Split EP mode code into a Zhiqiang Hou
@ 2020-07-09 15:31 ` Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 02/10] pci_ep: Add the init function Zhiqiang Hou
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2020-07-09 15:31 UTC (permalink / raw)
To: u-boot
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Split the RC and EP driver, and reimplement the EP driver base on
the EP framework.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- Rebase the patch without change intent.
drivers/pci/Makefile | 2 +-
drivers/pci/pcie_layerscape.c | 487 ++--------------------------
drivers/pci/pcie_layerscape.h | 44 ++-
drivers/pci/pcie_layerscape_ep.c | 241 ++++++++++++++
drivers/pci/pcie_layerscape_fixup.c | 79 +++--
drivers/pci/pcie_layerscape_rc.c | 379 ++++++++++++++++++++++
6 files changed, 735 insertions(+), 497 deletions(-)
create mode 100644 drivers/pci/pcie_layerscape_ep.c
create mode 100644 drivers/pci/pcie_layerscape_rc.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c051ecc9f3..440b5af588 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -33,7 +33,7 @@ obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
-obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
+obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o pcie_layerscape_rc.o pcie_layerscape_ep.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o pcie_layerscape_fixup_common.o
obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
pcie_layerscape_gen4_fixup.o \
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 39b6d40802..93018feb7c 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,18 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
#include <common.h>
#include <log.h>
-#include <asm/arch/fsl_serdes.h>
-#include <pci.h>
#include <asm/io.h>
#include <errno.h>
#include <malloc.h>
-#include <dm.h>
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
defined(CONFIG_ARM)
#include <asm/arch/clock.h>
@@ -23,18 +20,17 @@ DECLARE_GLOBAL_DATA_PTR;
LIST_HEAD(ls_pcie_list);
-static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
+unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
{
return in_le32(pcie->dbi + offset);
}
-static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
- unsigned int offset)
+void dbi_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset)
{
out_le32(pcie->dbi + offset, value);
}
-static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
+unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
{
if (pcie->big_endian)
return in_be32(pcie->ctrl + offset);
@@ -42,8 +38,8 @@ static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
return in_le32(pcie->ctrl + offset);
}
-static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
- unsigned int offset)
+void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
+ unsigned int offset)
{
if (pcie->big_endian)
out_be32(pcie->ctrl + offset, value);
@@ -51,6 +47,26 @@ static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
out_le32(pcie->ctrl + offset, value);
}
+void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie)
+{
+ u32 reg, val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dbi_readl(pcie, reg);
+ val |= PCIE_DBI_RO_WR_EN;
+ dbi_writel(pcie, val, reg);
+}
+
+void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie)
+{
+ u32 reg, val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dbi_readl(pcie, reg);
+ val &= ~PCIE_DBI_RO_WR_EN;
+ dbi_writel(pcie, val, reg);
+}
+
static int ls_pcie_ltssm(struct ls_pcie *pcie)
{
u32 state;
@@ -67,7 +83,7 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie)
return state;
}
-static int ls_pcie_link_up(struct ls_pcie *pcie)
+int ls_pcie_link_up(struct ls_pcie *pcie)
{
int ltssm;
@@ -78,22 +94,8 @@ static int ls_pcie_link_up(struct ls_pcie *pcie)
return 1;
}
-static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
- dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_VIEWPORT);
- dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
- dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_VIEWPORT);
- dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
- u64 phys, u64 bus_addr, pci_size_t size)
+void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
+ u64 phys, u64 bus_addr, pci_size_t size)
{
dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
@@ -106,18 +108,18 @@ static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
}
/* Use bar match mode and MEM type as default */
-static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
- int bar, u64 phys)
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, int type,
+ int bar, u64 phys)
{
dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
- dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
+ dbi_writel(pcie, type, PCIE_ATU_CR1);
dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
}
-static void ls_pcie_dump_atu(struct ls_pcie *pcie)
+void ls_pcie_dump_atu(struct ls_pcie *pcie)
{
int i;
@@ -134,431 +136,10 @@ static void ls_pcie_dump_atu(struct ls_pcie *pcie)
debug("\tUPPER BUS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
debug("\tLIMIT 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_LIMIT));
+ dbi_readl(pcie, PCIE_ATU_LIMIT));
debug("\tCR1 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_CR1));
debug("\tCR2 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_CR2));
}
}
-
-static void ls_pcie_setup_atu(struct ls_pcie *pcie)
-{
- struct pci_region *io, *mem, *pref;
- unsigned long long offset = 0;
- int idx = 0;
- uint svr;
-
- svr = get_svr();
- if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
- offset = LS1021_PCIE_SPACE_OFFSET +
- LS1021_PCIE_SPACE_SIZE * pcie->idx;
- }
-
- /* ATU 0 : OUTBOUND : CFG0 */
- ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_CFG0,
- pcie->cfg_res.start + offset,
- 0,
- fdt_resource_size(&pcie->cfg_res) / 2);
- /* ATU 1 : OUTBOUND : CFG1 */
- ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_TYPE_CFG1,
- pcie->cfg_res.start + offset +
- fdt_resource_size(&pcie->cfg_res) / 2,
- 0,
- fdt_resource_size(&pcie->cfg_res) / 2);
-
- pci_get_regions(pcie->bus, &io, &mem, &pref);
- idx = PCIE_ATU_REGION_INDEX1 + 1;
-
- /* Fix the pcie memory map for LS2088A series SoCs */
- svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
- if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A ||
- svr == SVR_LS2081A || svr == SVR_LS2041A) {
- if (io)
- io->phys_start = (io->phys_start &
- (PCIE_PHYS_SIZE - 1)) +
- LS2088A_PCIE1_PHYS_ADDR +
- LS2088A_PCIE_PHYS_SIZE * pcie->idx;
- if (mem)
- mem->phys_start = (mem->phys_start &
- (PCIE_PHYS_SIZE - 1)) +
- LS2088A_PCIE1_PHYS_ADDR +
- LS2088A_PCIE_PHYS_SIZE * pcie->idx;
- if (pref)
- pref->phys_start = (pref->phys_start &
- (PCIE_PHYS_SIZE - 1)) +
- LS2088A_PCIE1_PHYS_ADDR +
- LS2088A_PCIE_PHYS_SIZE * pcie->idx;
- }
-
- if (io)
- /* ATU : OUTBOUND : IO */
- ls_pcie_atu_outbound_set(pcie, idx++,
- PCIE_ATU_TYPE_IO,
- io->phys_start + offset,
- io->bus_start,
- io->size);
-
- if (mem)
- /* ATU : OUTBOUND : MEM */
- ls_pcie_atu_outbound_set(pcie, idx++,
- PCIE_ATU_TYPE_MEM,
- mem->phys_start + offset,
- mem->bus_start,
- mem->size);
-
- if (pref)
- /* ATU : OUTBOUND : pref */
- ls_pcie_atu_outbound_set(pcie, idx++,
- PCIE_ATU_TYPE_MEM,
- pref->phys_start + offset,
- pref->bus_start,
- pref->size);
-
- ls_pcie_dump_atu(pcie);
-}
-
-/* Return 0 if the address is valid, -errno if not valid */
-static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
-{
- struct udevice *bus = pcie->bus;
-
- if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
- return -ENODEV;
-
- if (!pcie->enabled)
- return -ENXIO;
-
- if (PCI_BUS(bdf) < bus->seq)
- return -EINVAL;
-
- if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
- return -EINVAL;
-
- if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
- return -EINVAL;
-
- return 0;
-}
-
-int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
- uint offset, void **paddress)
-{
- struct ls_pcie *pcie = dev_get_priv(bus);
- u32 busdev;
-
- if (ls_pcie_addr_valid(pcie, bdf))
- return -EINVAL;
-
- if (PCI_BUS(bdf) == bus->seq) {
- *paddress = pcie->dbi + offset;
- return 0;
- }
-
- busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) |
- PCIE_ATU_DEV(PCI_DEV(bdf)) |
- PCIE_ATU_FUNC(PCI_FUNC(bdf));
-
- if (PCI_BUS(bdf) == bus->seq + 1) {
- ls_pcie_cfg0_set_busdev(pcie, busdev);
- *paddress = pcie->cfg0 + offset;
- } else {
- ls_pcie_cfg1_set_busdev(pcie, busdev);
- *paddress = pcie->cfg1 + offset;
- }
- return 0;
-}
-
-static int ls_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
- uint offset, ulong *valuep,
- enum pci_size_t size)
-{
- return pci_generic_mmap_read_config(bus, ls_pcie_conf_address,
- bdf, offset, valuep, size);
-}
-
-static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
- uint offset, ulong value,
- enum pci_size_t size)
-{
- return pci_generic_mmap_write_config(bus, ls_pcie_conf_address,
- bdf, offset, value, size);
-}
-
-/* Clear multi-function bit */
-static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
-{
- writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
-}
-
-/* Fix class value */
-static void ls_pcie_fix_class(struct ls_pcie *pcie)
-{
- writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
-}
-
-/* Drop MSG TLP except for Vendor MSG */
-static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
-{
- u32 val;
-
- val = dbi_readl(pcie, PCIE_STRFMR1);
- val &= 0xDFFFFFFF;
- dbi_writel(pcie, val, PCIE_STRFMR1);
-}
-
-/* Disable all bars in RC mode */
-static void ls_pcie_disable_bars(struct ls_pcie *pcie)
-{
- dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
- dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
- dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
-}
-
-static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
-{
- ls_pcie_setup_atu(pcie);
-
- dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
- ls_pcie_fix_class(pcie);
- ls_pcie_clear_multifunction(pcie);
- ls_pcie_drop_msg_tlp(pcie);
- dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
-
- ls_pcie_disable_bars(pcie);
- pcie->stream_id_cur = 0;
-}
-
-static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
-{
- u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
-
- /* ATU 0 : INBOUND : map BAR0 */
- ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
- /* ATU 1 : INBOUND : map BAR1 */
- phys += PCIE_BAR1_SIZE;
- ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
- /* ATU 2 : INBOUND : map BAR2 */
- phys += PCIE_BAR2_SIZE;
- ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
- /* ATU 3 : INBOUND : map BAR4 */
- phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
- ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
-
- /* ATU 0 : OUTBOUND : map MEM */
- ls_pcie_atu_outbound_set(pcie, 0,
- PCIE_ATU_TYPE_MEM,
- pcie->cfg_res.start,
- 0,
- CONFIG_SYS_PCI_MEMORY_SIZE);
-}
-
-/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
-static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
-{
- /* The least inbound window is 4KiB */
- if (size < 4 * 1024)
- return;
-
- switch (bar) {
- case 0:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
- break;
- case 1:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
- break;
- case 2:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
- writel(0, bar_base + PCI_BASE_ADDRESS_3);
- break;
- case 4:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
- writel(0, bar_base + PCI_BASE_ADDRESS_5);
- break;
- default:
- break;
- }
-}
-
-static void ls_pcie_ep_setup_bars(void *bar_base)
-{
- /* BAR0 - 32bit - 4K configuration */
- ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
- /* BAR1 - 32bit - 8K MSIX*/
- ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
- /* BAR2 - 64bit - 4K MEM desciptor */
- ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
- /* BAR4 - 64bit - 1M MEM*/
- ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
-}
-
-static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
-{
- u32 config;
-
- config = ctrl_readl(pcie, PCIE_PF_CONFIG);
- config |= PCIE_CONFIG_READY;
- ctrl_writel(pcie, config, PCIE_PF_CONFIG);
-}
-
-static void ls_pcie_setup_ep(struct ls_pcie *pcie)
-{
- u32 sriov;
-
- sriov = readl(pcie->dbi + PCIE_SRIOV);
- if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
- int pf, vf;
-
- for (pf = 0; pf < PCIE_PF_NUM; pf++) {
- for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
- ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
- PCIE_PF_VF_CTRL);
-
- ls_pcie_ep_setup_bars(pcie->dbi);
- ls_pcie_ep_setup_atu(pcie);
- }
- }
- /* Disable CFG2 */
- ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
- } else {
- ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
- ls_pcie_ep_setup_atu(pcie);
- }
-
- ls_pcie_ep_enable_cfg(pcie);
-}
-
-static int ls_pcie_probe(struct udevice *dev)
-{
- struct ls_pcie *pcie = dev_get_priv(dev);
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(dev);
- u16 link_sta;
- uint svr;
- int ret;
- fdt_size_t cfg_size;
-
- pcie->bus = dev;
-
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "dbi", &pcie->dbi_res);
- if (ret) {
- printf("ls-pcie: resource \"dbi\" not found\n");
- return ret;
- }
-
- pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
-
- list_add(&pcie->list, &ls_pcie_list);
-
- pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
- if (!pcie->enabled) {
- printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
- return 0;
- }
-
- pcie->dbi = map_physmem(pcie->dbi_res.start,
- fdt_resource_size(&pcie->dbi_res),
- MAP_NOCACHE);
-
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "lut", &pcie->lut_res);
- if (!ret)
- pcie->lut = map_physmem(pcie->lut_res.start,
- fdt_resource_size(&pcie->lut_res),
- MAP_NOCACHE);
-
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "ctrl", &pcie->ctrl_res);
- if (!ret)
- pcie->ctrl = map_physmem(pcie->ctrl_res.start,
- fdt_resource_size(&pcie->ctrl_res),
- MAP_NOCACHE);
- if (!pcie->ctrl)
- pcie->ctrl = pcie->lut;
-
- if (!pcie->ctrl) {
- printf("%s: NOT find CTRL\n", dev->name);
- return -1;
- }
-
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "config", &pcie->cfg_res);
- if (ret) {
- printf("%s: resource \"config\" not found\n", dev->name);
- return ret;
- }
-
- /*
- * Fix the pcie memory map address and PF control registers address
- * for LS2088A series SoCs
- */
- svr = get_svr();
- svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
- if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A ||
- svr == SVR_LS2081A || svr == SVR_LS2041A) {
- cfg_size = fdt_resource_size(&pcie->cfg_res);
- pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
- LS2088A_PCIE_PHYS_SIZE * pcie->idx;
- pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
- pcie->ctrl = pcie->lut + 0x40000;
- }
-
- pcie->cfg0 = map_physmem(pcie->cfg_res.start,
- fdt_resource_size(&pcie->cfg_res),
- MAP_NOCACHE);
- pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
-
- pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
-
- debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
- dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
- (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
- pcie->big_endian);
-
- pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
-
- if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
- ls_pcie_setup_ep(pcie);
- } else {
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
- ls_pcie_setup_ctrl(pcie);
- }
-
- if (!ls_pcie_link_up(pcie)) {
- /* Let the user know there's no PCIe link */
- printf(": no link\n");
- return 0;
- }
-
- /* Print the negotiated PCIe link width */
- link_sta = readw(pcie->dbi + PCIE_LINK_STA);
- printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
- link_sta & PCIE_LINK_SPEED_MASK);
-
- return 0;
-}
-
-static const struct dm_pci_ops ls_pcie_ops = {
- .read_config = ls_pcie_read_config,
- .write_config = ls_pcie_write_config,
-};
-
-static const struct udevice_id ls_pcie_ids[] = {
- { .compatible = "fsl,ls-pcie" },
- { }
-};
-
-U_BOOT_DRIVER(pci_layerscape) = {
- .name = "pci_layerscape",
- .id = UCLASS_PCI,
- .of_match = ls_pcie_ids,
- .ops = &ls_pcie_ops,
- .probe = ls_pcie_probe,
- .priv_auto_alloc_size = sizeof(struct ls_pcie),
-};
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 95454bc188..217dcda6d1 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
@@ -60,7 +60,8 @@
/* DBI registers */
#define PCIE_SRIOV 0x178
#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
-#define PCIE_DBI_RO_WR_EN 0x8bc
+#define PCIE_DBI_RO_WR_EN BIT(0)
+#define PCIE_MISC_CONTROL_1_OFF 0x8BC
#define PCIE_LINK_CAP 0x7c
#define PCIE_LINK_SPEED_MASK 0xf
@@ -82,7 +83,7 @@
PCIE_LCTRL0_CFG2_ENABLE)
#define PCIE_NO_SRIOV_BAR_BASE 0x1000
-
+#define FSL_PCIE_EP_MIN_APERTURE 4096 /* 4 Kbytes */
#define PCIE_PF_NUM 2
#define PCIE_VF_NUM 64
@@ -129,25 +130,52 @@
#define LS1021_LTSSM_STATE_SHIFT 20
struct ls_pcie {
+ void __iomem *dbi;
+ void __iomem *lut;
+ void __iomem *ctrl;
int idx;
+ bool big_endian;
+ int mode;
+};
+
+struct ls_pcie_rc {
+ struct ls_pcie *pcie;
struct list_head list;
struct udevice *bus;
struct fdt_resource dbi_res;
struct fdt_resource lut_res;
struct fdt_resource ctrl_res;
struct fdt_resource cfg_res;
- void __iomem *dbi;
- void __iomem *lut;
- void __iomem *ctrl;
void __iomem *cfg0;
void __iomem *cfg1;
- bool big_endian;
bool enabled;
int next_lut_index;
int stream_id_cur;
- int mode;
+};
+
+struct ls_pcie_ep {
+ struct fdt_resource addr_res;
+ struct ls_pcie *pcie;
+ struct udevice *bus;
+ void __iomem *addr;
+ u32 num_ib_wins;
+ u32 num_ob_wins;
+ u8 max_functions;
};
extern struct list_head ls_pcie_list;
+unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset);
+void dbi_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset);
+unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset);
+void ctrl_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset);
+void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
+ u64 phys, u64 bus_addr, pci_size_t size);
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, int type,
+ int bar, u64 phys);
+void ls_pcie_dump_atu(struct ls_pcie *pcie);
+int ls_pcie_link_up(struct ls_pcie *pcie);
+void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
+void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie);
+
#endif /* _PCIE_LAYERSCAPE_H_ */
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
new file mode 100644
index 0000000000..b463a7734a
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ * Layerscape PCIe EP driver
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/devres.h>
+#include <errno.h>
+#include <pci_ep.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <linux/log2.h>
+#include "pcie_layerscape.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ls_pcie_ep_enable_cfg(struct ls_pcie_ep *pcie_ep)
+{
+ struct ls_pcie *pcie = pcie_ep->pcie;
+ u32 config;
+
+ config = ctrl_readl(pcie, PCIE_PF_CONFIG);
+ config |= PCIE_CONFIG_READY;
+ ctrl_writel(pcie, config, PCIE_PF_CONFIG);
+}
+
+static int ls_ep_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
+{
+ struct ls_pcie_ep *pcie_ep = dev_get_priv(dev);
+ struct ls_pcie *pcie = pcie_ep->pcie;
+ dma_addr_t bar_phys = ep_bar->phys_addr;
+ enum pci_barno bar = ep_bar->barno;
+ u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+ int flags = ep_bar->flags;
+ int type, idx;
+ u64 size;
+
+ idx = bar;
+ /* BAR size is 2^(aperture + 11) */
+ size = max_t(size_t, ep_bar->size, FSL_PCIE_EP_MIN_APERTURE);
+
+ if (!(flags & PCI_BASE_ADDRESS_SPACE))
+ type = PCIE_ATU_TYPE_MEM;
+ else
+ type = PCIE_ATU_TYPE_IO;
+
+ ls_pcie_atu_inbound_set(pcie, idx, bar, bar_phys, type);
+
+ dbi_writel(pcie, lower_32_bits(size - 1), reg + PCIE_NO_SRIOV_BAR_BASE);
+ dbi_writel(pcie, flags, reg);
+
+ if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ dbi_writel(pcie, upper_32_bits(size - 1),
+ reg + 4 + PCIE_NO_SRIOV_BAR_BASE);
+ dbi_writel(pcie, 0, reg + 4);
+ }
+
+ return 0;
+}
+
+static struct pci_ep_ops ls_pcie_ep_ops = {
+ .set_bar = ls_ep_set_bar,
+};
+
+static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep)
+{
+ struct ls_pcie *pcie = pcie_ep->pcie;
+ u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
+
+ /* ATU 0 : INBOUND : map BAR0 */
+ ls_pcie_atu_inbound_set(pcie, 0, PCIE_ATU_TYPE_MEM, 0, phys);
+ /* ATU 1 : INBOUND : map BAR1 */
+ phys += PCIE_BAR1_SIZE;
+ ls_pcie_atu_inbound_set(pcie, 1, PCIE_ATU_TYPE_MEM, 1, phys);
+ /* ATU 2 : INBOUND : map BAR2 */
+ phys += PCIE_BAR2_SIZE;
+ ls_pcie_atu_inbound_set(pcie, 2, PCIE_ATU_TYPE_MEM, 2, phys);
+ /* ATU 3 : INBOUND : map BAR4 */
+ phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
+ ls_pcie_atu_inbound_set(pcie, 3, PCIE_ATU_TYPE_MEM, 4, phys);
+
+ /* ATU 0 : OUTBOUND : map MEM */
+ ls_pcie_atu_outbound_set(pcie, 0,
+ PCIE_ATU_TYPE_MEM,
+ pcie_ep->addr_res.start,
+ 0,
+ CONFIG_SYS_PCI_MEMORY_SIZE);
+}
+
+/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
+static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
+{
+ /* The least inbound window is 4KiB */
+ if (size < 4 * 1024)
+ return;
+
+ switch (bar) {
+ case 0:
+ writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
+ break;
+ case 1:
+ writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
+ break;
+ case 2:
+ writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
+ writel(0, bar_base + PCI_BASE_ADDRESS_3);
+ break;
+ case 4:
+ writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
+ writel(0, bar_base + PCI_BASE_ADDRESS_5);
+ break;
+ default:
+ break;
+ }
+}
+
+static void ls_pcie_ep_setup_bars(void *bar_base)
+{
+ /* BAR0 - 32bit - 4K configuration */
+ ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
+ /* BAR1 - 32bit - 8K MSIX */
+ ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
+ /* BAR2 - 64bit - 4K MEM descriptor */
+ ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
+ /* BAR4 - 64bit - 1M MEM */
+ ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
+}
+
+static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
+{
+ u32 sriov;
+ struct ls_pcie *pcie = pcie_ep->pcie;
+
+ sriov = readl(pcie->dbi + PCIE_SRIOV);
+ if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
+ int pf, vf;
+
+ for (pf = 0; pf < PCIE_PF_NUM; pf++) {
+ for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+ ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
+ PCIE_PF_VF_CTRL);
+
+ ls_pcie_ep_setup_bars(pcie->dbi);
+ ls_pcie_ep_setup_atu(pcie_ep);
+ }
+ }
+ /* Disable CFG2 */
+ ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
+ } else {
+ ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
+ ls_pcie_ep_setup_atu(pcie_ep);
+ }
+
+ ls_pcie_ep_enable_cfg(pcie_ep);
+}
+
+static int ls_pcie_ep_probe(struct udevice *dev)
+{
+ struct ls_pcie_ep *pcie_ep = dev_get_priv(dev);
+ struct ls_pcie *pcie;
+ u16 link_sta;
+ int ret;
+
+ pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ pcie_ep->pcie = pcie;
+
+ pcie->dbi = (void __iomem *)devfdt_get_addr_index(dev, 0);
+ if (!pcie->dbi)
+ return -ENOMEM;
+
+ pcie->ctrl = (void __iomem *)devfdt_get_addr_index(dev, 1);
+ if (!pcie->ctrl)
+ return -ENOMEM;
+
+ ret = fdt_get_named_resource(gd->fdt_blob, dev_of_offset(dev),
+ "reg", "reg-names",
+ "addr_space", &pcie_ep->addr_res);
+ if (ret) {
+ printf("%s: resource \"addr_space\" not found\n", dev->name);
+ return ret;
+ }
+
+ pcie->idx = ((unsigned long)pcie->dbi - PCIE_SYS_BASE_ADDR) /
+ PCIE_CCSR_SIZE;
+
+ pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
+ "big-endian");
+
+ pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
+ if (pcie->mode != PCI_HEADER_TYPE_NORMAL)
+ return 0;
+
+ pcie_ep->max_functions = fdtdec_get_int(gd->fdt_blob,
+ dev_of_offset(dev),
+ "max-functions", 1);
+ pcie_ep->num_ib_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "num-ib-windows", 8);
+ pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "num-ob-windows", 8);
+
+ printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+ ls_pcie_setup_ep(pcie_ep);
+
+ if (!ls_pcie_link_up(pcie)) {
+ /* Let the user know there's no PCIe link */
+ printf(": no link\n");
+ return 0;
+ }
+
+ /* Print the negotiated PCIe link width */
+ link_sta = readw(pcie->dbi + PCIE_LINK_STA);
+ printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
+ link_sta & PCIE_LINK_SPEED_MASK);
+
+ return 0;
+}
+
+static int ls_pcie_ep_remove(struct udevice *dev)
+{
+ return 0;
+}
+
+const struct udevice_id ls_pcie_ep_ids[] = {
+ { .compatible = "fsl,ls-pcie-ep" },
+ { }
+};
+
+U_BOOT_DRIVER(pci_layerscape_ep) = {
+ .name = "pci_layerscape_ep",
+ .id = UCLASS_PCI_EP,
+ .of_match = ls_pcie_ep_ids,
+ .ops = &ls_pcie_ep_ops,
+ .probe = ls_pcie_ep_probe,
+ .remove = ls_pcie_ep_remove,
+ .priv_auto_alloc_size = sizeof(struct ls_pcie_ep),
+};
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 25a3c3870c..4a18a6e033 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -25,17 +25,19 @@
/*
* Return next available LUT index.
*/
-static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
+static int ls_pcie_next_lut_index(struct ls_pcie_rc *pcie_rc)
{
- if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
- return pcie->next_lut_index++;
+ if (pcie_rc->next_lut_index < PCIE_LUT_ENTRY_COUNT)
+ return pcie_rc->next_lut_index++;
else
return -ENOSPC; /* LUT is full */
}
-static void lut_writel(struct ls_pcie *pcie, unsigned int value,
+static void lut_writel(struct ls_pcie_rc *pcie_rc, unsigned int value,
unsigned int offset)
{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
if (pcie->big_endian)
out_be32(pcie->lut + offset, value);
else
@@ -45,12 +47,12 @@ static void lut_writel(struct ls_pcie *pcie, unsigned int value,
/*
* Program a single LUT entry
*/
-static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
- u32 streamid)
+static void ls_pcie_lut_set_mapping(struct ls_pcie_rc *pcie_rc, int index,
+ u32 devid, u32 streamid)
{
/* leave mask as all zeroes, want to match all bits */
- lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
- lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
+ lut_writel(pcie_rc, devid << 16, PCIE_LUT_UDR(index));
+ lut_writel(pcie_rc, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
}
/*
@@ -61,7 +63,8 @@ static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
*/
-static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
+static void fdt_pcie_set_msi_map_entry_ls(void *blob,
+ struct ls_pcie_rc *pcie_rc,
u32 devid, u32 streamid)
{
u32 *prop;
@@ -69,10 +72,11 @@ static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
int nodeoffset;
uint svr;
char *compat = NULL;
+ struct ls_pcie *pcie = pcie_rc->pcie;
/* find pci controller node */
nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie->dbi_res.start);
+ pcie_rc->dbi_res.start);
if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
@@ -84,7 +88,7 @@ static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
compat = CONFIG_FSL_PCIE_COMPAT;
if (compat)
nodeoffset = fdt_node_offset_by_compat_reg(blob,
- compat, pcie->dbi_res.start);
+ compat, pcie_rc->dbi_res.start);
#endif
if (nodeoffset < 0)
return;
@@ -114,7 +118,8 @@ static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
* iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
* [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
*/
-static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
+static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
+ struct ls_pcie_rc *pcie_rc,
u32 devid, u32 streamid)
{
u32 *prop;
@@ -123,10 +128,11 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
int lenp;
uint svr;
char *compat = NULL;
+ struct ls_pcie *pcie = pcie_rc->pcie;
/* find pci controller node */
nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie->dbi_res.start);
+ pcie_rc->dbi_res.start);
if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
@@ -139,7 +145,7 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
if (compat)
nodeoffset = fdt_node_offset_by_compat_reg(blob,
- compat, pcie->dbi_res.start);
+ compat, pcie_rc->dbi_res.start);
#endif
if (nodeoffset < 0)
return;
@@ -170,7 +176,7 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
static void fdt_fixup_pcie_ls(void *blob)
{
struct udevice *dev, *bus;
- struct ls_pcie *pcie;
+ struct ls_pcie_rc *pcie_rc;
int streamid;
int index;
pci_dev_t bdf;
@@ -181,17 +187,18 @@ static void fdt_fixup_pcie_ls(void *blob)
pci_find_next_device(&dev)) {
for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
- pcie = dev_get_priv(bus);
+ pcie_rc = dev_get_priv(bus);
- streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
+ streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
+ pcie_rc->pcie->idx);
if (streamid < 0) {
debug("ERROR: no stream ids free\n");
continue;
} else {
- pcie->stream_id_cur++;
+ pcie_rc->stream_id_cur++;
}
- index = ls_pcie_next_lut_index(pcie);
+ index = ls_pcie_next_lut_index(pcie_rc);
if (index < 0) {
debug("ERROR: no LUT indexes free\n");
continue;
@@ -200,27 +207,28 @@ static void fdt_fixup_pcie_ls(void *blob)
/* the DT fixup must be relative to the hose first_busno */
bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
/* map PCI b.d.f to streamID in LUT */
- ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
+ ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8,
streamid);
/* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
+ fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8,
streamid);
/* update iommu-map in device tree */
- fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
+ fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8,
streamid);
}
pcie_board_fix_fdt(blob);
}
#endif
-static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
{
int off;
uint svr;
char *compat = NULL;
+ struct ls_pcie *pcie = pcie_rc->pcie;
off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie->dbi_res.start);
+ pcie_rc->dbi_res.start);
if (off < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
@@ -232,46 +240,47 @@ static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
compat = CONFIG_FSL_PCIE_COMPAT;
if (compat)
off = fdt_node_offset_by_compat_reg(blob,
- compat, pcie->dbi_res.start);
+ compat, pcie_rc->dbi_res.start);
#endif
if (off < 0)
return;
}
- if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
+ if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
else
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
}
-static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_ep_fix(void *blob, struct ls_pcie_rc *pcie_rc)
{
int off;
+ struct ls_pcie *pcie = pcie_rc->pcie;
off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
- pcie->dbi_res.start);
+ pcie_rc->dbi_res.start);
if (off < 0)
return;
- if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
+ if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
else
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
}
-static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc *pcie_rc)
{
- ft_pcie_ep_fix(blob, pcie);
- ft_pcie_rc_fix(blob, pcie);
+ ft_pcie_ep_fix(blob, pcie_rc);
+ ft_pcie_rc_fix(blob, pcie_rc);
}
/* Fixup Kernel DT for PCIe */
void ft_pci_setup_ls(void *blob, bd_t *bd)
{
- struct ls_pcie *pcie;
+ struct ls_pcie_rc *pcie_rc;
- list_for_each_entry(pcie, &ls_pcie_list, list)
- ft_pcie_ls_setup(blob, pcie);
+ list_for_each_entry(pcie_rc, &ls_pcie_list, list)
+ ft_pcie_ls_setup(blob, pcie_rc);
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
fdt_fixup_pcie_ls(blob);
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
new file mode 100644
index 0000000000..e922e5dbcd
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ * Layerscape PCIe driver
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <malloc.h>
+#include <dm.h>
+#include <dm/devres.h>
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
+ defined(CONFIG_ARM)
+#include <asm/arch/clock.h>
+#endif
+#include "pcie_layerscape.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_VIEWPORT);
+ dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
+}
+
+static void ls_pcie_cfg1_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_VIEWPORT);
+ dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
+}
+
+static void ls_pcie_setup_atu(struct ls_pcie_rc *pcie_rc)
+{
+ struct pci_region *io, *mem, *pref;
+ unsigned long long offset = 0;
+ struct ls_pcie *pcie = pcie_rc->pcie;
+ int idx = 0;
+ uint svr;
+
+ svr = get_svr();
+ if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
+ offset = LS1021_PCIE_SPACE_OFFSET +
+ LS1021_PCIE_SPACE_SIZE * pcie->idx;
+ }
+
+ /* ATU 0 : OUTBOUND : CFG0 */
+ ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_CFG0,
+ pcie_rc->cfg_res.start + offset,
+ 0,
+ fdt_resource_size(&pcie_rc->cfg_res) / 2);
+ /* ATU 1 : OUTBOUND : CFG1 */
+ ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_CFG1,
+ pcie_rc->cfg_res.start + offset +
+ fdt_resource_size(&pcie_rc->cfg_res) / 2,
+ 0,
+ fdt_resource_size(&pcie_rc->cfg_res) / 2);
+
+ pci_get_regions(pcie_rc->bus, &io, &mem, &pref);
+ idx = PCIE_ATU_REGION_INDEX1 + 1;
+
+ /* Fix the pcie memory map for LS2088A series SoCs */
+ svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+ if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+ svr == SVR_LS2048A || svr == SVR_LS2044A ||
+ svr == SVR_LS2081A || svr == SVR_LS2041A) {
+ if (io)
+ io->phys_start = (io->phys_start &
+ (PCIE_PHYS_SIZE - 1)) +
+ LS2088A_PCIE1_PHYS_ADDR +
+ LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+ if (mem)
+ mem->phys_start = (mem->phys_start &
+ (PCIE_PHYS_SIZE - 1)) +
+ LS2088A_PCIE1_PHYS_ADDR +
+ LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+ if (pref)
+ pref->phys_start = (pref->phys_start &
+ (PCIE_PHYS_SIZE - 1)) +
+ LS2088A_PCIE1_PHYS_ADDR +
+ LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+ }
+
+ if (io)
+ /* ATU : OUTBOUND : IO */
+ ls_pcie_atu_outbound_set(pcie, idx++,
+ PCIE_ATU_TYPE_IO,
+ io->phys_start + offset,
+ io->bus_start,
+ io->size);
+
+ if (mem)
+ /* ATU : OUTBOUND : MEM */
+ ls_pcie_atu_outbound_set(pcie, idx++,
+ PCIE_ATU_TYPE_MEM,
+ mem->phys_start + offset,
+ mem->bus_start,
+ mem->size);
+
+ if (pref)
+ /* ATU : OUTBOUND : pref */
+ ls_pcie_atu_outbound_set(pcie, idx++,
+ PCIE_ATU_TYPE_MEM,
+ pref->phys_start + offset,
+ pref->bus_start,
+ pref->size);
+
+ ls_pcie_dump_atu(pcie);
+}
+
+/* Return 0 if the address is valid, -errno if not valid */
+static int ls_pcie_addr_valid(struct ls_pcie_rc *pcie_rc, pci_dev_t bdf)
+{
+ struct udevice *bus = pcie_rc->bus;
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
+ return -ENODEV;
+
+ if (!pcie_rc->enabled)
+ return -ENXIO;
+
+ if (PCI_BUS(bdf) < bus->seq)
+ return -EINVAL;
+
+ if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
+ return -EINVAL;
+
+ if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
+ return -EINVAL;
+
+ return 0;
+}
+
+int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
+ uint offset, void **paddress)
+{
+ struct ls_pcie_rc *pcie_rc = dev_get_priv(bus);
+ struct ls_pcie *pcie = pcie_rc->pcie;
+ u32 busdev;
+
+ if (ls_pcie_addr_valid(pcie_rc, bdf))
+ return -EINVAL;
+
+ if (PCI_BUS(bdf) == bus->seq) {
+ *paddress = pcie->dbi + offset;
+ return 0;
+ }
+
+ busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) |
+ PCIE_ATU_DEV(PCI_DEV(bdf)) |
+ PCIE_ATU_FUNC(PCI_FUNC(bdf));
+
+ if (PCI_BUS(bdf) == bus->seq + 1) {
+ ls_pcie_cfg0_set_busdev(pcie_rc, busdev);
+ *paddress = pcie_rc->cfg0 + offset;
+ } else {
+ ls_pcie_cfg1_set_busdev(pcie_rc, busdev);
+ *paddress = pcie_rc->cfg1 + offset;
+ }
+ return 0;
+}
+
+static int ls_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ return pci_generic_mmap_read_config(bus, ls_pcie_conf_address,
+ bdf, offset, valuep, size);
+}
+
+static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ return pci_generic_mmap_write_config(bus, ls_pcie_conf_address,
+ bdf, offset, value, size);
+}
+
+/* Clear multi-function bit */
+static void ls_pcie_clear_multifunction(struct ls_pcie_rc *pcie_rc)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
+}
+
+/* Fix class value */
+static void ls_pcie_fix_class(struct ls_pcie_rc *pcie_rc)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
+}
+
+/* Drop MSG TLP except for Vendor MSG */
+static void ls_pcie_drop_msg_tlp(struct ls_pcie_rc *pcie_rc)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+ u32 val;
+
+ val = dbi_readl(pcie, PCIE_STRFMR1);
+ val &= 0xDFFFFFFF;
+ dbi_writel(pcie, val, PCIE_STRFMR1);
+}
+
+/* Disable all bars in RC mode */
+static void ls_pcie_disable_bars(struct ls_pcie_rc *pcie_rc)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
+ dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
+ dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
+}
+
+static void ls_pcie_setup_ctrl(struct ls_pcie_rc *pcie_rc)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ ls_pcie_setup_atu(pcie_rc);
+
+ ls_pcie_dbi_ro_wr_en(pcie);
+ ls_pcie_fix_class(pcie_rc);
+ ls_pcie_clear_multifunction(pcie_rc);
+ ls_pcie_drop_msg_tlp(pcie_rc);
+ ls_pcie_dbi_ro_wr_dis(pcie);
+
+ ls_pcie_disable_bars(pcie_rc);
+ pcie_rc->stream_id_cur = 0;
+}
+
+static int ls_pcie_probe(struct udevice *dev)
+{
+ struct ls_pcie_rc *pcie_rc = dev_get_priv(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ struct ls_pcie *pcie;
+ u16 link_sta;
+ uint svr;
+ int ret;
+ fdt_size_t cfg_size;
+
+ pcie_rc->bus = dev;
+
+ pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ pcie_rc->pcie = pcie;
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "dbi", &pcie_rc->dbi_res);
+ if (ret) {
+ printf("ls-pcie: resource \"dbi\" not found\n");
+ return ret;
+ }
+
+ pcie->idx = (pcie_rc->dbi_res.start - PCIE_SYS_BASE_ADDR) /
+ PCIE_CCSR_SIZE;
+
+ list_add(&pcie_rc->list, &ls_pcie_list);
+
+ pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
+ if (!pcie_rc->enabled) {
+ printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+ return 0;
+ }
+
+ pcie->dbi = map_physmem(pcie_rc->dbi_res.start,
+ fdt_resource_size(&pcie_rc->dbi_res),
+ MAP_NOCACHE);
+
+ pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
+ if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
+ return 0;
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "lut", &pcie_rc->lut_res);
+ if (!ret)
+ pcie->lut = map_physmem(pcie_rc->lut_res.start,
+ fdt_resource_size(&pcie_rc->lut_res),
+ MAP_NOCACHE);
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "ctrl", &pcie_rc->ctrl_res);
+ if (!ret)
+ pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
+ fdt_resource_size(&pcie_rc->ctrl_res),
+ MAP_NOCACHE);
+ if (!pcie->ctrl)
+ pcie->ctrl = pcie->lut;
+
+ if (!pcie->ctrl) {
+ printf("%s: NOT find CTRL\n", dev->name);
+ return -1;
+ }
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "config", &pcie_rc->cfg_res);
+ if (ret) {
+ printf("%s: resource \"config\" not found\n", dev->name);
+ return ret;
+ }
+
+ /*
+ * Fix the pcie memory map address and PF control registers address
+ * for LS2088A series SoCs
+ */
+ svr = get_svr();
+ svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+ if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+ svr == SVR_LS2048A || svr == SVR_LS2044A ||
+ svr == SVR_LS2081A || svr == SVR_LS2041A) {
+ cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
+ pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
+ LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+ pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
+ pcie->ctrl = pcie->lut + 0x40000;
+ }
+
+ pcie_rc->cfg0 = map_physmem(pcie_rc->cfg_res.start,
+ fdt_resource_size(&pcie_rc->cfg_res),
+ MAP_NOCACHE);
+ pcie_rc->cfg1 = pcie_rc->cfg0 +
+ fdt_resource_size(&pcie_rc->cfg_res) / 2;
+
+ pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
+
+ debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
+ dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
+ (unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
+ pcie->big_endian);
+
+ printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+ ls_pcie_setup_ctrl(pcie_rc);
+
+ if (!ls_pcie_link_up(pcie)) {
+ /* Let the user know there's no PCIe link */
+ printf(": no link\n");
+ return 0;
+ }
+
+ /* Print the negotiated PCIe link width */
+ link_sta = readw(pcie->dbi + PCIE_LINK_STA);
+ printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
+ link_sta & PCIE_LINK_SPEED_MASK);
+
+ return 0;
+}
+
+static const struct dm_pci_ops ls_pcie_ops = {
+ .read_config = ls_pcie_read_config,
+ .write_config = ls_pcie_write_config,
+};
+
+static const struct udevice_id ls_pcie_ids[] = {
+ { .compatible = "fsl,ls-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(pci_layerscape) = {
+ .name = "pci_layerscape",
+ .id = UCLASS_PCI,
+ .of_match = ls_pcie_ids,
+ .ops = &ls_pcie_ops,
+ .probe = ls_pcie_probe,
+ .priv_auto_alloc_size = sizeof(struct ls_pcie_rc),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCHv2 02/10] pci_ep: Add the init function
2020-07-09 15:31 [PATCHv2 00/10] pci: layerscape: Split EP mode code into a Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 01/10] pci: layerscape: Split the EP and RC driver Zhiqiang Hou
@ 2020-07-09 15:31 ` Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 03/10] armv8: dts: ls1046a: Add the PCIe EP node Zhiqiang Hou
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2020-07-09 15:31 UTC (permalink / raw)
To: u-boot
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Some EP deivces need to initialize before RC scan it, e.g. NXP
layerscape platform, so add the init function in pci_ep uclass.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- Rebase the patch without change intent.
common/board_r.c | 12 ++++++++++++
drivers/pci_endpoint/pci_ep-uclass.c | 11 +++++++++++
include/init.h | 1 +
3 files changed, 24 insertions(+)
diff --git a/common/board_r.c b/common/board_r.c
index fa57fa9b69..d4db44fc59 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -233,6 +233,15 @@ static int initr_unlock_ram_in_cache(void)
}
#endif
+#ifdef CONFIG_PCI_ENDPOINT
+static int initr_pci_ep(void)
+{
+ pci_ep_init();
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_PCI
static int initr_pci(void)
{
@@ -830,6 +839,9 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_BITBANGMII
initr_bbmii,
#endif
+#ifdef CONFIG_PCI_ENDPOINT
+ initr_pci_ep,
+#endif
#ifdef CONFIG_CMD_NET
INIT_FUNC_WATCHDOG_RESET
initr_net,
diff --git a/drivers/pci_endpoint/pci_ep-uclass.c b/drivers/pci_endpoint/pci_ep-uclass.c
index 9f53a9a9b9..38a5f08376 100644
--- a/drivers/pci_endpoint/pci_ep-uclass.c
+++ b/drivers/pci_endpoint/pci_ep-uclass.c
@@ -209,3 +209,14 @@ UCLASS_DRIVER(pci_ep) = {
.name = "pci_ep",
.flags = DM_UC_FLAG_SEQ_ALIAS,
};
+
+void pci_ep_init(void)
+{
+ struct udevice *dev;
+
+ for (uclass_first_device_check(UCLASS_PCI_EP, &dev);
+ dev;
+ uclass_next_device_check(&dev)) {
+ ;
+ }
+}
diff --git a/include/init.h b/include/init.h
index b5a167b6ed..2d79afc381 100644
--- a/include/init.h
+++ b/include/init.h
@@ -213,6 +213,7 @@ int set_cpu_clk_info(void);
int update_flash_size(int flash_size);
int arch_early_init_r(void);
void pci_init(void);
+void pci_ep_init(void);
int misc_init_r(void);
#if defined(CONFIG_VID)
int init_func_vid(void);
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCHv2 03/10] armv8: dts: ls1046a: Add the PCIe EP node
2020-07-09 15:31 [PATCHv2 00/10] pci: layerscape: Split EP mode code into a Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 01/10] pci: layerscape: Split the EP and RC driver Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 02/10] pci_ep: Add the init function Zhiqiang Hou
@ 2020-07-09 15:31 ` Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 04/10] PCI_EP: layerscape: Add the multiple function support Zhiqiang Hou
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2020-07-09 15:31 UTC (permalink / raw)
To: u-boot
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Add the PCIe EP node for ls1046a.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- Rebase the patch without change intent.
arch/arm/dts/fsl-ls1046a.dtsi | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 8673a5db2a..3f11d6cd18 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -257,6 +257,17 @@
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
+ pcie_ep at 3400000 {
+ compatible = "fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x80000
+ 0x00 0x034c0000 0x0 0x40000
+ 0x40 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "ctrl", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ big-endian;
+ };
+
pcie at 3500000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
@@ -274,6 +285,17 @@
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
+ pcie_ep at 3500000 {
+ compatible = "fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x80000
+ 0x00 0x035c0000 0x0 0x40000
+ 0x48 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "ctrl", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ big-endian;
+ };
+
pcie at 3600000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
@@ -290,6 +312,17 @@
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
+ pcie_ep at 3600000 {
+ compatible = "fsl,ls-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x80000
+ 0x00 0x036c0000 0x0 0x40000
+ 0x50 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "ctrl", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ big-endian;
+ };
+
sata: sata at 3200000 {
compatible = "fsl,ls1046a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCHv2 04/10] PCI_EP: layerscape: Add the multiple function support
2020-07-09 15:31 [PATCHv2 00/10] pci: layerscape: Split EP mode code into a Zhiqiang Hou
` (2 preceding siblings ...)
2020-07-09 15:31 ` [PATCHv2 03/10] armv8: dts: ls1046a: Add the PCIe EP node Zhiqiang Hou
@ 2020-07-09 15:31 ` Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 05/10] pci_ep: layerscape: Add the workaround for errata A-009460 Zhiqiang Hou
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2020-07-09 15:31 UTC (permalink / raw)
To: u-boot
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Add the multiple function support for Layerscape platform, some PEXs
of Layerscaple platform have more than one PF.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape.c | 6 +-
drivers/pci/pcie_layerscape.h | 21 ++++--
drivers/pci/pcie_layerscape_ep.c | 119 +++++++++++++++++++++----------
3 files changed, 98 insertions(+), 48 deletions(-)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 93018feb7c..ea0fc43441 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -108,13 +108,13 @@ void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
}
/* Use bar match mode and MEM type as default */
-void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, int type,
- int bar, u64 phys)
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int type,
+ int idx, int bar, u64 phys)
{
dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
- dbi_writel(pcie, type, PCIE_ATU_CR1);
+ dbi_writel(pcie, type | PCIE_ATU_FUNC_NUM(pf), PCIE_ATU_CR1);
dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
}
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 217dcda6d1..dabfff32db 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -9,6 +9,7 @@
#define _PCIE_LAYERSCAPE_H_
#include <pci.h>
#include <dm.h>
+#include <linux/sizes.h>
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
@@ -44,6 +45,7 @@
#define PCIE_ATU_TYPE_IO (0x2 << 0)
#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
+#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
#define PCIE_ATU_CR2 0x908
#define PCIE_ATU_ENABLE (0x1 << 31)
#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
@@ -86,11 +88,16 @@
#define FSL_PCIE_EP_MIN_APERTURE 4096 /* 4 Kbytes */
#define PCIE_PF_NUM 2
#define PCIE_VF_NUM 64
+#define BAR_NUM 4
-#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
-#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
-#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
-#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
+#define PCIE_BAR0_SIZE SZ_4K
+#define PCIE_BAR1_SIZE SZ_8K
+#define PCIE_BAR2_SIZE SZ_4K
+#define PCIE_BAR4_SIZE SZ_1M
+
+#define PCIE_SRIOV_VFBAR0 0x19C
+
+#define PCIE_MASK_OFFSET(flag, pf) ((flag) ? 0 : (0x1000 + 0x20000 * (pf)))
/* LUT registers */
#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
@@ -158,6 +165,8 @@ struct ls_pcie_ep {
struct ls_pcie *pcie;
struct udevice *bus;
void __iomem *addr;
+ u32 cfg2_flag;
+ u32 sriov_flag;
u32 num_ib_wins;
u32 num_ob_wins;
u8 max_functions;
@@ -171,8 +180,8 @@ unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset);
void ctrl_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset);
void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
u64 phys, u64 bus_addr, pci_size_t size);
-void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, int type,
- int bar, u64 phys);
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int type,
+ int idx, int bar, u64 phys);
void ls_pcie_dump_atu(struct ls_pcie *pcie);
int ls_pcie_link_up(struct ls_pcie *pcie);
void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index b463a7734a..e609607c3a 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -46,7 +46,7 @@ static int ls_ep_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
else
type = PCIE_ATU_TYPE_IO;
- ls_pcie_atu_inbound_set(pcie, idx, bar, bar_phys, type);
+ ls_pcie_atu_inbound_set(pcie, fn, type, idx, bar, bar_phys);
dbi_writel(pcie, lower_32_bits(size - 1), reg + PCIE_NO_SRIOV_BAR_BASE);
dbi_writel(pcie, flags, reg);
@@ -64,51 +64,61 @@ static struct pci_ep_ops ls_pcie_ep_ops = {
.set_bar = ls_ep_set_bar,
};
-static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep)
+static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf)
{
struct ls_pcie *pcie = pcie_ep->pcie;
- u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
+ u64 phys = 0;
+ phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
+
+ phys = ALIGN(phys, PCIE_BAR0_SIZE);
/* ATU 0 : INBOUND : map BAR0 */
- ls_pcie_atu_inbound_set(pcie, 0, PCIE_ATU_TYPE_MEM, 0, phys);
+ ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
+ 0 + pf * BAR_NUM, 0, phys);
/* ATU 1 : INBOUND : map BAR1 */
- phys += PCIE_BAR1_SIZE;
- ls_pcie_atu_inbound_set(pcie, 1, PCIE_ATU_TYPE_MEM, 1, phys);
+ phys = ALIGN(phys + PCIE_BAR0_SIZE, PCIE_BAR1_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
+ 1 + pf * BAR_NUM, 1, phys);
/* ATU 2 : INBOUND : map BAR2 */
- phys += PCIE_BAR2_SIZE;
- ls_pcie_atu_inbound_set(pcie, 2, PCIE_ATU_TYPE_MEM, 2, phys);
- /* ATU 3 : INBOUND : map BAR4 */
- phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
- ls_pcie_atu_inbound_set(pcie, 3, PCIE_ATU_TYPE_MEM, 4, phys);
-
- /* ATU 0 : OUTBOUND : map MEM */
- ls_pcie_atu_outbound_set(pcie, 0,
- PCIE_ATU_TYPE_MEM,
- pcie_ep->addr_res.start,
- 0,
- CONFIG_SYS_PCI_MEMORY_SIZE);
+ phys = ALIGN(phys + PCIE_BAR1_SIZE, PCIE_BAR2_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
+ 2 + pf * BAR_NUM, 2, phys);
+ /* ATU 3 : INBOUND : map BAR2 */
+ phys = ALIGN(phys + PCIE_BAR2_SIZE, PCIE_BAR4_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
+ 3 + pf * BAR_NUM, 4, phys);
+
+ /* ATU: OUTBOUND : map MEM */
+ ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
+ (u64)pcie_ep->addr_res.start +
+ pf * CONFIG_SYS_PCI_MEMORY_SIZE,
+ 0, CONFIG_SYS_PCI_MEMORY_SIZE);
}
/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
{
+ u32 mask;
+
/* The least inbound window is 4KiB */
- if (size < 4 * 1024)
- return;
+ if (size < SZ_4K)
+ mask = 0;
+ else
+ mask = size - 1;
switch (bar) {
case 0:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
+ writel(mask, bar_base + PCI_BASE_ADDRESS_0);
break;
case 1:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
+ writel(mask, bar_base + PCI_BASE_ADDRESS_1);
break;
case 2:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
+ writel(mask, bar_base + PCI_BASE_ADDRESS_2);
writel(0, bar_base + PCI_BASE_ADDRESS_3);
break;
case 4:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
+ writel(mask, bar_base + PCI_BASE_ADDRESS_4);
writel(0, bar_base + PCI_BASE_ADDRESS_5);
break;
default:
@@ -118,39 +128,62 @@ static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
static void ls_pcie_ep_setup_bars(void *bar_base)
{
- /* BAR0 - 32bit - 4K configuration */
+ /* BAR0 - 32bit - MEM */
+ ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
+ /* BAR1 - 32bit - MEM*/
+ ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
+ /* BAR2 - 64bit - MEM */
+ ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
+ /* BAR4 - 64bit - MEM */
+ ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
+}
+
+static void ls_pcie_ep_setup_vf_bars(void *bar_base)
+{
+ /* VF BAR0 MASK register@offset 0x19c*/
+ bar_base += PCIE_SRIOV_VFBAR0 - PCI_BASE_ADDRESS_0;
+
+ /* VF-BAR0 - 32bit - MEM */
ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
- /* BAR1 - 32bit - 8K MSIX */
+ /* VF-BAR1 - 32bit - MEM*/
ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
- /* BAR2 - 64bit - 4K MEM descriptor */
+ /* VF-BAR2 - 64bit - MEM */
ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
- /* BAR4 - 64bit - 1M MEM */
+ /* VF-BAR4 - 64bit - MEM */
ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
}
static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
{
u32 sriov;
+ u32 pf, vf;
+ void *bar_base = NULL;
struct ls_pcie *pcie = pcie_ep->pcie;
sriov = readl(pcie->dbi + PCIE_SRIOV);
if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
- int pf, vf;
-
+ pcie_ep->sriov_flag = 1;
for (pf = 0; pf < PCIE_PF_NUM; pf++) {
- for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
- ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
- PCIE_PF_VF_CTRL);
-
- ls_pcie_ep_setup_bars(pcie->dbi);
- ls_pcie_ep_setup_atu(pcie_ep);
+ if (pcie_ep->cfg2_flag) {
+ for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+ ctrl_writel(pcie,
+ PCIE_LCTRL0_VAL(pf, vf),
+ PCIE_PF_VF_CTRL);
+ }
}
+ bar_base = pcie->dbi +
+ PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
+ ls_pcie_ep_setup_bars(bar_base);
+ ls_pcie_ep_setup_vf_bars(bar_base);
+
+ ls_pcie_ep_setup_atu(pcie_ep, pf);
}
- /* Disable CFG2 */
- ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
+
+ if (pcie_ep->cfg2_flag) /* Disable CFG2 */
+ ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
} else {
ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
- ls_pcie_ep_setup_atu(pcie_ep);
+ ls_pcie_ep_setup_atu(pcie_ep, 0);
}
ls_pcie_ep_enable_cfg(pcie_ep);
@@ -162,6 +195,7 @@ static int ls_pcie_ep_probe(struct udevice *dev)
struct ls_pcie *pcie;
u16 link_sta;
int ret;
+ u32 svr;
pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
if (!pcie)
@@ -191,6 +225,13 @@ static int ls_pcie_ep_probe(struct udevice *dev)
pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"big-endian");
+ svr = SVR_SOC_VER(get_svr());
+
+ if (svr == SVR_LS2080A || svr == SVR_LS2085A)
+ pcie_ep->cfg2_flag = 1;
+ else
+ pcie_ep->cfg2_flag = 0;
+
pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
if (pcie->mode != PCI_HEADER_TYPE_NORMAL)
return 0;
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCHv2 05/10] pci_ep: layerscape: Add the workaround for errata A-009460
2020-07-09 15:31 [PATCHv2 00/10] pci: layerscape: Split EP mode code into a Zhiqiang Hou
` (3 preceding siblings ...)
2020-07-09 15:31 ` [PATCHv2 04/10] PCI_EP: layerscape: Add the multiple function support Zhiqiang Hou
@ 2020-07-09 15:31 ` Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 06/10] pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode Zhiqiang Hou
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2020-07-09 15:31 UTC (permalink / raw)
To: u-boot
From: Xiaowei Bao <xiaowei.bao@nxp.com>
The VF_BARn_REG register's Prefetchable and Type bit fields
are overwritten by a write to VF's BAR Mask register.
workaround: Before writing to the VF_BARn_MASK_REG register,
write 0b to the PCIE_MISC_CONTROL_1_OFF register.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape_ep.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index e609607c3a..3f22c5ef7a 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -164,6 +164,15 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
pcie_ep->sriov_flag = 1;
for (pf = 0; pf < PCIE_PF_NUM; pf++) {
+ /*
+ * The VF_BARn_REG register's Prefetchable and Type bit
+ * fields are overwritten by a write to VF's BAR Mask
+ * register. Before writing to the VF_BARn_MASK_REG
+ * register, write 0b to the PCIE_MISC_CONTROL_1_OFF
+ * register.
+ */
+ writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
+
if (pcie_ep->cfg2_flag) {
for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
ctrl_writel(pcie,
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCHv2 06/10] pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode
2020-07-09 15:31 [PATCHv2 00/10] pci: layerscape: Split EP mode code into a Zhiqiang Hou
` (4 preceding siblings ...)
2020-07-09 15:31 ` [PATCHv2 05/10] pci_ep: layerscape: Add the workaround for errata A-009460 Zhiqiang Hou
@ 2020-07-09 15:31 ` Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 07/10] pci_ep: layerscape: Add the SRIOV VFs of PF support Zhiqiang Hou
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2020-07-09 15:31 UTC (permalink / raw)
To: u-boot
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Due to the ls2085a and ls2080a use different way to set the BAR size,
so add the BAR size init code here.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape_ep.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 3f22c5ef7a..20de056b8a 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -173,17 +173,25 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
*/
writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
+ bar_base = pcie->dbi +
+ PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
+
if (pcie_ep->cfg2_flag) {
- for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+ ctrl_writel(pcie,
+ PCIE_LCTRL0_VAL(pf, 0),
+ PCIE_PF_VF_CTRL);
+ ls_pcie_ep_setup_bars(bar_base);
+
+ for (vf = 1; vf <= PCIE_VF_NUM; vf++) {
ctrl_writel(pcie,
PCIE_LCTRL0_VAL(pf, vf),
PCIE_PF_VF_CTRL);
+ ls_pcie_ep_setup_vf_bars(bar_base);
}
+ } else {
+ ls_pcie_ep_setup_bars(bar_base);
+ ls_pcie_ep_setup_vf_bars(bar_base);
}
- bar_base = pcie->dbi +
- PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
- ls_pcie_ep_setup_bars(bar_base);
- ls_pcie_ep_setup_vf_bars(bar_base);
ls_pcie_ep_setup_atu(pcie_ep, pf);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCHv2 07/10] pci_ep: layerscape: Add the SRIOV VFs of PF support
2020-07-09 15:31 [PATCHv2 00/10] pci: layerscape: Split EP mode code into a Zhiqiang Hou
` (5 preceding siblings ...)
2020-07-09 15:31 ` [PATCHv2 06/10] pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode Zhiqiang Hou
@ 2020-07-09 15:31 ` Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 08/10] pci: layerscaple: Modify the ls_pcie_dump_atu function Zhiqiang Hou
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2020-07-09 15:31 UTC (permalink / raw)
To: u-boot
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Add the INBOUND configuration for VFs of PF.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape.c | 8 +++++---
drivers/pci/pcie_layerscape.h | 13 +++++++-----
drivers/pci/pcie_layerscape_ep.c | 34 +++++++++++++++++++++++++++-----
3 files changed, 42 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index ea0fc43441..0116af8aa5 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -95,7 +95,7 @@ int ls_pcie_link_up(struct ls_pcie *pcie)
}
void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
- u64 phys, u64 bus_addr, pci_size_t size)
+ u64 phys, u64 bus_addr, u64 size)
{
dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
@@ -108,14 +108,16 @@ void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
}
/* Use bar match mode and MEM type as default */
-void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int type,
- int idx, int bar, u64 phys)
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
+ int type, int idx, int bar, u64 phys)
{
dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
dbi_writel(pcie, type | PCIE_ATU_FUNC_NUM(pf), PCIE_ATU_CR1);
dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
+ (vf_flag ? PCIE_ATU_FUNC_NUM_MATCH_EN : 0) |
+ (vf_flag ? PCIE_ATU_VFBAR_MATCH_MODE_EN : 0) |
PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
}
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index dabfff32db..26d0177ca2 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -20,7 +20,7 @@
#endif
#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
-#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
+#define CONFIG_SYS_PCI_MEMORY_SIZE SZ_4G
#endif
#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
@@ -40,6 +40,7 @@
#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
#define PCIE_ATU_REGION_NUM 6
+#define PCIE_ATU_REGION_NUM_SRIOV 24
#define PCIE_ATU_CR1 0x904
#define PCIE_ATU_TYPE_MEM (0x0 << 0)
#define PCIE_ATU_TYPE_IO (0x2 << 0)
@@ -49,6 +50,8 @@
#define PCIE_ATU_CR2 0x908
#define PCIE_ATU_ENABLE (0x1 << 31)
#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
+#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
+#define PCIE_ATU_VFBAR_MATCH_MODE_EN BIT(26)
#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
#define PCIE_ATU_LOWER_BASE 0x90C
#define PCIE_ATU_UPPER_BASE 0x910
@@ -88,7 +91,7 @@
#define FSL_PCIE_EP_MIN_APERTURE 4096 /* 4 Kbytes */
#define PCIE_PF_NUM 2
#define PCIE_VF_NUM 64
-#define BAR_NUM 4
+#define BAR_NUM 8
#define PCIE_BAR0_SIZE SZ_4K
#define PCIE_BAR1_SIZE SZ_8K
@@ -179,9 +182,9 @@ void dbi_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset);
unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset);
void ctrl_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset);
void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
- u64 phys, u64 bus_addr, pci_size_t size);
-void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int type,
- int idx, int bar, u64 phys);
+ u64 phys, u64 bus_addr, u64 size);
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
+ int type, int idx, int bar, u64 phys);
void ls_pcie_dump_atu(struct ls_pcie *pcie);
int ls_pcie_link_up(struct ls_pcie *pcie);
void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 20de056b8a..cbf73e72c1 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -46,7 +46,7 @@ static int ls_ep_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
else
type = PCIE_ATU_TYPE_IO;
- ls_pcie_atu_inbound_set(pcie, fn, type, idx, bar, bar_phys);
+ ls_pcie_atu_inbound_set(pcie, fn, 0, type, idx, bar, bar_phys);
dbi_writel(pcie, lower_32_bits(size - 1), reg + PCIE_NO_SRIOV_BAR_BASE);
dbi_writel(pcie, flags, reg);
@@ -67,27 +67,51 @@ static struct pci_ep_ops ls_pcie_ep_ops = {
static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf)
{
struct ls_pcie *pcie = pcie_ep->pcie;
+ u32 vf_flag = 0;
u64 phys = 0;
phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
phys = ALIGN(phys, PCIE_BAR0_SIZE);
/* ATU 0 : INBOUND : map BAR0 */
- ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
0 + pf * BAR_NUM, 0, phys);
/* ATU 1 : INBOUND : map BAR1 */
phys = ALIGN(phys + PCIE_BAR0_SIZE, PCIE_BAR1_SIZE);
- ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
1 + pf * BAR_NUM, 1, phys);
/* ATU 2 : INBOUND : map BAR2 */
phys = ALIGN(phys + PCIE_BAR1_SIZE, PCIE_BAR2_SIZE);
- ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
2 + pf * BAR_NUM, 2, phys);
/* ATU 3 : INBOUND : map BAR2 */
phys = ALIGN(phys + PCIE_BAR2_SIZE, PCIE_BAR4_SIZE);
- ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
3 + pf * BAR_NUM, 4, phys);
+ if (pcie_ep->sriov_flag) {
+ vf_flag = 1;
+ /* ATU 4 : INBOUND : map BAR0 */
+ phys = ALIGN(phys + PCIE_BAR4_SIZE, PCIE_BAR0_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+ 4 + pf * BAR_NUM, 0, phys);
+ /* ATU 5 : INBOUND : map BAR1 */
+ phys = ALIGN(phys + PCIE_BAR0_SIZE * PCIE_VF_NUM,
+ PCIE_BAR1_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+ 5 + pf * BAR_NUM, 1, phys);
+ /* ATU 6 : INBOUND : map BAR2 */
+ phys = ALIGN(phys + PCIE_BAR1_SIZE * PCIE_VF_NUM,
+ PCIE_BAR2_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+ 6 + pf * BAR_NUM, 2, phys);
+ /* ATU 7 : INBOUND : map BAR4 */
+ phys = ALIGN(phys + PCIE_BAR2_SIZE * PCIE_VF_NUM,
+ PCIE_BAR4_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+ 7 + pf * BAR_NUM, 4, phys);
+ }
+
/* ATU: OUTBOUND : map MEM */
ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
(u64)pcie_ep->addr_res.start +
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCHv2 08/10] pci: layerscaple: Modify the ls_pcie_dump_atu function
2020-07-09 15:31 [PATCHv2 00/10] pci: layerscape: Split EP mode code into a Zhiqiang Hou
` (6 preceding siblings ...)
2020-07-09 15:31 ` [PATCHv2 07/10] pci_ep: layerscape: Add the SRIOV VFs of PF support Zhiqiang Hou
@ 2020-07-09 15:31 ` Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 09/10] pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2 Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 10/10] pci: layerscape: Add specific config entry for RC and EP mode driver Zhiqiang Hou
9 siblings, 0 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2020-07-09 15:31 UTC (permalink / raw)
To: u-boot
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Modify the ls_pcie_dump_atu function, make it can print the INBOUND
windows registers.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape.c | 25 +++++++++++++------------
drivers/pci/pcie_layerscape.h | 2 +-
drivers/pci/pcie_layerscape_ep.c | 3 +++
drivers/pci/pcie_layerscape_rc.c | 2 +-
4 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 0116af8aa5..25b5272d4e 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -121,24 +121,25 @@ void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
}
-void ls_pcie_dump_atu(struct ls_pcie *pcie)
+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type)
{
- int i;
+ int win_idx;
- for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
- dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
- PCIE_ATU_VIEWPORT);
- debug("iATU%d:\n", i);
+ for (win_idx = 0; win_idx < win_num; win_idx++) {
+ dbi_writel(pcie, type | win_idx, PCIE_ATU_VIEWPORT);
+ debug("iATU%d:\n", win_idx);
debug("\tLOWER PHYS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
debug("\tUPPER PHYS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
- debug("\tLOWER BUS 0x%08x\n",
- dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
- debug("\tUPPER BUS 0x%08x\n",
- dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
- debug("\tLIMIT 0x%08x\n",
- dbi_readl(pcie, PCIE_ATU_LIMIT));
+ if (type == PCIE_ATU_REGION_OUTBOUND) {
+ debug("\tLOWER BUS 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
+ debug("\tUPPER BUS 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
+ debug("\tLIMIT 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_LIMIT));
+ }
debug("\tCR1 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_CR1));
debug("\tCR2 0x%08x\n",
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 26d0177ca2..5f5c51d3d6 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -185,7 +185,7 @@ void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
u64 phys, u64 bus_addr, u64 size);
void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
int type, int idx, int bar, u64 phys);
-void ls_pcie_dump_atu(struct ls_pcie *pcie);
+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type);
int ls_pcie_link_up(struct ls_pcie *pcie);
void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie);
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index cbf73e72c1..52d6397064 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -227,6 +227,9 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
ls_pcie_ep_setup_atu(pcie_ep, 0);
}
+ ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM_SRIOV,
+ PCIE_ATU_REGION_INBOUND);
+
ls_pcie_ep_enable_cfg(pcie_ep);
}
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index e922e5dbcd..25c6ddebce 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -115,7 +115,7 @@ static void ls_pcie_setup_atu(struct ls_pcie_rc *pcie_rc)
pref->bus_start,
pref->size);
- ls_pcie_dump_atu(pcie);
+ ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM, PCIE_ATU_REGION_OUTBOUND);
}
/* Return 0 if the address is valid, -errno if not valid */
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCHv2 09/10] pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2
2020-07-09 15:31 [PATCHv2 00/10] pci: layerscape: Split EP mode code into a Zhiqiang Hou
` (7 preceding siblings ...)
2020-07-09 15:31 ` [PATCHv2 08/10] pci: layerscaple: Modify the ls_pcie_dump_atu function Zhiqiang Hou
@ 2020-07-09 15:31 ` Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 10/10] pci: layerscape: Add specific config entry for RC and EP mode driver Zhiqiang Hou
9 siblings, 0 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2020-07-09 15:31 UTC (permalink / raw)
To: u-boot
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Add the PCIe EP mode support for lx2160a-v2 platform.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape.h | 9 ++++++++-
drivers/pci/pcie_layerscape_ep.c | 8 +++++++-
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 5f5c51d3d6..593798e3e3 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -100,7 +100,7 @@
#define PCIE_SRIOV_VFBAR0 0x19C
-#define PCIE_MASK_OFFSET(flag, pf) ((flag) ? 0 : (0x1000 + 0x20000 * (pf)))
+#define PCIE_MASK_OFFSET(flag, pf, off) ((flag) ? 0 : (0x1000 + (off) * (pf)))
/* LUT registers */
#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
@@ -139,6 +139,12 @@
#define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
#define LS1021_LTSSM_STATE_SHIFT 20
+/* LX2160a PF1 offset */
+#define LX2160_PCIE_PF1_OFFSET 0x8000
+
+/* layerscape PF1 offset */
+#define LS_PCIE_PF1_OFFSET 0x20000
+
struct ls_pcie {
void __iomem *dbi;
void __iomem *lut;
@@ -170,6 +176,7 @@ struct ls_pcie_ep {
void __iomem *addr;
u32 cfg2_flag;
u32 sriov_flag;
+ u32 pf1_offset;
u32 num_ib_wins;
u32 num_ob_wins;
u8 max_functions;
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 52d6397064..eba230e3a5 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -198,7 +198,8 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
bar_base = pcie->dbi +
- PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
+ PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf,
+ pcie_ep->pf1_offset);
if (pcie_ep->cfg2_flag) {
ctrl_writel(pcie,
@@ -271,6 +272,11 @@ static int ls_pcie_ep_probe(struct udevice *dev)
svr = SVR_SOC_VER(get_svr());
+ if (svr == SVR_LX2160A)
+ pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET;
+ else
+ pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET;
+
if (svr == SVR_LS2080A || svr == SVR_LS2085A)
pcie_ep->cfg2_flag = 1;
else
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCHv2 10/10] pci: layerscape: Add specific config entry for RC and EP mode driver
2020-07-09 15:31 [PATCHv2 00/10] pci: layerscape: Split EP mode code into a Zhiqiang Hou
` (8 preceding siblings ...)
2020-07-09 15:31 ` [PATCHv2 09/10] pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2 Zhiqiang Hou
@ 2020-07-09 15:31 ` Zhiqiang Hou
9 siblings, 0 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2020-07-09 15:31 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add Root Complex and Endpoint mode specific config entries, such that
it's feasible to enable the RC and/or EP mode driver indepently.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- New patch.
configs/ls1012afrdm_qspi_defconfig | 2 +-
configs/ls1012afrdm_tfa_defconfig | 2 +-
.../ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls1012afrwy_qspi_defconfig | 2 +-
configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1012afrwy_tfa_defconfig | 2 +-
configs/ls1012aqds_qspi_defconfig | 2 +-
configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1012aqds_tfa_defconfig | 2 +-
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls1012ardb_qspi_defconfig | 2 +-
configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1012ardb_tfa_defconfig | 2 +-
configs/ls1021aiot_qspi_defconfig | 2 +-
configs/ls1021aiot_sdcard_defconfig | 2 +-
configs/ls1021aqds_ddr4_nor_defconfig | 2 +-
configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 2 +-
configs/ls1021aqds_nand_defconfig | 2 +-
configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 +-
configs/ls1021aqds_nor_defconfig | 2 +-
configs/ls1021aqds_nor_lpuart_defconfig | 2 +-
configs/ls1021aqds_qspi_defconfig | 2 +-
configs/ls1021aqds_sdcard_ifc_defconfig | 2 +-
configs/ls1021aqds_sdcard_qspi_defconfig | 2 +-
configs/ls1021atsn_qspi_defconfig | 2 +-
configs/ls1021atsn_sdcard_defconfig | 2 +-
configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 +-
configs/ls1021atwr_nor_defconfig | 2 +-
configs/ls1021atwr_nor_lpuart_defconfig | 2 +-
configs/ls1021atwr_qspi_defconfig | 2 +-
...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 +-
configs/ls1021atwr_sdcard_ifc_defconfig | 2 +-
configs/ls1021atwr_sdcard_qspi_defconfig | 2 +-
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1028aqds_tfa_defconfig | 2 +-
configs/ls1028aqds_tfa_lpuart_defconfig | 2 +-
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1028ardb_tfa_defconfig | 2 +-
configs/ls1043aqds_defconfig | 2 +-
configs/ls1043aqds_lpuart_defconfig | 2 +-
configs/ls1043aqds_nand_defconfig | 2 +-
configs/ls1043aqds_nor_ddr3_defconfig | 2 +-
configs/ls1043aqds_qspi_defconfig | 2 +-
configs/ls1043aqds_sdcard_ifc_defconfig | 2 +-
configs/ls1043aqds_sdcard_qspi_defconfig | 2 +-
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1043aqds_tfa_defconfig | 2 +-
configs/ls1043ardb_SECURE_BOOT_defconfig | 2 +-
configs/ls1043ardb_defconfig | 2 +-
configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 +-
configs/ls1043ardb_nand_defconfig | 2 +-
.../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 +-
configs/ls1043ardb_sdcard_defconfig | 2 +-
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1043ardb_tfa_defconfig | 2 +-
configs/ls1046afrwy_tfa_defconfig | 3 +-
configs/ls1046aqds_SECURE_BOOT_defconfig | 3 +-
configs/ls1046aqds_defconfig | 3 +-
configs/ls1046aqds_lpuart_defconfig | 3 +-
configs/ls1046aqds_nand_defconfig | 3 +-
configs/ls1046aqds_qspi_defconfig | 3 +-
configs/ls1046aqds_sdcard_ifc_defconfig | 3 +-
configs/ls1046aqds_sdcard_qspi_defconfig | 3 +-
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 3 +-
configs/ls1046aqds_tfa_defconfig | 3 +-
configs/ls1046ardb_emmc_defconfig | 3 +-
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 3 +-
configs/ls1046ardb_qspi_defconfig | 3 +-
configs/ls1046ardb_qspi_spl_defconfig | 3 +-
.../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 3 +-
configs/ls1046ardb_sdcard_defconfig | 3 +-
configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 3 +-
configs/ls1046ardb_tfa_defconfig | 3 +-
configs/ls1088aqds_defconfig | 2 +-
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls1088aqds_qspi_defconfig | 2 +-
configs/ls1088aqds_sdcard_ifc_defconfig | 2 +-
configs/ls1088aqds_sdcard_qspi_defconfig | 2 +-
configs/ls1088aqds_tfa_defconfig | 2 +-
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls1088ardb_qspi_defconfig | 2 +-
...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls1088ardb_sdcard_qspi_defconfig | 2 +-
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1088ardb_tfa_defconfig | 2 +-
configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +-
configs/ls2080aqds_defconfig | 2 +-
configs/ls2080aqds_nand_defconfig | 2 +-
configs/ls2080aqds_qspi_defconfig | 2 +-
configs/ls2080aqds_sdcard_defconfig | 2 +-
configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +-
configs/ls2080ardb_defconfig | 2 +-
configs/ls2080ardb_nand_defconfig | 2 +-
configs/ls2081ardb_defconfig | 2 +-
configs/ls2088aqds_tfa_defconfig | 2 +-
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls2088ardb_qspi_defconfig | 2 +-
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls2088ardb_tfa_defconfig | 2 +-
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 4 +--
configs/lx2160aqds_tfa_defconfig | 4 +--
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 4 +--
configs/lx2160ardb_tfa_defconfig | 4 +--
configs/lx2160ardb_tfa_stmm_defconfig | 4 +--
drivers/pci/Kconfig | 29 +++++++++++++++----
drivers/pci/Makefile | 7 +++--
106 files changed, 155 insertions(+), 117 deletions(-)
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 541cbb07ce..36424859d6 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -49,7 +49,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig
index b5043d7a18..86edeb8903 100644
--- a/configs/ls1012afrdm_tfa_defconfig
+++ b/configs/ls1012afrdm_tfa_defconfig
@@ -49,7 +49,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
index f105aaf2bc..bf3db5a656 100644
--- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
@@ -47,7 +47,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig
index 492276439e..5054440ed5 100644
--- a/configs/ls1012afrwy_qspi_defconfig
+++ b/configs/ls1012afrwy_qspi_defconfig
@@ -51,7 +51,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
index 9c89064150..9a0f284f54 100644
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
@@ -47,7 +47,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig
index 2948fd57ec..e5f9fb33d8 100644
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig
@@ -51,7 +51,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 65e8e5c791..a9a6f2d794 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -68,7 +68,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index 529cd08b12..8b8d964d5b 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -57,7 +57,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index 79d196c77b..44845b4b6e 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -68,7 +68,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
index 1483e64d8c..3f8701378f 100644
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
@@ -50,7 +50,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index e39de4caf5..8c35c3c07f 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -54,7 +54,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
index 8b67798429..546982bd2c 100644
--- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
@@ -51,7 +51,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig
index e0d203d442..e19d81eef7 100644
--- a/configs/ls1012ardb_tfa_defconfig
+++ b/configs/ls1012ardb_tfa_defconfig
@@ -53,7 +53,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
index dba33e2a9b..36d79de074 100644
--- a/configs/ls1021aiot_qspi_defconfig
+++ b/configs/ls1021aiot_qspi_defconfig
@@ -38,7 +38,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index fc6df70db7..c373cec6f0 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -44,7 +44,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 24e0316eb1..b3194875d5 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -59,7 +59,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index f0f3a747c6..8906879ab2 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -60,7 +60,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 8a88c5fd39..bc1598002d 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -76,7 +76,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 547b6393ba..f391234f7b 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -58,7 +58,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 58d251b908..72b5878a6b 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -60,7 +60,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index f74a4c6b29..cb348e1aa1 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -61,7 +61,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index f91534cfdd..207a43d5c6 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -59,7 +59,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 8d34213855..4fb1c86e8f 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -75,7 +75,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 9871c8edf4..17c0baada0 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -71,7 +71,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index a62e04e92a..246260c8fa 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -49,7 +49,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index db4f0ab796..04fb5c1cbe 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -60,7 +60,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 0bf4aad102..2cc67ec9a1 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -52,7 +52,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 5507dbe3c1..4e0ce7f66a 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -54,7 +54,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index cdf81957a8..7eecbcb181 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -56,7 +56,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 4c82d66899..768d5f0b3b 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -57,7 +57,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 9039ccc8f2..f2a4e427a8 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -67,7 +67,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 478d3df1b8..40a9dbe16d 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -69,7 +69,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index de783a8d3d..6bd969da0f 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -68,7 +68,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index 4fd9ff8f3a..98e77bc296 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -64,7 +64,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index fc6344cd7c..1dfd81a6db 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -70,7 +70,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig
index e0348279d9..c7f7359096 100644
--- a/configs/ls1028aqds_tfa_lpuart_defconfig
+++ b/configs/ls1028aqds_tfa_lpuart_defconfig
@@ -70,7 +70,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index 96f190d859..6dcce3234c 100644
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -61,7 +61,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index 1f05ae57cc..94148666c1 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -67,7 +67,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index da56fce693..a4bbd2de67 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -58,7 +58,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 9d450b3d63..defbd37c63 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -59,7 +59,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index a08ec2a7e4..6cfe90bfb0 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -74,7 +74,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index fe025facdd..fbdbdb49cc 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -59,7 +59,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index a018b22fa9..2b215a3b1f 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -54,7 +54,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 862458c7c7..1e34e003db 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -75,7 +75,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index a7252ac115..2dbd24f0ce 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -68,7 +68,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index 3ee5d2869c..54f24f8d5e 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
@@ -58,7 +58,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 297788b648..6ae2770570 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -68,7 +68,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 911bbef72c..5e66743a57 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -49,7 +49,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 4a15992f7c..99c61c45e2 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -52,7 +52,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index f399b1cbb3..70862d67df 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -69,7 +69,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 5f794605d6..f7acd3d537 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -70,7 +70,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 224321810a..b98d1c68b4 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -68,7 +68,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index bf557d7650..651d0bbd34 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -69,7 +69,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 0f3f920ffd..5b36322c38 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -51,7 +51,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index a62310ccc9..a4667de206 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -57,7 +57,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index 68271c35b2..f8c8f6176c 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -51,7 +51,8 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig
index caa4221875..15ff486ff6 100644
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig
@@ -54,7 +54,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 838d97cde4..4f0e22b78e 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -57,7 +57,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
index d89b7791b2..460527039e 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -58,7 +58,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index 4aebca7108..8b40a694cd 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -65,7 +65,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index 00b3568276..2d6fe28800 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -54,7 +54,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index a68c43566d..7c48e1f944 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -75,7 +75,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index a66b1bdca9..06046dbaa9 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -69,7 +69,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index 2b84a6bee5..77a5e6381a 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
@@ -57,7 +57,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index e412c05b53..5b29fdf212 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -67,7 +67,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index def9140fd6..49d4918fdd 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -67,7 +67,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index f29e86b8f9..fd9531d7d8 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -49,7 +49,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 51978686b5..6ebdd96cd5 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -53,7 +53,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index cbc598dea8..94efdaa796 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -70,7 +70,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index aeac0a248e..0ebe750072 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -63,7 +63,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 878bdf0513..e370533f80 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -66,7 +66,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index 7db5174111..b9a283138f 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -49,7 +49,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 06bedd66ff..1c95896264 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -55,7 +55,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig
index 61e05ceda6..f8be3a66bb 100644
--- a/configs/ls1088aqds_defconfig
+++ b/configs/ls1088aqds_defconfig
@@ -55,7 +55,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
index e51fdcab20..b63cde7702 100644
--- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
@@ -53,7 +53,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
index f7d0c15707..88ebb2cdb5 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -56,7 +56,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
index 57e706a4c4..4a006e1684 100644
--- a/configs/ls1088aqds_sdcard_ifc_defconfig
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig
@@ -65,7 +65,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index 4ff7173369..401225d21b 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -66,7 +66,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index c184843a6d..cbfa7d1107 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -79,7 +79,7 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
index f00307f964..d779c89d70 100644
--- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
@@ -55,7 +55,7 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
index 0572c9c241..43fab8ce72 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig
@@ -58,7 +58,7 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 3e00a25857..fc7289a0bc 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -67,7 +67,7 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index b6e21b2756..2b9578e8a3 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -68,7 +68,7 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index dba4526734..1f332857e3 100644
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
@@ -62,7 +62,7 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index 53b236ce9e..5618c05cac 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -67,7 +67,7 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index efbd5f75bd..6be03d1316 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -54,7 +54,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index ad53671e6c..e30490db5a 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -57,7 +57,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 590ca28000..c1410f198d 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -64,7 +64,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index b8fbb43eb3..4bc19d735d 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -56,7 +56,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index d493febf4b..008742b884 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -63,7 +63,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 21739f0f9e..dda7de618d 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -51,7 +51,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index dc4564b318..f253ccc884 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -54,7 +54,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index a3fa5c6bbf..ce5f4f879f 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -62,7 +62,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
index 9d08eb7af7..ed80dc9e4a 100644
--- a/configs/ls2081ardb_defconfig
+++ b/configs/ls2081ardb_defconfig
@@ -49,7 +49,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index ad17ef1703..92057f16e1 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -76,7 +76,7 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index be073b6724..bcf47032a2 100644
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -49,7 +49,7 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index f2eb8d765a..fc6a6e0d51 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -56,7 +56,7 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index a244af17bc..638dee75ae 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -64,7 +64,7 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index b64e3dc1d2..c2853e12de 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -73,7 +73,7 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index 51d5dc356e..5304de4992 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -65,8 +65,8 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_RC_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index 716c089ba9..e69fccac3c 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -69,8 +69,8 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_RC_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index 23f814fb6c..5f7bbc08d5 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -57,8 +57,8 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_RC_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index bc654cfee9..c6d5b23dd3 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -63,8 +63,8 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_RC_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig
index 5f181a3868..aacdb9b72b 100644
--- a/configs/lx2160ardb_tfa_stmm_defconfig
+++ b/configs/lx2160ardb_tfa_stmm_defconfig
@@ -66,8 +66,8 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_RC_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 6fc26884e2..c445a04487 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -128,12 +128,29 @@ config PCI_XILINX
which can be used on some generations of Xilinx FPGAs.
config PCIE_LAYERSCAPE
- bool "Layerscape PCIe support"
+ bool
+ default n
+
+config PCIE_LAYERSCAPE_RC
+ bool "Layerscape PCIe Root Complex mode support"
+ depends on DM_PCI
+ select PCIE_LAYERSCAPE
+ help
+ Enable Layerscape PCIe Root Complex mode driver support. The Layerscape
+ SoC may have one or several PCIe controllers. Each controller can be
+ configured to Root Complex mode by clearing the corresponding bit of
+ RCW[HOST_AGT_PEX].
+
+config PCIE_LAYERSCAPE_EP
+ bool "Layerscape PCIe Endpoint mode support"
depends on DM_PCI
+ select PCIE_LAYERSCAPE
+ select PCI_ENDPOINT
help
- Support Layerscape PCIe. The Layerscape SoC may have one or several
- PCIe controllers. The PCIe may works in RC or EP mode according to
- RCW[HOST_AGT_PEX] setting.
+ Enable Layerscape PCIe Endpoint mode driver support. The Layerscape
+ SoC may have one or several PCIe controllers. Each controller can be
+ configured to Endpoint mode by setting the corresponding bit of
+ RCW[HOST_AGT_PEX].
config PCIE_LAYERSCAPE_GEN4
bool "Layerscape Gen4 PCIe support"
@@ -145,7 +162,7 @@ config PCIE_LAYERSCAPE_GEN4
config FSL_PCIE_COMPAT
string "PCIe compatible of Kernel DT"
- depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
+ depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
default "fsl,ls1012a-pcie" if ARCH_LS1012A
default "fsl,ls1028a-pcie" if ARCH_LS1028A
default "fsl,ls1043a-pcie" if ARCH_LS1043A
@@ -160,7 +177,7 @@ config FSL_PCIE_COMPAT
config FSL_PCIE_EP_COMPAT
string "PCIe EP compatible of Kernel DT"
- depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
+ depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
default "fsl,ls-pcie-ep"
help
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 440b5af588..9465373b5c 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -33,8 +33,11 @@ obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
-obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o pcie_layerscape_rc.o pcie_layerscape_ep.o
-obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o pcie_layerscape_fixup_common.o
+obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
+obj-$(CONFIG_PCIE_LAYERSCAPE_RC) += pcie_layerscape_rc.o \
+ pcie_layerscape_fixup.o \
+ pcie_layerscape_fixup_common.o
+obj-$(CONFIG_PCIE_LAYERSCAPE_EP) += pcie_layerscape_ep.o
obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
pcie_layerscape_gen4_fixup.o \
pcie_layerscape_fixup_common.o
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-07-09 15:31 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-09 15:31 [PATCHv2 00/10] pci: layerscape: Split EP mode code into a Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 01/10] pci: layerscape: Split the EP and RC driver Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 02/10] pci_ep: Add the init function Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 03/10] armv8: dts: ls1046a: Add the PCIe EP node Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 04/10] PCI_EP: layerscape: Add the multiple function support Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 05/10] pci_ep: layerscape: Add the workaround for errata A-009460 Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 06/10] pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 07/10] pci_ep: layerscape: Add the SRIOV VFs of PF support Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 08/10] pci: layerscaple: Modify the ls_pcie_dump_atu function Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 09/10] pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2 Zhiqiang Hou
2020-07-09 15:31 ` [PATCHv2 10/10] pci: layerscape: Add specific config entry for RC and EP mode driver Zhiqiang Hou
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