[PATCH] arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core

* [PATCH] arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core
@ 2020-09-30 15:54 ` Lucas Stach
  0 siblings, 0 replies; 6+ messages in thread
From: Lucas Stach @ 2020-09-30 15:54 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Fabio Estevam, Frieder Schrempf, Marek Vasut,
	linux-arm-kernel, devicetree, kernel, patchwork-lst

From: Frieder Schrempf <frieder.schrempf@kontron.de>

According to the documents, the i.MX8M-Mini features a GC320 and a
GCNanoUltra GPU core. Etnaviv detects them as:

	etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653
	etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341

This seems to work fine more or less without any changes to the HWDB,
which still might be needed in the future to correct some features,
etc.

[lst]: Added power domains and switched clock assignments to the
       new clock defines used for the composite clocks, instead of
       relying on the backwards compat defines.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
This patch depends on the power domain support for i.MX8MM, as the
GPUs are in a invalid state (which might lead to full system lockups)
if they are not properly powered on via the power sequencing
implemented in the GPCv2 driver.
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 39 +++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index ab379d02d4e4..2f5812763315 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1012,6 +1012,45 @@
 			status = "disabled";
 		};
 
+		gpu_3d: gpu@38000000 {
+			compatible = "vivante,gc";
+			reg = <0x38000000 0x8000>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+			         <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+			         <&clk IMX8MM_CLK_GPU3D_ROOT>,
+			         <&clk IMX8MM_CLK_GPU3D_ROOT>;
+			clock-names = "reg", "bus", "core", "shader";
+			assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
+			                  <&clk IMX8MM_CLK_GPU_AXI>,
+			                  <&clk IMX8MM_CLK_GPU_AHB>,
+			                  <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>,
+			                         <&clk IMX8MM_SYS_PLL1_800M>,
+			                         <&clk IMX8MM_SYS_PLL1_800M>;
+			assigned-clock-rates = <0>, <0>,<400000000>,<1000000000>;
+			power-domains = <&pgc_gpu>;
+		};
+
+		gpu_2d: gpu@38008000 {
+			compatible = "vivante,gc";
+			reg = <0x38008000 0x8000>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+			         <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+			         <&clk IMX8MM_CLK_GPU2D_ROOT>;
+			clock-names = "reg", "bus", "core";
+			assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
+			                  <&clk IMX8MM_CLK_GPU_AXI>,
+			                  <&clk IMX8MM_CLK_GPU_AHB>,
+			                  <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>,
+			                         <&clk IMX8MM_SYS_PLL1_800M>,
+			                         <&clk IMX8MM_SYS_PLL1_800M>;
+			assigned-clock-rates = <0>, <0>,<400000000>,<1000000000>;
+			power-domains = <&pgc_gpu>;
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>, /* GIC Dist */
-- 
2.20.1


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