* [PATCH] arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD
@ 2020-10-01 9:39 Will Deacon
2020-10-01 9:52 ` Catalin Marinas
0 siblings, 1 reply; 4+ messages in thread
From: Will Deacon @ 2020-10-01 9:39 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Catalin Marinas, Will Deacon
TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local
TLB after setting the bit when detected support for the feature. Although
this isn't strictly necessary, since we can happily operate with the bit
effectively clear, the current code uses an ISB in a half-hearted attempt
to make the change effective, so let's just fix that up.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
---
arch/arm64/kernel/cpufeature.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 6424584be01e..29de76046977 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1442,7 +1442,7 @@ static inline void __cpu_enable_hw_dbm(void)
u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
write_sysreg(tcr, tcr_el1);
- isb();
+ local_flush_tlb_all();
}
static bool cpu_has_broken_dbm(void)
--
2.28.0.709.gb0816b6eb0-goog
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD
2020-10-01 9:39 [PATCH] arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD Will Deacon
@ 2020-10-01 9:52 ` Catalin Marinas
2020-10-01 10:32 ` Will Deacon
2020-10-01 10:33 ` Mark Rutland
0 siblings, 2 replies; 4+ messages in thread
From: Catalin Marinas @ 2020-10-01 9:52 UTC (permalink / raw)
To: Will Deacon; +Cc: linux-arm-kernel
On Thu, Oct 01, 2020 at 10:39:20AM +0100, Will Deacon wrote:
> TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local
> TLB after setting the bit when detected support for the feature. Although
> this isn't strictly necessary, since we can happily operate with the bit
> effectively clear, the current code uses an ISB in a half-hearted attempt
> to make the change effective, so let's just fix that up.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
> arch/arm64/kernel/cpufeature.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 6424584be01e..29de76046977 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1442,7 +1442,7 @@ static inline void __cpu_enable_hw_dbm(void)
> u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
>
> write_sysreg(tcr, tcr_el1);
> - isb();
> + local_flush_tlb_all();
Is the TLBI ordered with the TCR_EL1 write or we need the ISB as well?
--
Catalin
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD
2020-10-01 9:52 ` Catalin Marinas
@ 2020-10-01 10:32 ` Will Deacon
2020-10-01 10:33 ` Mark Rutland
1 sibling, 0 replies; 4+ messages in thread
From: Will Deacon @ 2020-10-01 10:32 UTC (permalink / raw)
To: Catalin Marinas; +Cc: linux-arm-kernel
On Thu, Oct 01, 2020 at 10:52:52AM +0100, Catalin Marinas wrote:
> On Thu, Oct 01, 2020 at 10:39:20AM +0100, Will Deacon wrote:
> > TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local
> > TLB after setting the bit when detected support for the feature. Although
> > this isn't strictly necessary, since we can happily operate with the bit
> > effectively clear, the current code uses an ISB in a half-hearted attempt
> > to make the change effective, so let's just fix that up.
> >
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Signed-off-by: Will Deacon <will@kernel.org>
> > ---
> > arch/arm64/kernel/cpufeature.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > index 6424584be01e..29de76046977 100644
> > --- a/arch/arm64/kernel/cpufeature.c
> > +++ b/arch/arm64/kernel/cpufeature.c
> > @@ -1442,7 +1442,7 @@ static inline void __cpu_enable_hw_dbm(void)
> > u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
> >
> > write_sysreg(tcr, tcr_el1);
> > - isb();
> > + local_flush_tlb_all();
>
> Is the TLBI ordered with the TCR_EL1 write or we need the ISB as well?
Good catch! I think this is direct-write -> indirect-read ordering, which
needs the ISB. so I'll keep it and add the flush immediately afterwards.
Will
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD
2020-10-01 9:52 ` Catalin Marinas
2020-10-01 10:32 ` Will Deacon
@ 2020-10-01 10:33 ` Mark Rutland
1 sibling, 0 replies; 4+ messages in thread
From: Mark Rutland @ 2020-10-01 10:33 UTC (permalink / raw)
To: Catalin Marinas; +Cc: Will Deacon, linux-arm-kernel
On Thu, Oct 01, 2020 at 10:52:52AM +0100, Catalin Marinas wrote:
> On Thu, Oct 01, 2020 at 10:39:20AM +0100, Will Deacon wrote:
> > TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local
> > TLB after setting the bit when detected support for the feature. Although
> > this isn't strictly necessary, since we can happily operate with the bit
> > effectively clear, the current code uses an ISB in a half-hearted attempt
> > to make the change effective, so let's just fix that up.
> >
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Signed-off-by: Will Deacon <will@kernel.org>
> > ---
> > arch/arm64/kernel/cpufeature.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > index 6424584be01e..29de76046977 100644
> > --- a/arch/arm64/kernel/cpufeature.c
> > +++ b/arch/arm64/kernel/cpufeature.c
> > @@ -1442,7 +1442,7 @@ static inline void __cpu_enable_hw_dbm(void)
> > u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
> >
> > write_sysreg(tcr, tcr_el1);
> > - isb();
> > + local_flush_tlb_all();
>
> Is the TLBI ordered with the TCR_EL1 write or we need the ISB as well?
I believe we still need the ISB prior to the TLBI since MSR and TLBI are
not usually ordered w.r.t. one another, so after teh TLBI it might still
be possible to allcote the stale value into TLBs.
Mark.
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-10-01 10:34 UTC | newest]
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2020-10-01 9:39 [PATCH] arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD Will Deacon
2020-10-01 9:52 ` Catalin Marinas
2020-10-01 10:32 ` Will Deacon
2020-10-01 10:33 ` Mark Rutland
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