From: Jordan Crouse <jcrouse@codeaurora.org> To: Rob Clark <robdclark@gmail.com> Cc: Jonathan Marek <jonathan@marek.ca>, David Airlie <airlied@linux.ie>, freedreno <freedreno@lists.freedesktop.org>, open list <linux-kernel@vger.kernel.org>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <dri-devel@lists.freedesktop.org>, Daniel Vetter <daniel@ffwll.ch>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <linux-arm-msm@vger.kernel.org>, Sean Paul <sean@poorly.run>, Christoph Hellwig <hch@lst.de> Subject: Re: [Freedreno] [RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance Date: Mon, 16 Nov 2020 10:27:04 -0700 [thread overview] Message-ID: <20201116172703.GD16856@jcrouse1-lnx.qualcomm.com> (raw) In-Reply-To: <CAF6AEGsH5Wk=J+HxHnRqTMLZscjErjKq2v0Rms7Td=W7icZ3sw@mail.gmail.com> On Sat, Nov 14, 2020 at 11:39:45AM -0800, Rob Clark wrote: > On Sat, Nov 14, 2020 at 10:58 AM Jonathan Marek <jonathan@marek.ca> wrote: > > > > On 11/14/20 1:46 PM, Rob Clark wrote: > > > On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig <hch@lst.de> wrote: > > >> > > >> On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote: > > >>> +void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags, > > >>> + size_t range_start, size_t range_end) > > >>> +{ > > >>> + struct msm_gem_object *msm_obj = to_msm_bo(obj); > > >>> + struct device *dev = msm_obj->base.dev->dev; > > >>> + > > >>> + /* exit early if get_pages() hasn't been called yet */ > > >>> + if (!msm_obj->pages) > > >>> + return; > > >>> + > > >>> + /* TODO: sync only the specified range */ > > >>> + > > >>> + if (flags & MSM_GEM_SYNC_FOR_DEVICE) { > > >>> + dma_sync_sg_for_device(dev, msm_obj->sgt->sgl, > > >>> + msm_obj->sgt->nents, DMA_TO_DEVICE); > > >>> + } > > >>> + > > >>> + if (flags & MSM_GEM_SYNC_FOR_CPU) { > > >>> + dma_sync_sg_for_cpu(dev, msm_obj->sgt->sgl, > > >>> + msm_obj->sgt->nents, DMA_FROM_DEVICE); > > >>> + } > > >> > > >> Splitting this helper from the only caller is rather strange, epecially > > >> with the two unused arguments. And I think the way this is specified > > >> to take a range, but ignoring it is actively dangerous. User space will > > >> rely on it syncing everything sooner or later and then you are stuck. > > >> So just define a sync all primitive for now, and if you really need a > > >> range sync and have actually implemented it add a new ioctl for that. > > > > > > We do already have a split of ioctl "layer" which enforces valid ioctl > > > params, etc, and gem (or other) module code which is called by the > > > ioctl func. So I think it is fine to keep this split here. (Also, I > > > think at some point there will be a uring type of ioctl alternative > > > which would re-use the same gem func.) > > > > > > But I do agree that the range should be respected or added later.. > > > drm_ioctl() dispatch is well prepared for extending ioctls. > > > > > > And I assume there should be some validation that the range is aligned > > > to cache-line? Or can we flush a partial cache line? > > > > > > > The range is intended to be "sync at least this range", so that > > userspace doesn't have to worry about details like that. > > > > I don't think userspace can *not* worry about details like that. > Consider a case where the cpu and gpu are simultaneously accessing > different parts of a buffer (for ex, sub-allocation). There needs to > be cache-line separation between the two. There is at least one compute conformance test that I can think of that does exactly this. Jordan > BR, > -R > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: Jordan Crouse <jcrouse@codeaurora.org> To: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <sean@poorly.run>, Jonathan Marek <jonathan@marek.ca>, David Airlie <airlied@linux.ie>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <linux-arm-msm@vger.kernel.org>, open list <linux-kernel@vger.kernel.org>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <dri-devel@lists.freedesktop.org>, freedreno <freedreno@lists.freedesktop.org>, Christoph Hellwig <hch@lst.de> Subject: Re: [Freedreno] [RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance Date: Mon, 16 Nov 2020 10:27:04 -0700 [thread overview] Message-ID: <20201116172703.GD16856@jcrouse1-lnx.qualcomm.com> (raw) In-Reply-To: <CAF6AEGsH5Wk=J+HxHnRqTMLZscjErjKq2v0Rms7Td=W7icZ3sw@mail.gmail.com> On Sat, Nov 14, 2020 at 11:39:45AM -0800, Rob Clark wrote: > On Sat, Nov 14, 2020 at 10:58 AM Jonathan Marek <jonathan@marek.ca> wrote: > > > > On 11/14/20 1:46 PM, Rob Clark wrote: > > > On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig <hch@lst.de> wrote: > > >> > > >> On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote: > > >>> +void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags, > > >>> + size_t range_start, size_t range_end) > > >>> +{ > > >>> + struct msm_gem_object *msm_obj = to_msm_bo(obj); > > >>> + struct device *dev = msm_obj->base.dev->dev; > > >>> + > > >>> + /* exit early if get_pages() hasn't been called yet */ > > >>> + if (!msm_obj->pages) > > >>> + return; > > >>> + > > >>> + /* TODO: sync only the specified range */ > > >>> + > > >>> + if (flags & MSM_GEM_SYNC_FOR_DEVICE) { > > >>> + dma_sync_sg_for_device(dev, msm_obj->sgt->sgl, > > >>> + msm_obj->sgt->nents, DMA_TO_DEVICE); > > >>> + } > > >>> + > > >>> + if (flags & MSM_GEM_SYNC_FOR_CPU) { > > >>> + dma_sync_sg_for_cpu(dev, msm_obj->sgt->sgl, > > >>> + msm_obj->sgt->nents, DMA_FROM_DEVICE); > > >>> + } > > >> > > >> Splitting this helper from the only caller is rather strange, epecially > > >> with the two unused arguments. And I think the way this is specified > > >> to take a range, but ignoring it is actively dangerous. User space will > > >> rely on it syncing everything sooner or later and then you are stuck. > > >> So just define a sync all primitive for now, and if you really need a > > >> range sync and have actually implemented it add a new ioctl for that. > > > > > > We do already have a split of ioctl "layer" which enforces valid ioctl > > > params, etc, and gem (or other) module code which is called by the > > > ioctl func. So I think it is fine to keep this split here. (Also, I > > > think at some point there will be a uring type of ioctl alternative > > > which would re-use the same gem func.) > > > > > > But I do agree that the range should be respected or added later.. > > > drm_ioctl() dispatch is well prepared for extending ioctls. > > > > > > And I assume there should be some validation that the range is aligned > > > to cache-line? Or can we flush a partial cache line? > > > > > > > The range is intended to be "sync at least this range", so that > > userspace doesn't have to worry about details like that. > > > > I don't think userspace can *not* worry about details like that. > Consider a case where the cpu and gpu are simultaneously accessing > different parts of a buffer (for ex, sub-allocation). There needs to > be cache-line separation between the two. There is at least one compute conformance test that I can think of that does exactly this. Jordan > BR, > -R > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-11-16 17:27 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-14 15:17 [RESEND PATCH v2 0/5] drm/msm: support for host-cached BOs Jonathan Marek 2020-11-14 15:17 ` Jonathan Marek 2020-11-14 15:17 ` Jonathan Marek 2020-11-14 15:17 ` [RESEND PATCH v2 1/5] drm/msm: add MSM_BO_CACHED_COHERENT Jonathan Marek 2020-11-14 15:17 ` Jonathan Marek 2020-11-14 15:17 ` [RESEND PATCH v2 2/5] dma-direct: add dma_direct_bypass() to force direct ops Jonathan Marek 2020-11-14 15:17 ` Jonathan Marek 2020-11-14 16:21 ` Christoph Hellwig 2020-11-14 16:21 ` Christoph Hellwig 2020-11-14 15:17 ` [RESEND PATCH v2 3/5] drm/msm: call dma_direct_bypass() Jonathan Marek 2020-11-14 15:17 ` Jonathan Marek 2020-11-14 16:21 ` Christoph Hellwig 2020-11-14 15:17 ` [RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance Jonathan Marek 2020-11-14 15:17 ` Jonathan Marek 2020-11-14 16:24 ` Christoph Hellwig 2020-11-14 18:46 ` Rob Clark 2020-11-14 18:46 ` Rob Clark 2020-11-14 18:54 ` Jonathan Marek 2020-11-14 18:54 ` Jonathan Marek 2020-11-14 19:39 ` Rob Clark 2020-11-14 19:39 ` Rob Clark 2020-11-14 20:07 ` Jonathan Marek 2020-11-14 20:07 ` Jonathan Marek 2020-11-14 20:48 ` Rob Clark 2020-11-14 20:48 ` Rob Clark 2020-11-16 17:33 ` Christoph Hellwig 2020-11-16 17:50 ` Rob Clark 2020-11-16 17:50 ` Rob Clark 2020-11-16 17:52 ` Jonathan Marek 2020-11-16 17:52 ` Jonathan Marek 2020-11-29 18:51 ` Rob Clark 2020-11-29 18:51 ` Rob Clark 2020-11-16 17:27 ` Jordan Crouse [this message] 2020-11-16 17:27 ` [Freedreno] " Jordan Crouse 2020-11-16 17:25 ` Jordan Crouse 2020-11-16 17:25 ` Jordan Crouse 2020-11-14 15:17 ` [RESEND PATCH v2 5/5] drm/msm: bump up the uapi version Jonathan Marek 2020-11-14 15:17 ` Jonathan Marek
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