From: Andre Przywara <andre.przywara@arm.com> To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@siol.net> Cc: "Icenowy Zheng" <icenowy@aosc.xyz>, "Linus Walleij" <linus.walleij@linaro.org>, "Rob Herring" <robh@kernel.org>, "Clément Péron" <peron.clem@gmail.com>, "Shuosheng Huang" <huangshuosheng@allwinnertech.com>, "Yangtao Li" <tiny.windzz@gmail.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, "Michael Turquette" <mturquette@baylibre.com>, "Stephen Boyd" <sboyd@kernel.org>, "Philipp Zabel" <p.zabel@pengutronix.de>, linux-clk@vger.kernel.org Subject: [PATCH v2 06/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU Date: Fri, 11 Dec 2020 01:19:19 +0000 [thread overview] Message-ID: <20201211011934.6171-7-andre.przywara@arm.com> (raw) In-Reply-To: <20201211011934.6171-1-andre.przywara@arm.com> The clocks itself are identical to the H6 R-CCU, it's just that the H616 has not all of them implemented (or connected). Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- drivers/clk/sunxi-ng/Kconfig | 2 +- drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 47 +++++++++++++++++++++++++- drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 3 +- 3 files changed, 49 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index ce5f5847d5d3..feeb8d2074ee 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -33,7 +33,7 @@ config SUN50I_H6_CCU depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST config SUN50I_H6_R_CCU - bool "Support for the Allwinner H6 PRCM CCU" + bool "Support for the Allwinner H6 and H616 PRCM CCU" default ARM64 && ARCH_SUNXI depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c index 50f8d1bc7046..0ca35f383975 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c @@ -136,6 +136,15 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = { &w1_clk.common, }; +static struct ccu_common *sun50i_h616_r_ccu_clks[] = { + &r_apb1_clk.common, + &r_apb2_clk.common, + &r_apb1_twd_clk.common, + &r_apb2_i2c_clk.common, + &r_apb1_ir_clk.common, + &ir_clk.common, +}; + static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { .hws = { [CLK_AR100] = &ar100_clk.common.hw, @@ -152,7 +161,20 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { [CLK_IR] = &ir_clk.common.hw, [CLK_W1] = &w1_clk.common.hw, }, - .num = CLK_NUMBER, + .num = CLK_NUMBER_H6, +}; + +static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = { + .hws = { + [CLK_R_AHB] = &r_ahb_clk.hw, + [CLK_R_APB1] = &r_apb1_clk.common.hw, + [CLK_R_APB2] = &r_apb2_clk.common.hw, + [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw, + [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw, + [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, + }, + .num = CLK_NUMBER_H616, }; static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { @@ -165,6 +187,12 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { [RST_R_APB1_W1] = { 0x1ec, BIT(16) }, }; +static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = { + [RST_R_APB1_TWD] = { 0x12c, BIT(16) }, + [RST_R_APB2_I2C] = { 0x19c, BIT(16) }, + [RST_R_APB1_IR] = { 0x1cc, BIT(16) }, +}; + static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { .ccu_clks = sun50i_h6_r_ccu_clks, .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks), @@ -175,6 +203,16 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets), }; +static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = { + .ccu_clks = sun50i_h616_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks), + + .hw_clks = &sun50i_h616_r_hw_clks, + + .resets = sun50i_h616_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets), +}; + static void __init sunxi_r_ccu_init(struct device_node *node, const struct sunxi_ccu_desc *desc) { @@ -195,3 +233,10 @@ static void __init sun50i_h6_r_ccu_setup(struct device_node *node) } CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu", sun50i_h6_r_ccu_setup); + +static void __init sun50i_h616_r_ccu_setup(struct device_node *node) +{ + sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc); +} +CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu", + sun50i_h616_r_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h index 782117dc0b28..128302696ca1 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h @@ -14,6 +14,7 @@ #define CLK_R_APB2 3 -#define CLK_NUMBER (CLK_W1 + 1) +#define CLK_NUMBER_H6 (CLK_W1 + 1) +#define CLK_NUMBER_H616 (CLK_IR + 1) #endif /* _CCU_SUN50I_H6_R_H */ -- 2.17.5
WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com> To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@siol.net> Cc: "Rob Herring" <robh@kernel.org>, "Yangtao Li" <tiny.windzz@gmail.com>, "Linus Walleij" <linus.walleij@linaro.org>, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, "Stephen Boyd" <sboyd@kernel.org>, linux-sunxi@googlegroups.com, "Clément Péron" <peron.clem@gmail.com>, "Icenowy Zheng" <icenowy@aosc.xyz>, "Philipp Zabel" <p.zabel@pengutronix.de>, "Shuosheng Huang" <huangshuosheng@allwinnertech.com>, "Michael Turquette" <mturquette@baylibre.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 06/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU Date: Fri, 11 Dec 2020 01:19:19 +0000 [thread overview] Message-ID: <20201211011934.6171-7-andre.przywara@arm.com> (raw) In-Reply-To: <20201211011934.6171-1-andre.przywara@arm.com> The clocks itself are identical to the H6 R-CCU, it's just that the H616 has not all of them implemented (or connected). Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- drivers/clk/sunxi-ng/Kconfig | 2 +- drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 47 +++++++++++++++++++++++++- drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 3 +- 3 files changed, 49 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index ce5f5847d5d3..feeb8d2074ee 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -33,7 +33,7 @@ config SUN50I_H6_CCU depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST config SUN50I_H6_R_CCU - bool "Support for the Allwinner H6 PRCM CCU" + bool "Support for the Allwinner H6 and H616 PRCM CCU" default ARM64 && ARCH_SUNXI depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c index 50f8d1bc7046..0ca35f383975 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c @@ -136,6 +136,15 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = { &w1_clk.common, }; +static struct ccu_common *sun50i_h616_r_ccu_clks[] = { + &r_apb1_clk.common, + &r_apb2_clk.common, + &r_apb1_twd_clk.common, + &r_apb2_i2c_clk.common, + &r_apb1_ir_clk.common, + &ir_clk.common, +}; + static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { .hws = { [CLK_AR100] = &ar100_clk.common.hw, @@ -152,7 +161,20 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { [CLK_IR] = &ir_clk.common.hw, [CLK_W1] = &w1_clk.common.hw, }, - .num = CLK_NUMBER, + .num = CLK_NUMBER_H6, +}; + +static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = { + .hws = { + [CLK_R_AHB] = &r_ahb_clk.hw, + [CLK_R_APB1] = &r_apb1_clk.common.hw, + [CLK_R_APB2] = &r_apb2_clk.common.hw, + [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw, + [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw, + [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, + }, + .num = CLK_NUMBER_H616, }; static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { @@ -165,6 +187,12 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { [RST_R_APB1_W1] = { 0x1ec, BIT(16) }, }; +static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = { + [RST_R_APB1_TWD] = { 0x12c, BIT(16) }, + [RST_R_APB2_I2C] = { 0x19c, BIT(16) }, + [RST_R_APB1_IR] = { 0x1cc, BIT(16) }, +}; + static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { .ccu_clks = sun50i_h6_r_ccu_clks, .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks), @@ -175,6 +203,16 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets), }; +static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = { + .ccu_clks = sun50i_h616_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks), + + .hw_clks = &sun50i_h616_r_hw_clks, + + .resets = sun50i_h616_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets), +}; + static void __init sunxi_r_ccu_init(struct device_node *node, const struct sunxi_ccu_desc *desc) { @@ -195,3 +233,10 @@ static void __init sun50i_h6_r_ccu_setup(struct device_node *node) } CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu", sun50i_h6_r_ccu_setup); + +static void __init sun50i_h616_r_ccu_setup(struct device_node *node) +{ + sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc); +} +CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu", + sun50i_h616_r_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h index 782117dc0b28..128302696ca1 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h @@ -14,6 +14,7 @@ #define CLK_R_APB2 3 -#define CLK_NUMBER (CLK_W1 + 1) +#define CLK_NUMBER_H6 (CLK_W1 + 1) +#define CLK_NUMBER_H616 (CLK_IR + 1) #endif /* _CCU_SUN50I_H6_R_H */ -- 2.17.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-12-11 1:24 UTC|newest] Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-11 1:19 [PATCH v2 00/21] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-11 1:19 ` [PATCH v2 01/21] clk: sunxi-ng: h6: Fix clock divider range on some clocks Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-11 1:19 ` [PATCH v2 02/21] dt-bindings: pinctrl: Add Allwinner H616 compatible strings Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-14 9:37 ` Maxime Ripard 2020-12-14 9:37 ` Maxime Ripard 2021-01-14 0:45 ` Andre Przywara 2021-01-14 0:45 ` Andre Przywara 2021-01-14 11:57 ` Maxime Ripard 2021-01-14 11:57 ` Maxime Ripard 2020-12-11 1:19 ` [PATCH v2 03/21] pinctrl: sunxi: Add support for the Allwinner H616 pin controller Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-14 9:44 ` Maxime Ripard 2020-12-14 9:44 ` Maxime Ripard 2020-12-11 1:19 ` [PATCH v2 04/21] pinctrl: sunxi: Add support for the Allwinner H616-R " Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-11 1:19 ` [PATCH v2 05/21] dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-14 22:53 ` Rob Herring 2020-12-14 22:53 ` Rob Herring 2020-12-11 1:19 ` Andre Przywara [this message] 2020-12-11 1:19 ` [PATCH v2 06/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU Andre Przywara 2020-12-11 1:19 ` [PATCH v2 07/21] clk: sunxi-ng: Add support for the Allwinner H616 CCU Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-11 1:19 ` [PATCH v2 08/21] dt-bindings: mmc: sunxi: Add Allwinner A100 and H616 compatibles Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-14 22:54 ` Rob Herring 2020-12-14 22:54 ` Rob Herring 2021-01-11 18:06 ` Ulf Hansson 2021-01-11 18:06 ` Ulf Hansson 2020-12-11 1:19 ` [PATCH v2 09/21] mmc: sunxi: add support for A100 mmc controller Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2021-01-11 18:06 ` Ulf Hansson 2021-01-11 18:06 ` Ulf Hansson 2020-12-11 1:19 ` [PATCH v2 10/21] mfd: axp20x: Allow AXP chips without interrupt lines Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-11 1:19 ` [PATCH v2 11/21] dt-bindings: sram: sunxi-sram: Add H616 compatible string Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-14 22:54 ` Rob Herring 2020-12-14 22:54 ` Rob Herring 2020-12-11 1:19 ` [PATCH v2 12/21] soc: sunxi: sram: Add support for more than one EMAC clock Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-11 1:19 ` [PATCH v2 13/21] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-11 1:19 ` [PATCH v2 14/21] phy: sun4i-usb: Rework "pmu_unk1" handling Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-13 18:24 ` Icenowy Zheng 2020-12-13 18:24 ` Icenowy Zheng 2020-12-14 1:35 ` André Przywara 2020-12-14 1:35 ` André Przywara 2020-12-14 4:45 ` Icenowy Zheng 2020-12-14 4:45 ` Icenowy Zheng 2020-12-11 1:19 ` [PATCH v2 15/21] phy: sun4i-usb: Add support for the H616 USB PHY Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-14 9:52 ` Maxime Ripard 2020-12-14 9:52 ` Maxime Ripard 2020-12-11 1:19 ` [PATCH v2 16/21] dt-bindings: watchdog: sun4i: Add A100 compatible Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-13 16:12 ` Guenter Roeck 2020-12-13 16:12 ` Guenter Roeck 2020-12-11 1:19 ` [PATCH v2 17/21] dt-bindings: watchdog: sun4i: Add H616 compatible string Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-14 22:55 ` Rob Herring 2020-12-14 22:55 ` Rob Herring 2021-01-23 17:29 ` Guenter Roeck 2021-01-23 17:29 ` Guenter Roeck 2020-12-11 1:19 ` [PATCH v2 18/21] dt-bindings: allwinner: Add H616 compatible strings Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-14 22:56 ` Rob Herring 2020-12-14 22:56 ` Rob Herring 2021-01-05 16:29 ` Wolfram Sang 2021-01-05 16:29 ` Wolfram Sang 2020-12-11 1:19 ` [PATCH v2 19/21] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-14 9:58 ` Maxime Ripard 2020-12-14 9:58 ` Maxime Ripard 2020-12-14 12:53 ` Andre Przywara 2020-12-14 12:53 ` Andre Przywara 2020-12-14 13:28 ` [linux-sunxi] " Chen-Yu Tsai 2020-12-14 13:28 ` Chen-Yu Tsai 2020-12-14 14:14 ` Maxime Ripard 2020-12-14 14:14 ` Maxime Ripard 2020-12-14 14:12 ` Maxime Ripard 2020-12-14 14:12 ` Maxime Ripard 2020-12-11 1:19 ` [PATCH v2 20/21] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-14 22:56 ` Rob Herring 2020-12-14 22:56 ` Rob Herring 2020-12-11 1:19 ` [PATCH v2 21/21] arm64: dts: allwinner: Add OrangePi Zero 2 .dts Andre Przywara 2020-12-11 1:19 ` Andre Przywara 2020-12-14 9:59 ` Maxime Ripard 2020-12-14 9:59 ` Maxime Ripard 2020-12-13 17:47 ` [PATCH v2 00/21] arm64: sunxi: Initial Allwinner H616 SoC support Icenowy Zheng 2020-12-13 17:47 ` Icenowy Zheng 2020-12-14 1:18 ` André Przywara 2020-12-14 1:18 ` André Przywara
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