From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, jonathan.zhouwen@huawei.com, Suzuki K Poulose <suzuki.poulose@arm.com>, Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>, Tingwei Zhang <tingwei@codeaurora.org> Subject: [PATCH v5 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore Date: Mon, 14 Dec 2020 17:37:08 +0000 [thread overview] Message-ID: <20201214173731.302520-3-suzuki.poulose@arm.com> (raw) In-Reply-To: <20201214173731.302520-1-suzuki.poulose@arm.com> When the ETM is affected by Qualcomm errata, modifying the TRCPDCR could cause the system hang. Even though this is taken care of during enable/disable ETM, the ETM state save/restore could still access the TRCPDCR. Make sure we skip the access during the save/restore. Found by code inspection. Fixes: 02510a5aa78df45 ("coresight: etm4x: Add support to skip trace unit power up") Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Cc: Tingwei Zhang <tingwei@codeaurora.org> Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index eb56fba1f7c0..20136722011e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1277,7 +1277,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR); - state->trcpdcr = readl(drvdata->base + TRCPDCR); + if (!drvdata->skip_power_up) + state->trcpdcr = readl(drvdata->base + TRCPDCR); /* wait for TRCSTATR.IDLE to go up */ if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { @@ -1295,9 +1296,9 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) * potentially save power on systems that respect the TRCPDCR_PU * despite requesting software to save/restore state. */ - writel_relaxed((state->trcpdcr & ~TRCPDCR_PU), - drvdata->base + TRCPDCR); - + if (!drvdata->skip_power_up) + writel_relaxed((state->trcpdcr & ~TRCPDCR_PU), + drvdata->base + TRCPDCR); out: CS_LOCK(drvdata->base); return ret; @@ -1392,7 +1393,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET); - writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR); + if (!drvdata->skip_power_up) + writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR); drvdata->state_needs_restore = false; -- 2.24.1
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>, mathieu.poirier@linaro.org, Suzuki K Poulose <suzuki.poulose@arm.com>, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, Tingwei Zhang <tingwei@codeaurora.org>, leo.yan@linaro.org, jonathan.zhouwen@huawei.com, mike.leach@linaro.org Subject: [PATCH v5 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore Date: Mon, 14 Dec 2020 17:37:08 +0000 [thread overview] Message-ID: <20201214173731.302520-3-suzuki.poulose@arm.com> (raw) In-Reply-To: <20201214173731.302520-1-suzuki.poulose@arm.com> When the ETM is affected by Qualcomm errata, modifying the TRCPDCR could cause the system hang. Even though this is taken care of during enable/disable ETM, the ETM state save/restore could still access the TRCPDCR. Make sure we skip the access during the save/restore. Found by code inspection. Fixes: 02510a5aa78df45 ("coresight: etm4x: Add support to skip trace unit power up") Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Cc: Tingwei Zhang <tingwei@codeaurora.org> Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index eb56fba1f7c0..20136722011e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1277,7 +1277,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR); - state->trcpdcr = readl(drvdata->base + TRCPDCR); + if (!drvdata->skip_power_up) + state->trcpdcr = readl(drvdata->base + TRCPDCR); /* wait for TRCSTATR.IDLE to go up */ if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { @@ -1295,9 +1296,9 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) * potentially save power on systems that respect the TRCPDCR_PU * despite requesting software to save/restore state. */ - writel_relaxed((state->trcpdcr & ~TRCPDCR_PU), - drvdata->base + TRCPDCR); - + if (!drvdata->skip_power_up) + writel_relaxed((state->trcpdcr & ~TRCPDCR_PU), + drvdata->base + TRCPDCR); out: CS_LOCK(drvdata->base); return ret; @@ -1392,7 +1393,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET); - writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR); + if (!drvdata->skip_power_up) + writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR); drvdata->state_needs_restore = false; -- 2.24.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-12-14 18:23 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-14 17:37 [PATCH v5 00/25] coresight: etm4x: Support for system instructions Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 01/25] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose [this message] 2020-12-14 17:37 ` [PATCH v5 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 03/25] coresight: Introduce device access abstraction Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 04/25] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 05/25] coresight: Convert coresight_timeout to use " Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 06/25] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 07/25] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 08/25] coresight: etm4x: Convert all register accesses Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 09/25] coresight: etm4x: Add commentary on the registers Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 10/25] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 11/25] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 12/25] coresight: etm4x: Check for Software Lock Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 13/25] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 14/25] coresight: etm4x: Clean up " Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 15/25] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 16/25] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 17/25] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 18/25] coresight: etm4x: Expose trcdevarch via trcidr Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-16 18:01 ` Mike Leach 2020-12-16 18:01 ` Mike Leach 2020-12-14 17:37 ` [PATCH v5 19/25] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 20/25] coresight: etm4x: Detect system instructions support Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 21/25] coresight: etm4x: Refactor probing routine Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2021-01-05 21:44 ` Mathieu Poirier 2021-01-05 21:44 ` Mathieu Poirier 2020-12-14 17:37 ` [PATCH v5 22/25] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 23/25] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 24/25] arm64: Add TRFCR_ELx definitions Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2020-12-14 17:37 ` [PATCH v5 25/25] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose 2020-12-14 17:37 ` Suzuki K Poulose 2021-01-06 14:48 ` [PATCH v5 00/25] coresight: etm4x: Support for system instructions Mike Leach 2021-01-06 14:48 ` Mike Leach 2021-01-06 14:52 ` Suzuki K Poulose 2021-01-06 14:52 ` Suzuki K Poulose
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20201214173731.302520-3-suzuki.poulose@arm.com \ --to=suzuki.poulose@arm.com \ --cc=catalin.marinas@arm.com \ --cc=jonathan.zhouwen@huawei.com \ --cc=leo.yan@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mathieu.poirier@linaro.org \ --cc=mike.leach@linaro.org \ --cc=saiprakash.ranjan@codeaurora.org \ --cc=tingwei@codeaurora.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.