From: Amelie Delaunay <amelie.delaunay@foss.st.com> To: Kishon Vijay Abraham I <kishon@ti.com>, Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>, Alexandre Torgue <alexandre.torgue@foss.st.com>, Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-stm32@st-md-mailman.stormreply.com>, Amelie Delaunay <amelie.delaunay@foss.st.com> Subject: [PATCH v2 0/6] STM32 USBPHYC PLL management rework Date: Tue, 5 Jan 2021 10:05:19 +0100 [thread overview] Message-ID: <20210105090525.23164-1-amelie.delaunay@foss.st.com> (raw) STM32 USBPHYC controls the USB PLL. PLL requires to be powered with 1v1 and 1v8 supplies. To ensure a good behavior of the PLL, during boot, runtime and suspend/resume sequences, this series reworks its management to fix regulators issues and improve PLL status reliability. --- Changes in v2: - Move author mail address from @st.com to @foss.st.com - Add Rob's Reviewed-by on bindings patch 1/6 Amelie Delaunay (6): dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation phy: stm32: replace regulator_bulk* by multiple regulator_* phy: stm32: ensure pll is disabled before phys creation phy: stm32: ensure phy are no more active when removing the driver phy: stm32: rework PLL Lock detection .../bindings/phy/phy-stm32-usbphyc.yaml | 22 +- drivers/phy/st/phy-stm32-usbphyc.c | 222 +++++++++++------- 2 files changed, 153 insertions(+), 91 deletions(-) -- 2.17.1
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From: Amelie Delaunay <amelie.delaunay@foss.st.com> To: Kishon Vijay Abraham I <kishon@ti.com>, Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>, Alexandre Torgue <alexandre.torgue@foss.st.com>, Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Amelie Delaunay <amelie.delaunay@foss.st.com>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 0/6] STM32 USBPHYC PLL management rework Date: Tue, 5 Jan 2021 10:05:19 +0100 [thread overview] Message-ID: <20210105090525.23164-1-amelie.delaunay@foss.st.com> (raw) STM32 USBPHYC controls the USB PLL. PLL requires to be powered with 1v1 and 1v8 supplies. To ensure a good behavior of the PLL, during boot, runtime and suspend/resume sequences, this series reworks its management to fix regulators issues and improve PLL status reliability. --- Changes in v2: - Move author mail address from @st.com to @foss.st.com - Add Rob's Reviewed-by on bindings patch 1/6 Amelie Delaunay (6): dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation phy: stm32: replace regulator_bulk* by multiple regulator_* phy: stm32: ensure pll is disabled before phys creation phy: stm32: ensure phy are no more active when removing the driver phy: stm32: rework PLL Lock detection .../bindings/phy/phy-stm32-usbphyc.yaml | 22 +- drivers/phy/st/phy-stm32-usbphyc.c | 222 +++++++++++------- 2 files changed, 153 insertions(+), 91 deletions(-) -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2021-01-05 9:07 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-05 9:05 Amelie Delaunay [this message] 2021-01-05 9:05 ` [PATCH v2 0/6] STM32 USBPHYC PLL management rework Amelie Delaunay 2021-01-05 9:05 ` [PATCH v2 1/6] dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node Amelie Delaunay 2021-01-05 9:05 ` Amelie Delaunay 2021-01-05 9:05 ` [PATCH v2 2/6] phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation Amelie Delaunay 2021-01-05 9:05 ` Amelie Delaunay 2021-01-05 9:05 ` [PATCH v2 3/6] phy: stm32: replace regulator_bulk* by multiple regulator_* Amelie Delaunay 2021-01-05 9:05 ` Amelie Delaunay 2021-01-05 9:05 ` [PATCH v2 4/6] phy: stm32: ensure pll is disabled before phys creation Amelie Delaunay 2021-01-05 9:05 ` Amelie Delaunay 2021-01-05 9:05 ` [PATCH v2 5/6] phy: stm32: ensure phy are no more active when removing the driver Amelie Delaunay 2021-01-05 9:05 ` Amelie Delaunay 2021-01-05 9:05 ` [PATCH v2 6/6] phy: stm32: rework PLL Lock detection Amelie Delaunay 2021-01-05 9:05 ` Amelie Delaunay 2021-01-13 15:10 ` [PATCH v2 0/6] STM32 USBPHYC PLL management rework Vinod Koul 2021-01-13 15:10 ` Vinod Koul
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