From: Imre Deak <imre.deak@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Lyude Paul <lyude@redhat.com>, Ville Syrjala <ville.syrjala@intel.com>, stable@vger.kernel.org Subject: [PATCH 2/2] drm/i915: Fix the MST PBN divider calculation Date: Mon, 25 Jan 2021 19:36:36 +0200 [thread overview] Message-ID: <20210125173636.1733812-2-imre.deak@intel.com> (raw) In-Reply-To: <20210125173636.1733812-1-imre.deak@intel.com> Atm the driver will calculate a wrong MST timeslots/MTP (aka time unit) value for MST streams if the link parameters (link rate or lane count) are limited in a way independent of the sink capabilities (reported by DPCD). One example of such a limitation is when a MUX between the sink and source connects only a limited number of lanes to the display and connects the rest of the lanes to other peripherals (USB). Another issue is that atm MST core calculates the divider based on the backwards compatible DPCD (at address 0x0000) vs. the extended capability info (at address 0x2200). This can result in leaving some part of the MST BW unused (For instance in case of the WD19TB dock). Fix the above two issues by calculating the PBN divider value based on the rate and lane count link parameters that the driver uses for all other computation. Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/2977 Cc: Lyude Paul <lyude@redhat.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d6a1b961a0e8..b4621ed0127e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -68,7 +68,9 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, connector->port, - crtc_state->pbn, 0); + crtc_state->pbn, + drm_dp_get_vc_payload_bw(crtc_state->port_clock, + crtc_state->lane_count)); if (slots == -EDEADLK) return slots; if (slots >= 0) -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Imre Deak <imre.deak@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Ville Syrjala <ville.syrjala@intel.com>, stable@vger.kernel.org Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Fix the MST PBN divider calculation Date: Mon, 25 Jan 2021 19:36:36 +0200 [thread overview] Message-ID: <20210125173636.1733812-2-imre.deak@intel.com> (raw) In-Reply-To: <20210125173636.1733812-1-imre.deak@intel.com> Atm the driver will calculate a wrong MST timeslots/MTP (aka time unit) value for MST streams if the link parameters (link rate or lane count) are limited in a way independent of the sink capabilities (reported by DPCD). One example of such a limitation is when a MUX between the sink and source connects only a limited number of lanes to the display and connects the rest of the lanes to other peripherals (USB). Another issue is that atm MST core calculates the divider based on the backwards compatible DPCD (at address 0x0000) vs. the extended capability info (at address 0x2200). This can result in leaving some part of the MST BW unused (For instance in case of the WD19TB dock). Fix the above two issues by calculating the PBN divider value based on the rate and lane count link parameters that the driver uses for all other computation. Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/2977 Cc: Lyude Paul <lyude@redhat.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d6a1b961a0e8..b4621ed0127e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -68,7 +68,9 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, connector->port, - crtc_state->pbn, 0); + crtc_state->pbn, + drm_dp_get_vc_payload_bw(crtc_state->port_clock, + crtc_state->lane_count)); if (slots == -EDEADLK) return slots; if (slots >= 0) -- 2.25.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-01-25 17:38 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-25 17:36 [PATCH 1/2] drm/dp/mst: Export drm_dp_get_vc_payload_bw() Imre Deak 2021-01-25 17:36 ` [Intel-gfx] " Imre Deak 2021-01-25 17:36 ` Imre Deak 2021-01-25 17:36 ` Imre Deak [this message] 2021-01-25 17:36 ` [Intel-gfx] [PATCH 2/2] drm/i915: Fix the MST PBN divider calculation Imre Deak 2021-01-25 19:24 ` Lyude Paul 2021-01-25 19:24 ` [Intel-gfx] " Lyude Paul 2021-01-25 21:04 ` Imre Deak 2021-01-25 21:04 ` [Intel-gfx] " Imre Deak 2021-01-25 22:55 ` Lyude Paul 2021-01-25 22:55 ` [Intel-gfx] " Lyude Paul 2021-01-26 12:06 ` Imre Deak 2021-01-26 12:06 ` [Intel-gfx] " Imre Deak 2021-01-28 13:54 ` Ville Syrjälä 2021-01-28 13:54 ` Ville Syrjälä 2021-01-25 19:22 ` [PATCH 1/2] drm/dp/mst: Export drm_dp_get_vc_payload_bw() Lyude Paul 2021-01-25 19:22 ` [Intel-gfx] " Lyude Paul 2021-01-25 19:22 ` Lyude Paul 2021-01-25 19:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] " Patchwork 2021-01-25 19:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-01-25 19:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-01-26 1:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-01-28 19:38 ` Imre Deak 2021-01-28 19:38 ` [Intel-gfx] " Imre Deak
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