From: Jonathan Cameron <Jonathan.Cameron@Huawei.com> To: Ben Widawsky <ben.widawsky@intel.com> Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, "Chris Browy" <cbrowy@avery-design.com>, "Dan Williams" <dan.j.williams@intel.com>, "David Hildenbrand" <david@redhat.com>, "Igor Mammedov" <imammedo@redhat.com>, "Ira Weiny" <ira.weiny@intel.com>, "Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>, "Markus Armbruster" <armbru@redhat.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, "Vishal Verma" <vishal.l.verma@intel.com>, "John Groves (jgroves)" <jgroves@micron.com>, "Michael S. Tsirkin" <mst@redhat.com> Subject: Re: [RFC PATCH v3 04/31] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Date: Tue, 2 Feb 2021 12:23:50 +0000 [thread overview] Message-ID: <20210202122350.000047f3@Huawei.com> (raw) In-Reply-To: <20210202005948.241655-5-ben.widawsky@intel.com> On Mon, 1 Feb 2021 16:59:21 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > This implements all device MMIO up to the first capability. That > includes the CXL Device Capabilities Array Register, as well as all of > the CXL Device Capability Header Registers. The latter are filled in as > they are implemented in the following patches. > > Endianness and alignment are managed by softmmu memory core. > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> A few trivials > --- > hw/cxl/cxl-device-utils.c | 105 ++++++++++++++++++++++++++++++++++++ > hw/cxl/meson.build | 1 + > include/hw/cxl/cxl_device.h | 27 +++++++++- > 3 files changed, 132 insertions(+), 1 deletion(-) > create mode 100644 hw/cxl/cxl-device-utils.c > > diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c > new file mode 100644 > index 0000000000..bb15ad9a0f > --- /dev/null > +++ b/hw/cxl/cxl-device-utils.c > @@ -0,0 +1,105 @@ > +/* > + * CXL Utility library for devices > + * > + * Copyright(C) 2020 Intel Corporation. > + * > + * This work is licensed under the terms of the GNU GPL, version 2. See the > + * COPYING file in the top-level directory. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "hw/cxl/cxl.h" > + > +/* > + * Device registers have no restrictions per the spec, and so fall back to the > + * default memory mapped register rules in 8.2: > + * Software shall use CXL.io Memory Read and Write to access memory mapped > + * register defined in this section. Unless otherwise specified, software > + * shall restrict the accesses width based on the following: > + * • A 32 bit register shall be accessed as a 1 Byte, 2 Bytes or 4 Bytes odd spacing > + * quantity. > + * • A 64 bit register shall be accessed as a 1 Byte, 2 Bytes, 4 Bytes or 8 > + * Bytes > + * • The address shall be a multiple of the access width, e.g. when > + * accessing a register as a 4 Byte quantity, the address shall be > + * multiple of 4. > + * • The accesses shall map to contiguous bytes.If these rules are not > + * followed, the behavior is undefined > + */ > + > +static uint64_t caps_reg_read(void *opaque, hwaddr offset, unsigned size) > +{ > + CXLDeviceState *cxl_dstate = opaque; > + > + return cxl_dstate->caps_reg_state32[offset / 4]; > +} > + > +static uint64_t dev_reg_read(void *opaque, hwaddr offset, unsigned size) > +{ > + return 0; > +} > + > +static const MemoryRegionOps dev_ops = { > + .read = dev_reg_read, > + .write = NULL, /* status register is read only */ > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 1, > + .max_access_size = 8, > + .unaligned = false, > + }, > + .impl = { > + .min_access_size = 1, > + .max_access_size = 8, > + }, > +}; > + > +static const MemoryRegionOps caps_ops = { > + .read = caps_reg_read, > + .write = NULL, /* caps registers are read only */ > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 1, > + .max_access_size = 8, > + .unaligned = false, > + }, > + .impl = { > + .min_access_size = 4, > + .max_access_size = 4, > + }, > +}; > + > +void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstate) > +{ > + /* This will be a BAR, so needs to be rounded up to pow2 for PCI spec */ > + memory_region_init(&cxl_dstate->device_registers, obj, "device-registers", > + pow2ceil(CXL_MMIO_SIZE)); > + > + memory_region_init_io(&cxl_dstate->caps, obj, &caps_ops, cxl_dstate, > + "cap-array", CXL_DEVICE_REGISTERS_OFFSET - 0); Specifying a size in terms of the offset of another region isn't exactly intuitive so perhaps a comment on why or better yet actually use a size parameter covering what is there rather than simply the region below the CXL_DEVICE_REGISTERS_OFFSET. > + memory_region_init_io(&cxl_dstate->device, obj, &dev_ops, cxl_dstate, > + "device-status", CXL_DEVICE_REGISTERS_LENGTH); > + > + memory_region_add_subregion(&cxl_dstate->device_registers, 0, > + &cxl_dstate->caps); > + memory_region_add_subregion(&cxl_dstate->device_registers, > + CXL_DEVICE_REGISTERS_OFFSET, > + &cxl_dstate->device); > +} > + > +static void device_reg_init_common(CXLDeviceState *cxl_dstate) { } > + > +void cxl_device_register_init_common(CXLDeviceState *cxl_dstate) > +{ > + uint32_t *cap_hdrs = cxl_dstate->caps_reg_state32; > + const int cap_count = 1; > + > + /* CXL Device Capabilities Array Register */ > + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0); > + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1); > + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY2, CAP_COUNT, cap_count); > + > + cxl_device_cap_init(cxl_dstate, DEVICE, 1); > + device_reg_init_common(cxl_dstate); > +} > diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build > index 00c3876a0f..47154d6850 100644 > --- a/hw/cxl/meson.build > +++ b/hw/cxl/meson.build > @@ -1,3 +1,4 @@ > softmmu_ss.add(when: 'CONFIG_CXL', if_true: files( > 'cxl-component-utils.c', > + 'cxl-device-utils.c', > )) > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h > index a85f250503..f3bcf19410 100644 > --- a/include/hw/cxl/cxl_device.h > +++ b/include/hw/cxl/cxl_device.h > @@ -58,6 +58,8 @@ > #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */ > #define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */ > #define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */ > +#define CXL_CAPS_SIZE \ > + (CXL_DEVICE_CAP_REG_SIZE * CXL_DEVICE_CAPS_MAX + 1) /* +1 for header */ > > #define CXL_DEVICE_REGISTERS_OFFSET 0x80 /* Read comment above */ > #define CXL_DEVICE_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */ > @@ -70,11 +72,18 @@ > #define CXL_MAILBOX_REGISTERS_LENGTH \ > (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) > > +#define CXL_MMIO_SIZE \ > + CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_REGISTERS_LENGTH + \ > + CXL_MAILBOX_REGISTERS_LENGTH > + > typedef struct cxl_device_state { > MemoryRegion device_registers; > > /* mmio for device capabilities array - 8.2.8.2 */ > - MemoryRegion caps; > + struct { > + MemoryRegion caps; > + uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4]; > + }; With this unnamed,w hat is the benefit of having these two in a struct? The naming makes it clear they are related anyway. > > /* mmio for the device status registers 8.2.8.3 */ > MemoryRegion device; > @@ -126,6 +135,22 @@ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVICE_CAP_HDR1_OFFSET) > CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \ > CXL_DEVICE_CAP_REG_SIZE) > > +#define cxl_device_cap_init(dstate, reg, cap_id) \ > + do { \ > + uint32_t *cap_hdrs = dstate->caps_reg_state32; \ > + int which = R_CXL_DEV_##reg##_CAP_HDR0; \ > + cap_hdrs[which] = \ > + FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_ID, cap_id); \ > + cap_hdrs[which] = FIELD_DP32( \ > + cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, 1); \ > + cap_hdrs[which + 1] = \ > + FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, \ > + CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); \ > + cap_hdrs[which + 2] = \ > + FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, \ > + CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); \ > + } while (0) > + > REG32(CXL_DEV_MAILBOX_CAP, 0) > FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) > FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1)
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron <Jonathan.Cameron@Huawei.com> To: Ben Widawsky <ben.widawsky@intel.com> Cc: "David Hildenbrand" <david@redhat.com>, "Vishal Verma" <vishal.l.verma@intel.com>, "John Groves (jgroves)" <jgroves@micron.com>, "Chris Browy" <cbrowy@avery-design.com>, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, "Markus Armbruster" <armbru@redhat.com>, "Michael S. Tsirkin" <mst@redhat.com>, "Igor Mammedov" <imammedo@redhat.com>, "Dan Williams" <dan.j.williams@intel.com>, "Ira Weiny" <ira.weiny@intel.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org> Subject: Re: [RFC PATCH v3 04/31] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Date: Tue, 2 Feb 2021 12:23:50 +0000 [thread overview] Message-ID: <20210202122350.000047f3@Huawei.com> (raw) In-Reply-To: <20210202005948.241655-5-ben.widawsky@intel.com> On Mon, 1 Feb 2021 16:59:21 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > This implements all device MMIO up to the first capability. That > includes the CXL Device Capabilities Array Register, as well as all of > the CXL Device Capability Header Registers. The latter are filled in as > they are implemented in the following patches. > > Endianness and alignment are managed by softmmu memory core. > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> A few trivials > --- > hw/cxl/cxl-device-utils.c | 105 ++++++++++++++++++++++++++++++++++++ > hw/cxl/meson.build | 1 + > include/hw/cxl/cxl_device.h | 27 +++++++++- > 3 files changed, 132 insertions(+), 1 deletion(-) > create mode 100644 hw/cxl/cxl-device-utils.c > > diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c > new file mode 100644 > index 0000000000..bb15ad9a0f > --- /dev/null > +++ b/hw/cxl/cxl-device-utils.c > @@ -0,0 +1,105 @@ > +/* > + * CXL Utility library for devices > + * > + * Copyright(C) 2020 Intel Corporation. > + * > + * This work is licensed under the terms of the GNU GPL, version 2. See the > + * COPYING file in the top-level directory. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "hw/cxl/cxl.h" > + > +/* > + * Device registers have no restrictions per the spec, and so fall back to the > + * default memory mapped register rules in 8.2: > + * Software shall use CXL.io Memory Read and Write to access memory mapped > + * register defined in this section. Unless otherwise specified, software > + * shall restrict the accesses width based on the following: > + * • A 32 bit register shall be accessed as a 1 Byte, 2 Bytes or 4 Bytes odd spacing > + * quantity. > + * • A 64 bit register shall be accessed as a 1 Byte, 2 Bytes, 4 Bytes or 8 > + * Bytes > + * • The address shall be a multiple of the access width, e.g. when > + * accessing a register as a 4 Byte quantity, the address shall be > + * multiple of 4. > + * • The accesses shall map to contiguous bytes.If these rules are not > + * followed, the behavior is undefined > + */ > + > +static uint64_t caps_reg_read(void *opaque, hwaddr offset, unsigned size) > +{ > + CXLDeviceState *cxl_dstate = opaque; > + > + return cxl_dstate->caps_reg_state32[offset / 4]; > +} > + > +static uint64_t dev_reg_read(void *opaque, hwaddr offset, unsigned size) > +{ > + return 0; > +} > + > +static const MemoryRegionOps dev_ops = { > + .read = dev_reg_read, > + .write = NULL, /* status register is read only */ > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 1, > + .max_access_size = 8, > + .unaligned = false, > + }, > + .impl = { > + .min_access_size = 1, > + .max_access_size = 8, > + }, > +}; > + > +static const MemoryRegionOps caps_ops = { > + .read = caps_reg_read, > + .write = NULL, /* caps registers are read only */ > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 1, > + .max_access_size = 8, > + .unaligned = false, > + }, > + .impl = { > + .min_access_size = 4, > + .max_access_size = 4, > + }, > +}; > + > +void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstate) > +{ > + /* This will be a BAR, so needs to be rounded up to pow2 for PCI spec */ > + memory_region_init(&cxl_dstate->device_registers, obj, "device-registers", > + pow2ceil(CXL_MMIO_SIZE)); > + > + memory_region_init_io(&cxl_dstate->caps, obj, &caps_ops, cxl_dstate, > + "cap-array", CXL_DEVICE_REGISTERS_OFFSET - 0); Specifying a size in terms of the offset of another region isn't exactly intuitive so perhaps a comment on why or better yet actually use a size parameter covering what is there rather than simply the region below the CXL_DEVICE_REGISTERS_OFFSET. > + memory_region_init_io(&cxl_dstate->device, obj, &dev_ops, cxl_dstate, > + "device-status", CXL_DEVICE_REGISTERS_LENGTH); > + > + memory_region_add_subregion(&cxl_dstate->device_registers, 0, > + &cxl_dstate->caps); > + memory_region_add_subregion(&cxl_dstate->device_registers, > + CXL_DEVICE_REGISTERS_OFFSET, > + &cxl_dstate->device); > +} > + > +static void device_reg_init_common(CXLDeviceState *cxl_dstate) { } > + > +void cxl_device_register_init_common(CXLDeviceState *cxl_dstate) > +{ > + uint32_t *cap_hdrs = cxl_dstate->caps_reg_state32; > + const int cap_count = 1; > + > + /* CXL Device Capabilities Array Register */ > + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0); > + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1); > + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY2, CAP_COUNT, cap_count); > + > + cxl_device_cap_init(cxl_dstate, DEVICE, 1); > + device_reg_init_common(cxl_dstate); > +} > diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build > index 00c3876a0f..47154d6850 100644 > --- a/hw/cxl/meson.build > +++ b/hw/cxl/meson.build > @@ -1,3 +1,4 @@ > softmmu_ss.add(when: 'CONFIG_CXL', if_true: files( > 'cxl-component-utils.c', > + 'cxl-device-utils.c', > )) > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h > index a85f250503..f3bcf19410 100644 > --- a/include/hw/cxl/cxl_device.h > +++ b/include/hw/cxl/cxl_device.h > @@ -58,6 +58,8 @@ > #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */ > #define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */ > #define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */ > +#define CXL_CAPS_SIZE \ > + (CXL_DEVICE_CAP_REG_SIZE * CXL_DEVICE_CAPS_MAX + 1) /* +1 for header */ > > #define CXL_DEVICE_REGISTERS_OFFSET 0x80 /* Read comment above */ > #define CXL_DEVICE_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */ > @@ -70,11 +72,18 @@ > #define CXL_MAILBOX_REGISTERS_LENGTH \ > (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) > > +#define CXL_MMIO_SIZE \ > + CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_REGISTERS_LENGTH + \ > + CXL_MAILBOX_REGISTERS_LENGTH > + > typedef struct cxl_device_state { > MemoryRegion device_registers; > > /* mmio for device capabilities array - 8.2.8.2 */ > - MemoryRegion caps; > + struct { > + MemoryRegion caps; > + uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4]; > + }; With this unnamed,w hat is the benefit of having these two in a struct? The naming makes it clear they are related anyway. > > /* mmio for the device status registers 8.2.8.3 */ > MemoryRegion device; > @@ -126,6 +135,22 @@ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVICE_CAP_HDR1_OFFSET) > CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \ > CXL_DEVICE_CAP_REG_SIZE) > > +#define cxl_device_cap_init(dstate, reg, cap_id) \ > + do { \ > + uint32_t *cap_hdrs = dstate->caps_reg_state32; \ > + int which = R_CXL_DEV_##reg##_CAP_HDR0; \ > + cap_hdrs[which] = \ > + FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_ID, cap_id); \ > + cap_hdrs[which] = FIELD_DP32( \ > + cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, 1); \ > + cap_hdrs[which + 1] = \ > + FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, \ > + CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); \ > + cap_hdrs[which + 2] = \ > + FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, \ > + CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); \ > + } while (0) > + > REG32(CXL_DEV_MAILBOX_CAP, 0) > FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) > FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1)
next prev parent reply other threads:[~2021-02-02 12:25 UTC|newest] Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-02 0:59 [RFC PATCH v3 00/31] CXL 2.0 Support Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 01/31] hw/pci/cxl: Add a CXL component type (interface) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 02/31] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 11:48 ` Jonathan Cameron 2021-02-02 11:48 ` Jonathan Cameron 2021-02-17 18:36 ` Ben Widawsky 2021-02-11 17:08 ` Jonathan Cameron 2021-02-11 17:08 ` Jonathan Cameron 2021-02-17 16:40 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 03/31] hw/cxl/device: Introduce a CXL device (8.2.8) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 12:03 ` Jonathan Cameron 2021-02-02 12:03 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 04/31] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 12:23 ` Jonathan Cameron [this message] 2021-02-02 12:23 ` Jonathan Cameron 2021-02-17 22:15 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 05/31] hw/cxl/device: Implement basic mailbox (8.2.8.4) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 14:58 ` Jonathan Cameron 2021-02-02 14:58 ` Jonathan Cameron 2021-02-11 17:46 ` Jonathan Cameron 2021-02-18 0:55 ` Ben Widawsky 2021-02-18 16:50 ` Jonathan Cameron 2021-02-11 18:09 ` Jonathan Cameron 2021-02-11 18:09 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 06/31] hw/cxl/device: Add memory device utilities Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 07/31] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 13:44 ` Jonathan Cameron 2021-02-02 13:44 ` Jonathan Cameron 2021-02-11 17:59 ` Jonathan Cameron 2021-02-11 17:59 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 08/31] hw/cxl/device: Timestamp implementation (8.2.9.3) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 09/31] hw/cxl/device: Add log commands (8.2.9.4) + CEL Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 10/31] hw/pxb: Use a type for realizing expanders Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 13:50 ` Jonathan Cameron 2021-02-02 13:50 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 11/31] hw/pci/cxl: Create a CXL bus type Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 12/31] hw/pxb: Allow creation of a CXL PXB (host bridge) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 13/31] qtest: allow DSDT acpi table changes Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 14/31] acpi/pci: Consolidate host bridge setup Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 13:56 ` Jonathan Cameron 2021-02-02 13:56 ` Jonathan Cameron 2021-12-02 10:32 ` Jonathan Cameron 2021-12-02 10:32 ` Jonathan Cameron via 2021-02-02 0:59 ` [RFC PATCH v3 15/31] tests/acpi: remove stale allowed tables Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 16/31] hw/pci: Plumb _UID through host bridges Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 15:00 ` Jonathan Cameron 2021-02-02 15:00 ` Jonathan Cameron 2021-02-02 15:24 ` Michael S. Tsirkin 2021-02-02 15:24 ` Michael S. Tsirkin 2021-02-02 15:42 ` Ben Widawsky 2021-02-02 15:42 ` Ben Widawsky 2021-02-02 15:51 ` Michael S. Tsirkin 2021-02-02 15:51 ` Michael S. Tsirkin 2021-02-02 16:20 ` Ben Widawsky 2021-02-02 16:20 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 17/31] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 19:21 ` Jonathan Cameron 2021-02-02 19:21 ` Jonathan Cameron 2021-02-02 19:45 ` Ben Widawsky 2021-02-02 20:43 ` Jonathan Cameron 2021-02-02 21:03 ` Ben Widawsky 2021-02-02 22:06 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 18/31] acpi/pxb/cxl: Reserve host bridge MMIO Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 19/31] hw/pxb/cxl: Add "windows" for host bridges Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 20/31] hw/cxl/rp: Add a root port Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 21/31] hw/cxl/device: Add a memory device (8.2.8.5) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 14:26 ` Eric Blake 2021-02-02 15:06 ` Ben Widawsky 2021-02-02 15:06 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 22/31] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 23/31] acpi/cxl: Add _OSC implementation (9.14.2) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 24/31] tests/acpi: allow CEDT table addition Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 25/31] acpi/cxl: Create the CEDT (9.14.1) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 26/31] tests/acpi: Add new CEDT files Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 27/31] hw/cxl/device: Add some trivial commands Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 28/31] hw/cxl/device: Plumb real LSA sizing Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 29/31] hw/cxl/device: Implement get/set LSA Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 30/31] qtest/cxl: Add very basic sanity tests Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 31/31] WIP: i386/cxl: Initialize a host bridge Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 1:33 ` [RFC PATCH v3 00/31] CXL 2.0 Support no-reply 2021-02-02 1:33 ` no-reply 2021-02-03 17:42 ` Ben Widawsky 2021-02-11 18:51 ` Jonathan Cameron 2021-02-11 18:51 ` Jonathan Cameron 2021-03-11 23:27 ` [RFC PATCH] hw/mem/cxl_type3: Go back to subregions Ben Widawsky
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