* [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-12 18:50 ` Lyude Paul
0 siblings, 0 replies; 19+ messages in thread
From: Lyude Paul @ 2021-02-12 18:50 UTC (permalink / raw)
To: intel-gfx
Cc: Tejas Upadhyay, Matt Roper, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, David Airlie, Daniel Vetter, open list:DRM DRIVERS,
open list
From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
For Legacy S3 suspend/resume GEN9 BC needs to enable and
setup TGP PCH.
v2:
* Move Wa_14010685332 into it's own function - vsyrjala
* Add TODO comment about figuring out if we can move this workaround - imre
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
1 file changed, 36 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98145a7f28a4..7d912aa950ee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
+static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ /*
+ * Wa_14010685332:cnp/cmp,tgp,adp
+ * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
+ * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
+ */
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
+}
+
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
GEN3_IRQ_RESET(uncore, GEN8_PCU_);
- if (HAS_PCH_SPLIT(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ GEN3_IRQ_RESET(uncore, SDE);
+ else if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev_priv);
+
+ if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1))
+ cnp_irq_post_reset(dev_priv);
}
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
- /* Wa_14010685332:cnp/cmp,tgp,adp */
if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
- (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
- INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, 0);
- }
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1))
+ cnp_irq_post_reset(dev_priv);
}
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
@@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
spt_hpd_detection_setup(dev_priv);
+
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_hpd_irq_setup(dev_priv);
}
static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
@@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
}
}
+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ u32 mask = SDE_GMBUS_ICP;
+
+ GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
+}
+
static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_irq_postinstall(dev_priv);
+ else if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev_priv);
gen8_gt_irq_postinstall(&dev_priv->gt);
@@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
gen8_master_intr_enable(dev_priv->uncore.regs);
}
-static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- u32 mask = SDE_GMBUS_ICP;
-
- GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
-}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
--
2.29.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-12 18:50 ` Lyude Paul
0 siblings, 0 replies; 19+ messages in thread
From: Lyude Paul @ 2021-02-12 18:50 UTC (permalink / raw)
To: intel-gfx
Cc: David Airlie, open list, open list:DRM DRIVERS, Rodrigo Vivi,
Tejas Upadhyay
From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
For Legacy S3 suspend/resume GEN9 BC needs to enable and
setup TGP PCH.
v2:
* Move Wa_14010685332 into it's own function - vsyrjala
* Add TODO comment about figuring out if we can move this workaround - imre
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
1 file changed, 36 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98145a7f28a4..7d912aa950ee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
+static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ /*
+ * Wa_14010685332:cnp/cmp,tgp,adp
+ * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
+ * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
+ */
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
+}
+
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
GEN3_IRQ_RESET(uncore, GEN8_PCU_);
- if (HAS_PCH_SPLIT(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ GEN3_IRQ_RESET(uncore, SDE);
+ else if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev_priv);
+
+ if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1))
+ cnp_irq_post_reset(dev_priv);
}
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
- /* Wa_14010685332:cnp/cmp,tgp,adp */
if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
- (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
- INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, 0);
- }
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1))
+ cnp_irq_post_reset(dev_priv);
}
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
@@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
spt_hpd_detection_setup(dev_priv);
+
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_hpd_irq_setup(dev_priv);
}
static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
@@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
}
}
+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ u32 mask = SDE_GMBUS_ICP;
+
+ GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
+}
+
static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_irq_postinstall(dev_priv);
+ else if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev_priv);
gen8_gt_irq_postinstall(&dev_priv->gt);
@@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
gen8_master_intr_enable(dev_priv->uncore.regs);
}
-static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- u32 mask = SDE_GMBUS_ICP;
-
- GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
-}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
--
2.29.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-12 18:50 ` Lyude Paul
0 siblings, 0 replies; 19+ messages in thread
From: Lyude Paul @ 2021-02-12 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: David Airlie, open list, open list:DRM DRIVERS
From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
For Legacy S3 suspend/resume GEN9 BC needs to enable and
setup TGP PCH.
v2:
* Move Wa_14010685332 into it's own function - vsyrjala
* Add TODO comment about figuring out if we can move this workaround - imre
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
1 file changed, 36 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98145a7f28a4..7d912aa950ee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
+static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ /*
+ * Wa_14010685332:cnp/cmp,tgp,adp
+ * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
+ * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
+ */
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
+}
+
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
GEN3_IRQ_RESET(uncore, GEN8_PCU_);
- if (HAS_PCH_SPLIT(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ GEN3_IRQ_RESET(uncore, SDE);
+ else if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev_priv);
+
+ if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1))
+ cnp_irq_post_reset(dev_priv);
}
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
- /* Wa_14010685332:cnp/cmp,tgp,adp */
if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
- (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
- INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, 0);
- }
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1))
+ cnp_irq_post_reset(dev_priv);
}
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
@@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
spt_hpd_detection_setup(dev_priv);
+
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_hpd_irq_setup(dev_priv);
}
static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
@@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
}
}
+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ u32 mask = SDE_GMBUS_ICP;
+
+ GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
+}
+
static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_irq_postinstall(dev_priv);
+ else if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev_priv);
gen8_gt_irq_postinstall(&dev_priv->gt);
@@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
gen8_master_intr_enable(dev_priv->uncore.regs);
}
-static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- u32 mask = SDE_GMBUS_ICP;
-
- GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
-}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev2)
2021-02-12 18:50 ` Lyude Paul
(?)
(?)
@ 2021-02-12 19:32 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2021-02-12 19:32 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3223 bytes --]
== Series Details ==
Series: drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev2)
URL : https://patchwork.freedesktop.org/series/86346/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9771 -> Patchwork_19673
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/index.html
Known issues
------------
Here are the changes found in Patchwork_19673 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-tgl-y: NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/fi-tgl-y/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_basic@userptr:
- fi-byt-j1900: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/fi-byt-j1900/igt@amdgpu/amd_basic@userptr.html
* igt@gem_render_tiled_blits@basic:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
#### Possible fixes ####
* igt@gem_linear_blits@basic:
- fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/fi-tgl-y/igt@gem_linear_blits@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/fi-tgl-y/igt@gem_linear_blits@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [INCOMPLETE][7] ([i915#142] / [i915#2405]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (45 -> 39)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-ehl-2 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9771 -> Patchwork_19673
CI-20190529: 20190529
CI_DRM_9771: 1b095889c6780e40f6161bfb824b5e944fd69547 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6003: 627cc5353535d61fa33c5f7ff7e64f154c84f10a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19673: 1ffa579a6e3408e1a4033b88eb5ab0a4186f82a5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1ffa579a6e34 drm/i915/gen9bc: Handle TGP PCH during suspend/resume
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/index.html
[-- Attachment #1.2: Type: text/html, Size: 4005 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev2)
2021-02-12 18:50 ` Lyude Paul
` (2 preceding siblings ...)
(?)
@ 2021-02-12 21:04 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2021-02-12 21:04 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30283 bytes --]
== Series Details ==
Series: drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev2)
URL : https://patchwork.freedesktop.org/series/86346/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9771_full -> Patchwork_19673_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19673_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19673_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19673_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_sequence@queue-busy:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl4/igt@kms_sequence@queue-busy.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl10/igt@kms_sequence@queue-busy.html
Known issues
------------
Here are the changes found in Patchwork_19673_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-glk9/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-iclb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-kbl2/igt@gem_exec_fair@basic-pace@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_params@secure-non-master:
- shard-tglb: NOTRUN -> [SKIP][13] ([fdo#112283])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb6/igt@gem_exec_params@secure-non-master.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl6/igt@gem_softpin@noreloc-s3.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl2/igt@gem_softpin@noreloc-s3.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-apl: NOTRUN -> [DMESG-WARN][16] ([i915#180])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl7/igt@gem_workarounds@suspend-resume-fd.html
* igt@gen9_exec_parse@secure-batches:
- shard-tglb: NOTRUN -> [SKIP][17] ([fdo#112306])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb6/igt@gen9_exec_parse@secure-batches.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271]) +65 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl1/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][19] -> [FAIL][20] ([i915#2597])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-tglb5/igt@kms_async_flips@test-time-stamp.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb7/igt@kms_async_flips@test-time-stamp.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#111615])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb6/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180:
- shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111304])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl1/igt@kms_ccs@pipe-c-crc-primary-rotation-180.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111827]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl3/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-tglb: NOTRUN -> [SKIP][24] ([fdo#109284] / [fdo#111827])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb6/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-c-ctm-max:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +6 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl7/igt@kms_color_chamelium@pipe-c-ctm-max.html
* igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +6 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl5/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][27] ([i915#1319])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl3/igt@kms_content_protection@legacy.html
- shard-tglb: NOTRUN -> [SKIP][28] ([fdo#111828])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb6/igt@kms_content_protection@legacy.html
- shard-apl: NOTRUN -> [TIMEOUT][29] ([i915#1319])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl3/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][30] -> [DMESG-WARN][31] ([i915#180]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-random:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#54]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html
* igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding:
- shard-skl: NOTRUN -> [FAIL][34] ([i915#54]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-random:
- shard-tglb: NOTRUN -> [SKIP][35] ([fdo#109279])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-512x512-random.html
* igt@kms_cursor_crc@pipe-d-cursor-128x42-sliding:
- shard-kbl: NOTRUN -> [SKIP][36] ([fdo#109271]) +40 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl3/igt@kms_cursor_crc@pipe-d-cursor-128x42-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-skl: NOTRUN -> [FAIL][37] ([i915#2346])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-skl: [PASS][38] -> [FAIL][39] ([i915#2346])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][40] -> [INCOMPLETE][41] ([i915#180])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-tglb: NOTRUN -> [SKIP][42] ([fdo#111825]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb6/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp1:
- shard-kbl: [PASS][43] -> [FAIL][44] ([i915#79])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl7/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [PASS][45] -> [FAIL][46] ([i915#2122])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a2:
- shard-glk: [PASS][47] -> [FAIL][48] ([i915#2122])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-glk1/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a2.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-glk7/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-apl: NOTRUN -> [FAIL][49] ([i915#2641])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271]) +59 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#533])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl7/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][52] ([fdo#108145] / [i915#265]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
- shard-kbl: NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
- shard-skl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][55] -> [FAIL][56] ([fdo#108145] / [i915#265])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#658]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl10/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
- shard-tglb: NOTRUN -> [SKIP][59] ([i915#2920])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-kbl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][61] -> [SKIP][62] ([fdo#109441]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-skl: [PASS][63] -> [INCOMPLETE][64] ([i915#198] / [i915#2295])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf@polling-parameterized:
- shard-tglb: [PASS][65] -> [FAIL][66] ([i915#1542])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-tglb7/igt@perf@polling-parameterized.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb7/igt@perf@polling-parameterized.html
* igt@sysfs_clients@recycle:
- shard-glk: [PASS][67] -> [FAIL][68] ([i915#3028])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-glk5/igt@sysfs_clients@recycle.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-glk9/igt@sysfs_clients@recycle.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-skl: [INCOMPLETE][69] ([i915#198]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][71] ([i915#2842]) -> [PASS][72] +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][73] ([i915#2842]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl1/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [FAIL][75] ([i915#2842]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-glk2/igt@gem_exec_fair@basic-pace@vcs0.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-glk3/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-apl: [FAIL][77] ([i915#2389]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl1/igt@gem_exec_reloc@basic-many-active@rcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl3/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-skl: [DMESG-WARN][79] ([i915#1610] / [i915#2803]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl4/igt@gem_exec_schedule@u-fairslice@rcs0.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl10/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-apl: [DMESG-WARN][81] ([i915#1610]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl1/igt@gem_exec_schedule@u-fairslice@vcs0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl3/igt@gem_exec_schedule@u-fairslice@vcs0.html
* igt@gem_exec_schedule@u-fairslice@vecs0:
- shard-tglb: [DMESG-WARN][83] ([i915#2803]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-tglb3/igt@gem_exec_schedule@u-fairslice@vecs0.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb6/igt@gem_exec_schedule@u-fairslice@vecs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-hsw: [WARN][85] ([i915#1519]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-hsw1/igt@i915_pm_rc6_residency@rc6-fence.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-hsw6/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][87] ([i915#180]) -> [PASS][88] +3 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [FAIL][89] ([i915#2521]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl3/igt@kms_async_flips@alternate-sync-async-flip.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
- shard-skl: [FAIL][91] ([i915#54]) -> [PASS][92] +9 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [FAIL][93] ([i915#2122]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][95] ([i915#1188]) -> [PASS][96] +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][97] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-iclb4/igt@kms_psr2_su@frontbuffer.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][99] ([fdo#109441]) -> [PASS][100] +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_vblank@pipe-b-accuracy-idle:
- shard-skl: [DMESG-WARN][101] ([i915#1982]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl4/igt@kms_vblank@pipe-b-accuracy-idle.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl9/igt@kms_vblank@pipe-b-accuracy-idle.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][103] ([i915#180]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-kbl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@sysfs_clients@recycle:
- shard-tglb: [FAIL][105] ([i915#3028]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-tglb2/igt@sysfs_clients@recycle.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb2/igt@sysfs_clients@recycle.html
* igt@sysfs_clients@split-10@bcs0:
- shard-apl: [SKIP][107] ([fdo#109271] / [i915#3026]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl7/igt@sysfs_clients@split-10@bcs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl2/igt@sysfs_clients@split-10@bcs0.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][109] ([i915#588]) -> [SKIP][110] ([i915#658])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_content_protection@srm:
- shard-apl: [TIMEOUT][111] ([i915#1319]) -> [FAIL][112] ([fdo#110321])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl8/igt@kms_content_protection@srm.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl7/igt@kms_content_protection@srm.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-iclb: [SKIP][113] ([i915#658]) -> [SKIP][114] ([i915#2920]) +2 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][115] ([i915#2920]) -> [SKIP][116] ([i915#658]) +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122]) ([i915#1814] / [i915#2295] / [i915#2505] / [i915#3002] / [i915#602] / [i915#92]) -> ([FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130]) ([i915#1814] / [i915#2295] / [i915#2505] / [i915#3002] / [i915#92])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-kbl4/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-kbl6/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-kbl7/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-kbl2/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-kbl7/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-kbl6/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl3/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl1/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl6/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl1/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl1/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl6/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl6/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-kbl1/igt@runner@aborted.html
- shard-apl: ([FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#1610] / [i915#1814] / [i915#2295] / [i915#2426] / [i915#3002]) -> ([FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145]) ([fdo#109271] / [i915#2295] / [i915#3002])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl6/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl3/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl2/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl1/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl3/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl6/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl8/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-apl4/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl3/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl2/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl7/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl2/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl7/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl2/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-apl1/igt@runner@aborted.html
- shard-tglb: ([FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149]) ([i915#1764] / [i915#2295] / [i915#2426] / [i915#2667] / [i915#2803] / [i915#3002]) -> ([FAIL][150], [FAIL][151], [FAIL][152]) ([i915#2295] / [i915#2667] / [i915#3002])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-tglb8/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-tglb8/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-tglb3/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-tglb1/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb8/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb8/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-tglb1/igt@runner@aborted.html
- shard-skl: ([FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157]) ([i915#1814] / [i915#2029] / [i915#2295] / [i915#2426] / [i915#3002]) -> ([FAIL][158], [FAIL][159], [FAIL][160]) ([i915#2295] / [i915#3002])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl4/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl4/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl5/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl4/igt@runner@aborted.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9771/shard-skl5/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl9/igt@runner@aborted.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl4/igt@runner@aborted.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/shard-skl10/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cg
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19673/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev3)
2021-02-12 18:50 ` Lyude Paul
` (3 preceding siblings ...)
(?)
@ 2021-02-12 23:30 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2021-02-12 23:30 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3785 bytes --]
== Series Details ==
Series: drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev3)
URL : https://patchwork.freedesktop.org/series/86346/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9772 -> Patchwork_19675
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/index.html
Known issues
------------
Here are the changes found in Patchwork_19675 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-soraka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/fi-kbl-soraka/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/fi-kbl-soraka/igt@i915_pm_rpm@module-reload.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([i915#1372])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [DMESG-WARN][7] ([i915#2411] / [i915#402]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live@client:
- fi-glk-dsi: [DMESG-FAIL][9] ([i915#3047]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/fi-glk-dsi/igt@i915_selftest@live@client.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/fi-glk-dsi/igt@i915_selftest@live@client.html
* igt@prime_self_import@basic-with_one_bo:
- fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/fi-tgl-y/igt@prime_self_import@basic-with_one_bo.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/fi-tgl-y/igt@prime_self_import@basic-with_one_bo.html
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#3047]: https://gitlab.freedesktop.org/drm/intel/issues/3047
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (45 -> 39)
------------------------------
Missing (6): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9772 -> Patchwork_19675
CI-20190529: 20190529
CI_DRM_9772: e1ed2a25853b41a3f1561a4388de3edfef206170 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6003: 627cc5353535d61fa33c5f7ff7e64f154c84f10a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19675: 6117b3e1da840d32ba6e08af8c07e830a5778602 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6117b3e1da84 drm/i915/gen9bc: Handle TGP PCH during suspend/resume
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev3)
2021-02-12 18:50 ` Lyude Paul
` (4 preceding siblings ...)
(?)
@ 2021-02-13 1:11 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2021-02-13 1:11 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30283 bytes --]
== Series Details ==
Series: drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev3)
URL : https://patchwork.freedesktop.org/series/86346/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9772_full -> Patchwork_19675_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_19675_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][1] -> [TIMEOUT][2] ([i915#1037] / [i915#2481])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb2/igt@gem_eio@unwedge-stress.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][3] ([i915#2846])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2842])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb7/igt@gem_exec_fair@basic-pace@vcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-iclb: [PASS][11] -> [DMESG-WARN][12] ([i915#2803])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb3/igt@gem_exec_schedule@u-fairslice@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb3/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_pwrite@basic-exhaustion:
- shard-kbl: NOTRUN -> [WARN][13] ([i915#2658])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl6/igt@gem_pwrite@basic-exhaustion.html
- shard-apl: NOTRUN -> [WARN][14] ([i915#2658])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-apl8/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@input-checking:
- shard-kbl: NOTRUN -> [DMESG-WARN][15] ([i915#3002])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@process-exit-mmap-busy@uc:
- shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1699]) +3 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl3/igt@gem_userptr_blits@process-exit-mmap-busy@uc.html
* igt@gen3_mixed_blits:
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271]) +79 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl2/igt@gen3_mixed_blits.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [PASS][18] -> [INCOMPLETE][19] ([i915#2880])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][20] ([i915#454])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl3/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_ccs@pipe-c-crc-primary-basic:
- shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111304])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl3/igt@kms_ccs@pipe-c-crc-primary-basic.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) +6 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl4/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_color_chamelium@pipe-c-ctm-max:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111827]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-apl4/igt@kms_color_chamelium@pipe-c-ctm-max.html
* igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827]) +15 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl9/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][25] ([i915#1319])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl4/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding:
- shard-skl: NOTRUN -> [FAIL][26] ([i915#54])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
- shard-skl: [PASS][27] -> [FAIL][28] ([i915#54]) +8 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-256x85-onscreen:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109278]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb7/igt@kms_cursor_crc@pipe-d-cursor-256x85-onscreen.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109274] / [fdo#109278])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [PASS][33] -> [FAIL][34] ([i915#2370])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-hsw8/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [FAIL][35] ([i915#2346] / [i915#533])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
- shard-skl: [PASS][36] -> [INCOMPLETE][37] ([i915#198] / [i915#2295])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
* igt@kms_flip@modeset-vs-vblank-race-interruptible@a-edp1:
- shard-skl: NOTRUN -> [FAIL][38] ([i915#407])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl2/igt@kms_flip@modeset-vs-vblank-race-interruptible@a-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a2:
- shard-glk: [PASS][39] -> [FAIL][40] ([i915#2122])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-glk1/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a2.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-glk2/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a2.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#2122])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-skl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#2642])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#2642])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-kbl: NOTRUN -> [FAIL][45] ([i915#2641])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271]) +122 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109280])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
- shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271]) +42 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-apl4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html
* igt@kms_hdr@bpc-switch:
- shard-skl: NOTRUN -> [FAIL][49] ([i915#1188])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl4/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][50] -> [DMESG-WARN][51] ([i915#180]) +3 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl1/igt@kms_hdr@bpc-switch-suspend.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#533])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#533])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-apl4/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#533]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [PASS][55] -> [DMESG-WARN][56] ([i915#180] / [i915#533])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][57] ([fdo#108145] / [i915#265]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][58] ([i915#265])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-apl4/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][61] -> [FAIL][62] ([fdo#108145] / [i915#265]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#658]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-apl4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#658]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][66] -> [SKIP][67] ([fdo#109441]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_writeback@writeback-check-output:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2437])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@kms_writeback@writeback-check-output.html
* igt@prime_nv_api@nv_i915_import_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109291])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb7/igt@prime_nv_api@nv_i915_import_twice_check_flink_name.html
* igt@sysfs_clients@busy@vecs0:
- shard-kbl: [PASS][70] -> [FAIL][71] ([i915#3009])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl2/igt@sysfs_clients@busy@vecs0.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl3/igt@sysfs_clients@busy@vecs0.html
* igt@sysfs_clients@split-10@bcs0:
- shard-apl: [PASS][72] -> [SKIP][73] ([fdo#109271] / [i915#3026])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-apl1/igt@sysfs_clients@split-10@bcs0.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-apl1/igt@sysfs_clients@split-10@bcs0.html
#### Possible fixes ####
* igt@gem_exec_balancer@hang:
- shard-iclb: [INCOMPLETE][74] ([i915#1895] / [i915#2295]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb4/igt@gem_exec_balancer@hang.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb7/igt@gem_exec_balancer@hang.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-kbl: [SKIP][76] ([fdo#109271]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl4/igt@gem_exec_fair@basic-flow@rcs0.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl4/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][78] ([i915#2842]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
- shard-apl: [FAIL][80] ([i915#2842]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-apl4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-iclb: [FAIL][82] ([i915#2842]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [FAIL][84] ([i915#2842]) -> [PASS][85] +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-glk2/igt@gem_exec_fair@basic-pace@vcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-glk6/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-skl: [DMESG-WARN][86] ([i915#1610] / [i915#2803]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl10/igt@gem_exec_schedule@u-fairslice@rcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl6/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [DMESG-WARN][88] ([i915#180]) -> [PASS][89] +4 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl7/igt@gem_exec_suspend@basic-s3.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@gem_exec_suspend@basic-s3.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][90] ([i915#1436] / [i915#716]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl6/igt@gen9_exec_parse@allowed-single.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl7/igt@gen9_exec_parse@allowed-single.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-random:
- shard-skl: [FAIL][92] ([i915#54]) -> [PASS][93] +7 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [DMESG-WARN][94] ([i915#180]) -> [PASS][95] +2 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][96] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [FAIL][98] ([i915#2598]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1:
- shard-glk: [FAIL][100] ([i915#2122]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-glk1/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-glk2/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][102] ([fdo#108145] / [i915#265]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][104] ([fdo#109441]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][106] ([i915#198] / [i915#2405]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@sysfs_clients@recycle:
- shard-hsw: [FAIL][108] ([i915#3028]) -> [PASS][109] +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-hsw4/igt@sysfs_clients@recycle.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-hsw5/igt@sysfs_clients@recycle.html
* {igt@sysfs_clients@recycle-many}:
- shard-glk: [FAIL][110] ([i915#3028]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-glk9/igt@sysfs_clients@recycle-many.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-glk9/igt@sysfs_clients@recycle-many.html
- shard-tglb: [FAIL][112] ([i915#3028]) -> [PASS][113] +1 similar issue
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-tglb1/igt@sysfs_clients@recycle-many.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-tglb8/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@sema-25@vcs0:
- shard-skl: [SKIP][114] ([fdo#109271]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl10/igt@sysfs_clients@sema-25@vcs0.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl6/igt@sysfs_clients@sema-25@vcs0.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][116] ([i915#2842]) -> [SKIP][117] ([fdo#109271])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][118] ([i915#2842]) -> [FAIL][119] ([i915#2849])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][120] ([i915#1804] / [i915#2684]) -> [WARN][121] ([i915#2681] / [i915#2684])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: [SKIP][122] ([i915#2920]) -> [SKIP][123] ([i915#658]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
- shard-iclb: [SKIP][124] ([i915#658]) -> [SKIP][125] ([i915#2920]) +1 similar issue
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb4/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134]) ([i915#1814] / [i915#2295] / [i915#2505] / [i915#3002] / [i915#602] / [i915#92]) -> ([FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144]) ([i915#1814] / [i915#2295] / [i915#2505] / [i915#3002])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl7/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl7/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl4/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl6/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl7/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl7/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl1/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl1/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-kbl1/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl6/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl4/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl7/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl6/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-kbl1/igt@runner@aborted.html
- shard-iclb: ([FAIL][145], [FAIL][146], [FAIL][147]) ([i915#2295] / [i915#2724] / [i915#3002]) -> ([FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151]) ([i915#2295] / [i915#2426] / [i915#2724] / [i915#3002])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb3/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb5/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-iclb2/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb2/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb3/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb2/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-iclb1/igt@runner@aborted.html
- shard-skl: ([FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157]) ([i915#1436] / [i915#1814] / [i915#2029] / [i915#2295] / [i915#2426] / [i915#3002]) -> ([FAIL][158], [FAIL][159], [FAIL][160]) ([i915#2295] / [i915#3002])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl6/igt@runner@aborted.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl3/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl10/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl1/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl3/igt@runner@aborted.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9772/shard-skl1/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/shard-skl4/igt@runner@aborted.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19675/index.html
[-- Attachment #1.2: Type: text/html, Size: 33589 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
2021-02-12 18:50 ` Lyude Paul
(?)
@ 2021-02-16 18:08 ` Imre Deak
-1 siblings, 0 replies; 19+ messages in thread
From: Imre Deak @ 2021-02-16 18:08 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx, David Airlie, open list, open list:DRM DRIVERS
Hi,
thanks for respinning this patchset, some comments below.
On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
>
> v2:
> * Move Wa_14010685332 into it's own function - vsyrjala
> * Add TODO comment about figuring out if we can move this workaround - imre
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> 1 file changed, 36 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 98145a7f28a4..7d912aa950ee 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
Maybe a better name is cnp_display_clock_wa.
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> +
> + /*
> + * Wa_14010685332:cnp/cmp,tgp,adp
Bspec says this WA applies ICL onwards and it's not PCH specific, for
instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
add a 'clarify platforms where this applies' todo item.
> + * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
> + * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
> + */
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> +}
> +
> static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> GEN3_IRQ_RESET(uncore, GEN8_PCU_);
>
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
It was mentioned already earlier, why is this check necessary and can't we
just call ibx_irq_reset() for all PCHs?
> + GEN3_IRQ_RESET(uncore, SDE);
> + else if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_reset(dev_priv);
> +
> + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1))
The check could be also moved to the helper.
> + cnp_irq_post_reset(dev_priv);
> }
>
> static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
>
> - /* Wa_14010685332:cnp/cmp,tgp,adp */
> if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, 0);
> - }
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1))
> + cnp_irq_post_reset(dev_priv);
> }
>
> static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>
> spt_hpd_detection_setup(dev_priv);
> +
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_hpd_irq_setup(dev_priv);
This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
setup done already earlier in this function and
spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
like for ICP+ we need to call icp_hpd_irq_setup() instead of
spt_hpd_irq_setup(), but haven't checked in detail.
> }
>
> static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> + u32 mask = SDE_GMBUS_ICP;
> +
> + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> +}
> +
> static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_irq_postinstall(dev_priv);
> + else if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_postinstall(dev_priv);
>
> gen8_gt_irq_postinstall(&dev_priv->gt);
> @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> gen8_master_intr_enable(dev_priv->uncore.regs);
> }
>
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - u32 mask = SDE_GMBUS_ICP;
> -
> - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> -}
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-16 18:08 ` Imre Deak
0 siblings, 0 replies; 19+ messages in thread
From: Imre Deak @ 2021-02-16 18:08 UTC (permalink / raw)
To: Lyude Paul; +Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
Hi,
thanks for respinning this patchset, some comments below.
On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
>
> v2:
> * Move Wa_14010685332 into it's own function - vsyrjala
> * Add TODO comment about figuring out if we can move this workaround - imre
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> 1 file changed, 36 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 98145a7f28a4..7d912aa950ee 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
Maybe a better name is cnp_display_clock_wa.
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> +
> + /*
> + * Wa_14010685332:cnp/cmp,tgp,adp
Bspec says this WA applies ICL onwards and it's not PCH specific, for
instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
add a 'clarify platforms where this applies' todo item.
> + * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
> + * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
> + */
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> +}
> +
> static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> GEN3_IRQ_RESET(uncore, GEN8_PCU_);
>
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
It was mentioned already earlier, why is this check necessary and can't we
just call ibx_irq_reset() for all PCHs?
> + GEN3_IRQ_RESET(uncore, SDE);
> + else if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_reset(dev_priv);
> +
> + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1))
The check could be also moved to the helper.
> + cnp_irq_post_reset(dev_priv);
> }
>
> static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
>
> - /* Wa_14010685332:cnp/cmp,tgp,adp */
> if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, 0);
> - }
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1))
> + cnp_irq_post_reset(dev_priv);
> }
>
> static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>
> spt_hpd_detection_setup(dev_priv);
> +
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_hpd_irq_setup(dev_priv);
This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
setup done already earlier in this function and
spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
like for ICP+ we need to call icp_hpd_irq_setup() instead of
spt_hpd_irq_setup(), but haven't checked in detail.
> }
>
> static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> + u32 mask = SDE_GMBUS_ICP;
> +
> + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> +}
> +
> static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_irq_postinstall(dev_priv);
> + else if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_postinstall(dev_priv);
>
> gen8_gt_irq_postinstall(&dev_priv->gt);
> @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> gen8_master_intr_enable(dev_priv->uncore.regs);
> }
>
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - u32 mask = SDE_GMBUS_ICP;
> -
> - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> -}
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-16 18:08 ` Imre Deak
0 siblings, 0 replies; 19+ messages in thread
From: Imre Deak @ 2021-02-16 18:08 UTC (permalink / raw)
To: Lyude Paul; +Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
Hi,
thanks for respinning this patchset, some comments below.
On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
>
> v2:
> * Move Wa_14010685332 into it's own function - vsyrjala
> * Add TODO comment about figuring out if we can move this workaround - imre
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> 1 file changed, 36 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 98145a7f28a4..7d912aa950ee 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
Maybe a better name is cnp_display_clock_wa.
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> +
> + /*
> + * Wa_14010685332:cnp/cmp,tgp,adp
Bspec says this WA applies ICL onwards and it's not PCH specific, for
instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
add a 'clarify platforms where this applies' todo item.
> + * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
> + * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
> + */
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> +}
> +
> static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> GEN3_IRQ_RESET(uncore, GEN8_PCU_);
>
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
It was mentioned already earlier, why is this check necessary and can't we
just call ibx_irq_reset() for all PCHs?
> + GEN3_IRQ_RESET(uncore, SDE);
> + else if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_reset(dev_priv);
> +
> + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1))
The check could be also moved to the helper.
> + cnp_irq_post_reset(dev_priv);
> }
>
> static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
>
> - /* Wa_14010685332:cnp/cmp,tgp,adp */
> if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, 0);
> - }
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1))
> + cnp_irq_post_reset(dev_priv);
> }
>
> static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>
> spt_hpd_detection_setup(dev_priv);
> +
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_hpd_irq_setup(dev_priv);
This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
setup done already earlier in this function and
spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
like for ICP+ we need to call icp_hpd_irq_setup() instead of
spt_hpd_irq_setup(), but haven't checked in detail.
> }
>
> static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> + u32 mask = SDE_GMBUS_ICP;
> +
> + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> +}
> +
> static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_irq_postinstall(dev_priv);
> + else if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_postinstall(dev_priv);
>
> gen8_gt_irq_postinstall(&dev_priv->gt);
> @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> gen8_master_intr_enable(dev_priv->uncore.regs);
> }
>
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - u32 mask = SDE_GMBUS_ICP;
> -
> - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> -}
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
2021-02-16 18:08 ` Imre Deak
(?)
@ 2021-02-17 2:36 ` Lyude Paul
-1 siblings, 0 replies; 19+ messages in thread
From: Lyude Paul @ 2021-02-17 2:36 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx, David Airlie, open list, open list:DRM DRIVERS
On Tue, 2021-02-16 at 20:08 +0200, Imre Deak wrote:
> Hi,
>
> thanks for respinning this patchset, some comments below.
>
> On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> >
> > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > setup TGP PCH.
> >
> > v2:
> > * Move Wa_14010685332 into it's own function - vsyrjala
> > * Add TODO comment about figuring out if we can move this workaround - imre
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > Signed-off-by: Lyude Paul <lyude@redhat.com>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> > 1 file changed, 36 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 98145a7f28a4..7d912aa950ee 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct
> > drm_i915_private *dev_priv)
> > spin_unlock_irq(&dev_priv->irq_lock);
> > }
> >
> > +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
>
> Maybe a better name is cnp_display_clock_wa.
>
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > +
> > + /*
> > + * Wa_14010685332:cnp/cmp,tgp,adp
>
> Bspec says this WA applies ICL onwards and it's not PCH specific, for
> instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
> add a 'clarify platforms where this applies' todo item.
>
> > + * TODO: Figure out if this workaround can be applied in the s0ix
> > suspend/resume handlers as
> > + * on earlier platforms and whether the workaround is also needed
> > for runtime suspend/resume
> > + */
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> > +}
> > +
> > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > {
> > struct intel_uncore *uncore = &dev_priv->uncore;
> > @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private
> > *dev_priv)
> > GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> >
> > - if (HAS_PCH_SPLIT(dev_priv))
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>
> It was mentioned already earlier, why is this check necessary and can't we
> just call ibx_irq_reset() for all PCHs?
>
> > + GEN3_IRQ_RESET(uncore, SDE);
> > + else if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_reset(dev_priv);
> > +
> > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > < PCH_DG1))
>
> The check could be also moved to the helper.
>
> > + cnp_irq_post_reset(dev_priv);
> > }
> >
> > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct
> > drm_i915_private *dev_priv)
> > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > GEN3_IRQ_RESET(uncore, SDE);
> >
> > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS, 0);
> > - }
> > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > < PCH_DG1))
> > + cnp_irq_post_reset(dev_priv);
> > }
> >
> > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private
> > *dev_priv)
> > ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> >
> > spt_hpd_detection_setup(dev_priv);
> > +
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_hpd_irq_setup(dev_priv);
>
> This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
> setup done already earlier in this function and
> spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
> like for ICP+ we need to call icp_hpd_irq_setup() instead of
> spt_hpd_irq_setup(), but haven't checked in detail.
Could you please check :)? I don't work at Intel so you have far more access to
this information then I do.
FWIW the code -looks- mostly equivalent to me (SHOTPLUG_CTL_DDI and
SHOTPLUG_CTL_TC seem to be equivalent registers to what's set in
spt_hpd_irq_setup()), but the icelake point codepath enables an additional port,
and changes an additional register called SHPD_FILTER_CNT. I'll update it to use
this in the next patch, but please definitely confirm this. I would very much
like to avoid potentially breaking unrelated ICP systems with this.
>
> > }
> >
> > static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> > @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > }
> > }
> >
> > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > + u32 mask = SDE_GMBUS_ICP;
> > +
> > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > +}
> > +
> > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > - if (HAS_PCH_SPLIT(dev_priv))
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_irq_postinstall(dev_priv);
> > + else if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_postinstall(dev_priv);
> >
> > gen8_gt_irq_postinstall(&dev_priv->gt);
> > @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > gen8_master_intr_enable(dev_priv->uncore.regs);
> > }
> >
> > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > -{
> > - struct intel_uncore *uncore = &dev_priv->uncore;
> > - u32 mask = SDE_GMBUS_ICP;
> > -
> > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > -}
> >
> > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > --
> > 2.29.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 2:36 ` Lyude Paul
0 siblings, 0 replies; 19+ messages in thread
From: Lyude Paul @ 2021-02-17 2:36 UTC (permalink / raw)
To: imre.deak; +Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
On Tue, 2021-02-16 at 20:08 +0200, Imre Deak wrote:
> Hi,
>
> thanks for respinning this patchset, some comments below.
>
> On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> >
> > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > setup TGP PCH.
> >
> > v2:
> > * Move Wa_14010685332 into it's own function - vsyrjala
> > * Add TODO comment about figuring out if we can move this workaround - imre
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > Signed-off-by: Lyude Paul <lyude@redhat.com>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> > 1 file changed, 36 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 98145a7f28a4..7d912aa950ee 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct
> > drm_i915_private *dev_priv)
> > spin_unlock_irq(&dev_priv->irq_lock);
> > }
> >
> > +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
>
> Maybe a better name is cnp_display_clock_wa.
>
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > +
> > + /*
> > + * Wa_14010685332:cnp/cmp,tgp,adp
>
> Bspec says this WA applies ICL onwards and it's not PCH specific, for
> instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
> add a 'clarify platforms where this applies' todo item.
>
> > + * TODO: Figure out if this workaround can be applied in the s0ix
> > suspend/resume handlers as
> > + * on earlier platforms and whether the workaround is also needed
> > for runtime suspend/resume
> > + */
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> > +}
> > +
> > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > {
> > struct intel_uncore *uncore = &dev_priv->uncore;
> > @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private
> > *dev_priv)
> > GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> >
> > - if (HAS_PCH_SPLIT(dev_priv))
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>
> It was mentioned already earlier, why is this check necessary and can't we
> just call ibx_irq_reset() for all PCHs?
>
> > + GEN3_IRQ_RESET(uncore, SDE);
> > + else if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_reset(dev_priv);
> > +
> > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > < PCH_DG1))
>
> The check could be also moved to the helper.
>
> > + cnp_irq_post_reset(dev_priv);
> > }
> >
> > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct
> > drm_i915_private *dev_priv)
> > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > GEN3_IRQ_RESET(uncore, SDE);
> >
> > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS, 0);
> > - }
> > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > < PCH_DG1))
> > + cnp_irq_post_reset(dev_priv);
> > }
> >
> > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private
> > *dev_priv)
> > ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> >
> > spt_hpd_detection_setup(dev_priv);
> > +
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_hpd_irq_setup(dev_priv);
>
> This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
> setup done already earlier in this function and
> spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
> like for ICP+ we need to call icp_hpd_irq_setup() instead of
> spt_hpd_irq_setup(), but haven't checked in detail.
Could you please check :)? I don't work at Intel so you have far more access to
this information then I do.
FWIW the code -looks- mostly equivalent to me (SHOTPLUG_CTL_DDI and
SHOTPLUG_CTL_TC seem to be equivalent registers to what's set in
spt_hpd_irq_setup()), but the icelake point codepath enables an additional port,
and changes an additional register called SHPD_FILTER_CNT. I'll update it to use
this in the next patch, but please definitely confirm this. I would very much
like to avoid potentially breaking unrelated ICP systems with this.
>
> > }
> >
> > static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> > @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > }
> > }
> >
> > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > + u32 mask = SDE_GMBUS_ICP;
> > +
> > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > +}
> > +
> > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > - if (HAS_PCH_SPLIT(dev_priv))
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_irq_postinstall(dev_priv);
> > + else if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_postinstall(dev_priv);
> >
> > gen8_gt_irq_postinstall(&dev_priv->gt);
> > @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > gen8_master_intr_enable(dev_priv->uncore.regs);
> > }
> >
> > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > -{
> > - struct intel_uncore *uncore = &dev_priv->uncore;
> > - u32 mask = SDE_GMBUS_ICP;
> > -
> > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > -}
> >
> > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > --
> > 2.29.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 2:36 ` Lyude Paul
0 siblings, 0 replies; 19+ messages in thread
From: Lyude Paul @ 2021-02-17 2:36 UTC (permalink / raw)
To: imre.deak; +Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
On Tue, 2021-02-16 at 20:08 +0200, Imre Deak wrote:
> Hi,
>
> thanks for respinning this patchset, some comments below.
>
> On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> >
> > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > setup TGP PCH.
> >
> > v2:
> > * Move Wa_14010685332 into it's own function - vsyrjala
> > * Add TODO comment about figuring out if we can move this workaround - imre
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > Signed-off-by: Lyude Paul <lyude@redhat.com>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> > 1 file changed, 36 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 98145a7f28a4..7d912aa950ee 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct
> > drm_i915_private *dev_priv)
> > spin_unlock_irq(&dev_priv->irq_lock);
> > }
> >
> > +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
>
> Maybe a better name is cnp_display_clock_wa.
>
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > +
> > + /*
> > + * Wa_14010685332:cnp/cmp,tgp,adp
>
> Bspec says this WA applies ICL onwards and it's not PCH specific, for
> instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
> add a 'clarify platforms where this applies' todo item.
>
> > + * TODO: Figure out if this workaround can be applied in the s0ix
> > suspend/resume handlers as
> > + * on earlier platforms and whether the workaround is also needed
> > for runtime suspend/resume
> > + */
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> > +}
> > +
> > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > {
> > struct intel_uncore *uncore = &dev_priv->uncore;
> > @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private
> > *dev_priv)
> > GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> >
> > - if (HAS_PCH_SPLIT(dev_priv))
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>
> It was mentioned already earlier, why is this check necessary and can't we
> just call ibx_irq_reset() for all PCHs?
>
> > + GEN3_IRQ_RESET(uncore, SDE);
> > + else if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_reset(dev_priv);
> > +
> > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > < PCH_DG1))
>
> The check could be also moved to the helper.
>
> > + cnp_irq_post_reset(dev_priv);
> > }
> >
> > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct
> > drm_i915_private *dev_priv)
> > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > GEN3_IRQ_RESET(uncore, SDE);
> >
> > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS, 0);
> > - }
> > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > < PCH_DG1))
> > + cnp_irq_post_reset(dev_priv);
> > }
> >
> > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private
> > *dev_priv)
> > ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> >
> > spt_hpd_detection_setup(dev_priv);
> > +
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_hpd_irq_setup(dev_priv);
>
> This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
> setup done already earlier in this function and
> spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
> like for ICP+ we need to call icp_hpd_irq_setup() instead of
> spt_hpd_irq_setup(), but haven't checked in detail.
Could you please check :)? I don't work at Intel so you have far more access to
this information then I do.
FWIW the code -looks- mostly equivalent to me (SHOTPLUG_CTL_DDI and
SHOTPLUG_CTL_TC seem to be equivalent registers to what's set in
spt_hpd_irq_setup()), but the icelake point codepath enables an additional port,
and changes an additional register called SHPD_FILTER_CNT. I'll update it to use
this in the next patch, but please definitely confirm this. I would very much
like to avoid potentially breaking unrelated ICP systems with this.
>
> > }
> >
> > static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> > @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > }
> > }
> >
> > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > + u32 mask = SDE_GMBUS_ICP;
> > +
> > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > +}
> > +
> > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > - if (HAS_PCH_SPLIT(dev_priv))
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_irq_postinstall(dev_priv);
> > + else if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_postinstall(dev_priv);
> >
> > gen8_gt_irq_postinstall(&dev_priv->gt);
> > @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > gen8_master_intr_enable(dev_priv->uncore.regs);
> > }
> >
> > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > -{
> > - struct intel_uncore *uncore = &dev_priv->uncore;
> > - u32 mask = SDE_GMBUS_ICP;
> > -
> > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > -}
> >
> > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > --
> > 2.29.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
2021-02-17 2:36 ` Lyude Paul
(?)
@ 2021-02-17 2:37 ` Lyude Paul
-1 siblings, 0 replies; 19+ messages in thread
From: Lyude Paul @ 2021-02-17 2:37 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx, David Airlie, open list, open list:DRM DRIVERS
On Tue, 2021-02-16 at 21:36 -0500, Lyude Paul wrote:
> On Tue, 2021-02-16 at 20:08 +0200, Imre Deak wrote:
> > Hi,
> >
> > thanks for respinning this patchset, some comments below.
> >
> > On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> > > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > >
> > > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > > setup TGP PCH.
> > >
> > > v2:
> > > * Move Wa_14010685332 into it's own function - vsyrjala
> > > * Add TODO comment about figuring out if we can move this workaround -
> > > imre
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Tejas Upadhyay <
> > > tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > Signed-off-by: Lyude Paul <lyude@redhat.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> > > 1 file changed, 36 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 98145a7f28a4..7d912aa950ee 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
> >
> > Maybe a better name is cnp_display_clock_wa.
> >
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > +
> > > + /*
> > > + * Wa_14010685332:cnp/cmp,tgp,adp
> >
> > Bspec says this WA applies ICL onwards and it's not PCH specific, for
> > instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
> > add a 'clarify platforms where this applies' todo item.
> >
> > > + * TODO: Figure out if this workaround can be applied in the s0ix
> > > suspend/resume handlers as
> > > + * on earlier platforms and whether the workaround is also needed
> > > for runtime suspend/resume
> > > + */
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> > > +}
> > > +
> > > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > > {
> > > struct intel_uncore *uncore = &dev_priv->uncore;
> > > @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private
> > > *dev_priv)
> > > GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > > GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > >
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >
> > It was mentioned already earlier, why is this check necessary and can't we
> > just call ibx_irq_reset() for all PCHs?
> >
> > > + GEN3_IRQ_RESET(uncore, SDE);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_reset(dev_priv);
> > > +
> > > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1))
> >
> > The check could be also moved to the helper.
> >
> > > + cnp_irq_post_reset(dev_priv);
> > > }
> > >
> > > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > GEN3_IRQ_RESET(uncore, SDE);
> > >
> > > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > > if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS, 0);
> > > - }
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1))
> > > + cnp_irq_post_reset(dev_priv);
> > > }
> > >
> > > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct
> > > drm_i915_private
> > > *dev_priv)
> > > ibx_display_interrupt_update(dev_priv, hotplug_irqs,
> > > enabled_irqs);
> > >
> > > spt_hpd_detection_setup(dev_priv);
> > > +
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_hpd_irq_setup(dev_priv);
> >
> > This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
> > setup done already earlier in this function and
> > spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
> > like for ICP+ we need to call icp_hpd_irq_setup() instead of
> > spt_hpd_irq_setup(), but haven't checked in detail.
>
> Could you please check :)? I don't work at Intel so you have far more access
> to
> this information then I do.
>
> FWIW the code -looks- mostly equivalent to me (SHOTPLUG_CTL_DDI and
> SHOTPLUG_CTL_TC seem to be equivalent registers to what's set in
> spt_hpd_irq_setup()), but the icelake point codepath enables an additional
> port,
> and changes an additional register called SHPD_FILTER_CNT. I'll update it to
> use
> this in the next patch, but please definitely confirm this. I would very much
> like to avoid potentially breaking unrelated ICP systems with this.
JFYI I misspoke on the SHPD_FILTER_CNT, somehow my eyes missed it when I was
looking at spt_hpd_irq_setup(). Still definitely confirm this correct if you can
though
>
> >
> > > }
> > >
> > > static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> > > @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > }
> > > }
> > >
> > > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > + u32 mask = SDE_GMBUS_ICP;
> > > +
> > > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > > +}
> > > +
> > > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_irq_postinstall(dev_priv);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_postinstall(dev_priv);
> > >
> > > gen8_gt_irq_postinstall(&dev_priv->gt);
> > > @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > gen8_master_intr_enable(dev_priv->uncore.regs);
> > > }
> > >
> > > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > -{
> > > - struct intel_uncore *uncore = &dev_priv->uncore;
> > > - u32 mask = SDE_GMBUS_ICP;
> > > -
> > > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > > -}
> > >
> > > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > --
> > > 2.29.2
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
>
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 2:37 ` Lyude Paul
0 siblings, 0 replies; 19+ messages in thread
From: Lyude Paul @ 2021-02-17 2:37 UTC (permalink / raw)
To: imre.deak; +Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
On Tue, 2021-02-16 at 21:36 -0500, Lyude Paul wrote:
> On Tue, 2021-02-16 at 20:08 +0200, Imre Deak wrote:
> > Hi,
> >
> > thanks for respinning this patchset, some comments below.
> >
> > On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> > > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > >
> > > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > > setup TGP PCH.
> > >
> > > v2:
> > > * Move Wa_14010685332 into it's own function - vsyrjala
> > > * Add TODO comment about figuring out if we can move this workaround -
> > > imre
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Tejas Upadhyay <
> > > tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > Signed-off-by: Lyude Paul <lyude@redhat.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> > > 1 file changed, 36 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 98145a7f28a4..7d912aa950ee 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
> >
> > Maybe a better name is cnp_display_clock_wa.
> >
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > +
> > > + /*
> > > + * Wa_14010685332:cnp/cmp,tgp,adp
> >
> > Bspec says this WA applies ICL onwards and it's not PCH specific, for
> > instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
> > add a 'clarify platforms where this applies' todo item.
> >
> > > + * TODO: Figure out if this workaround can be applied in the s0ix
> > > suspend/resume handlers as
> > > + * on earlier platforms and whether the workaround is also needed
> > > for runtime suspend/resume
> > > + */
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> > > +}
> > > +
> > > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > > {
> > > struct intel_uncore *uncore = &dev_priv->uncore;
> > > @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private
> > > *dev_priv)
> > > GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > > GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > >
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >
> > It was mentioned already earlier, why is this check necessary and can't we
> > just call ibx_irq_reset() for all PCHs?
> >
> > > + GEN3_IRQ_RESET(uncore, SDE);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_reset(dev_priv);
> > > +
> > > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1))
> >
> > The check could be also moved to the helper.
> >
> > > + cnp_irq_post_reset(dev_priv);
> > > }
> > >
> > > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > GEN3_IRQ_RESET(uncore, SDE);
> > >
> > > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > > if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS, 0);
> > > - }
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1))
> > > + cnp_irq_post_reset(dev_priv);
> > > }
> > >
> > > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct
> > > drm_i915_private
> > > *dev_priv)
> > > ibx_display_interrupt_update(dev_priv, hotplug_irqs,
> > > enabled_irqs);
> > >
> > > spt_hpd_detection_setup(dev_priv);
> > > +
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_hpd_irq_setup(dev_priv);
> >
> > This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
> > setup done already earlier in this function and
> > spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
> > like for ICP+ we need to call icp_hpd_irq_setup() instead of
> > spt_hpd_irq_setup(), but haven't checked in detail.
>
> Could you please check :)? I don't work at Intel so you have far more access
> to
> this information then I do.
>
> FWIW the code -looks- mostly equivalent to me (SHOTPLUG_CTL_DDI and
> SHOTPLUG_CTL_TC seem to be equivalent registers to what's set in
> spt_hpd_irq_setup()), but the icelake point codepath enables an additional
> port,
> and changes an additional register called SHPD_FILTER_CNT. I'll update it to
> use
> this in the next patch, but please definitely confirm this. I would very much
> like to avoid potentially breaking unrelated ICP systems with this.
JFYI I misspoke on the SHPD_FILTER_CNT, somehow my eyes missed it when I was
looking at spt_hpd_irq_setup(). Still definitely confirm this correct if you can
though
>
> >
> > > }
> > >
> > > static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> > > @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > }
> > > }
> > >
> > > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > + u32 mask = SDE_GMBUS_ICP;
> > > +
> > > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > > +}
> > > +
> > > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_irq_postinstall(dev_priv);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_postinstall(dev_priv);
> > >
> > > gen8_gt_irq_postinstall(&dev_priv->gt);
> > > @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > gen8_master_intr_enable(dev_priv->uncore.regs);
> > > }
> > >
> > > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > -{
> > > - struct intel_uncore *uncore = &dev_priv->uncore;
> > > - u32 mask = SDE_GMBUS_ICP;
> > > -
> > > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > > -}
> > >
> > > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > --
> > > 2.29.2
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
>
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 2:37 ` Lyude Paul
0 siblings, 0 replies; 19+ messages in thread
From: Lyude Paul @ 2021-02-17 2:37 UTC (permalink / raw)
To: imre.deak; +Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
On Tue, 2021-02-16 at 21:36 -0500, Lyude Paul wrote:
> On Tue, 2021-02-16 at 20:08 +0200, Imre Deak wrote:
> > Hi,
> >
> > thanks for respinning this patchset, some comments below.
> >
> > On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> > > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > >
> > > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > > setup TGP PCH.
> > >
> > > v2:
> > > * Move Wa_14010685332 into it's own function - vsyrjala
> > > * Add TODO comment about figuring out if we can move this workaround -
> > > imre
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Tejas Upadhyay <
> > > tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > Signed-off-by: Lyude Paul <lyude@redhat.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> > > 1 file changed, 36 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 98145a7f28a4..7d912aa950ee 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
> >
> > Maybe a better name is cnp_display_clock_wa.
> >
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > +
> > > + /*
> > > + * Wa_14010685332:cnp/cmp,tgp,adp
> >
> > Bspec says this WA applies ICL onwards and it's not PCH specific, for
> > instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
> > add a 'clarify platforms where this applies' todo item.
> >
> > > + * TODO: Figure out if this workaround can be applied in the s0ix
> > > suspend/resume handlers as
> > > + * on earlier platforms and whether the workaround is also needed
> > > for runtime suspend/resume
> > > + */
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> > > +}
> > > +
> > > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > > {
> > > struct intel_uncore *uncore = &dev_priv->uncore;
> > > @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private
> > > *dev_priv)
> > > GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > > GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > >
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >
> > It was mentioned already earlier, why is this check necessary and can't we
> > just call ibx_irq_reset() for all PCHs?
> >
> > > + GEN3_IRQ_RESET(uncore, SDE);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_reset(dev_priv);
> > > +
> > > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1))
> >
> > The check could be also moved to the helper.
> >
> > > + cnp_irq_post_reset(dev_priv);
> > > }
> > >
> > > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > GEN3_IRQ_RESET(uncore, SDE);
> > >
> > > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > > if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS, 0);
> > > - }
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1))
> > > + cnp_irq_post_reset(dev_priv);
> > > }
> > >
> > > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct
> > > drm_i915_private
> > > *dev_priv)
> > > ibx_display_interrupt_update(dev_priv, hotplug_irqs,
> > > enabled_irqs);
> > >
> > > spt_hpd_detection_setup(dev_priv);
> > > +
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_hpd_irq_setup(dev_priv);
> >
> > This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
> > setup done already earlier in this function and
> > spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
> > like for ICP+ we need to call icp_hpd_irq_setup() instead of
> > spt_hpd_irq_setup(), but haven't checked in detail.
>
> Could you please check :)? I don't work at Intel so you have far more access
> to
> this information then I do.
>
> FWIW the code -looks- mostly equivalent to me (SHOTPLUG_CTL_DDI and
> SHOTPLUG_CTL_TC seem to be equivalent registers to what's set in
> spt_hpd_irq_setup()), but the icelake point codepath enables an additional
> port,
> and changes an additional register called SHPD_FILTER_CNT. I'll update it to
> use
> this in the next patch, but please definitely confirm this. I would very much
> like to avoid potentially breaking unrelated ICP systems with this.
JFYI I misspoke on the SHPD_FILTER_CNT, somehow my eyes missed it when I was
looking at spt_hpd_irq_setup(). Still definitely confirm this correct if you can
though
>
> >
> > > }
> > >
> > > static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> > > @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > }
> > > }
> > >
> > > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > + u32 mask = SDE_GMBUS_ICP;
> > > +
> > > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > > +}
> > > +
> > > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_irq_postinstall(dev_priv);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_postinstall(dev_priv);
> > >
> > > gen8_gt_irq_postinstall(&dev_priv->gt);
> > > @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > gen8_master_intr_enable(dev_priv->uncore.regs);
> > > }
> > >
> > > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > -{
> > > - struct intel_uncore *uncore = &dev_priv->uncore;
> > > - u32 mask = SDE_GMBUS_ICP;
> > > -
> > > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > > -}
> > >
> > > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > --
> > > 2.29.2
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
>
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
2021-02-17 2:36 ` Lyude Paul
(?)
@ 2021-02-17 7:52 ` Imre Deak
-1 siblings, 0 replies; 19+ messages in thread
From: Imre Deak @ 2021-02-17 7:52 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx, David Airlie, open list, open list:DRM DRIVERS
On Tue, Feb 16, 2021 at 09:36:01PM -0500, Lyude Paul wrote:
> On Tue, 2021-02-16 at 20:08 +0200, Imre Deak wrote:
> > Hi,
> >
> > thanks for respinning this patchset, some comments below.
> >
> > On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> > > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > >
> > > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > > setup TGP PCH.
> > >
> > > v2:
> > > * Move Wa_14010685332 into it's own function - vsyrjala
> > > * Add TODO comment about figuring out if we can move this workaround - imre
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > Signed-off-by: Lyude Paul <lyude@redhat.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> > > 1 file changed, 36 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 98145a7f28a4..7d912aa950ee 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
> >
> > Maybe a better name is cnp_display_clock_wa.
> >
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > +
> > > + /*
> > > + * Wa_14010685332:cnp/cmp,tgp,adp
> >
> > Bspec says this WA applies ICL onwards and it's not PCH specific, for
> > instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
> > add a 'clarify platforms where this applies' todo item.
> >
> > > + * TODO: Figure out if this workaround can be applied in the s0ix
> > > suspend/resume handlers as
> > > + * on earlier platforms and whether the workaround is also needed
> > > for runtime suspend/resume
> > > + */
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> > > +}
> > > +
> > > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > > {
> > > struct intel_uncore *uncore = &dev_priv->uncore;
> > > @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private
> > > *dev_priv)
> > > GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > > GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > >
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >
> > It was mentioned already earlier, why is this check necessary and can't we
> > just call ibx_irq_reset() for all PCHs?
> >
> > > + GEN3_IRQ_RESET(uncore, SDE);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_reset(dev_priv);
> > > +
> > > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1))
> >
> > The check could be also moved to the helper.
> >
> > > + cnp_irq_post_reset(dev_priv);
> > > }
> > >
> > > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > GEN3_IRQ_RESET(uncore, SDE);
> > >
> > > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > > if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS, 0);
> > > - }
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1))
> > > + cnp_irq_post_reset(dev_priv);
> > > }
> > >
> > > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private
> > > *dev_priv)
> > > ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> > >
> > > spt_hpd_detection_setup(dev_priv);
> > > +
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_hpd_irq_setup(dev_priv);
> >
> > This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
> > setup done already earlier in this function and
> > spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
> > like for ICP+ we need to call icp_hpd_irq_setup() instead of
> > spt_hpd_irq_setup(), but haven't checked in detail.
>
> Could you please check :)? I don't work at Intel so you have far more access to
> this information then I do.
>
> FWIW the code -looks- mostly equivalent to me (SHOTPLUG_CTL_DDI and
> SHOTPLUG_CTL_TC seem to be equivalent registers to what's set in
> spt_hpd_irq_setup()), but the icelake point codepath enables an additional port,
> and changes an additional register called SHPD_FILTER_CNT.
The register definitions for SHOTPLUG_CTL_DDI wrt. PCH_PORT_HOTPLUG and
SHOTPLUG_CTL_TC wrt. PCH_PORT_HOTPLUG2 are different even though their
addresses match.
> I'll update it to use this in the next patch, but please definitely
> confirm this. I would very much like to avoid potentially breaking
> unrelated ICP systems with this.
>
> >
> > > }
> > >
> > > static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> > > @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > }
> > > }
> > >
> > > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > + u32 mask = SDE_GMBUS_ICP;
> > > +
> > > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > > +}
> > > +
> > > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_irq_postinstall(dev_priv);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_postinstall(dev_priv);
> > >
> > > gen8_gt_irq_postinstall(&dev_priv->gt);
> > > @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > gen8_master_intr_enable(dev_priv->uncore.regs);
> > > }
> > >
> > > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > -{
> > > - struct intel_uncore *uncore = &dev_priv->uncore;
> > > - u32 mask = SDE_GMBUS_ICP;
> > > -
> > > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > > -}
> > >
> > > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > --
> > > 2.29.2
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
>
> --
> Sincerely,
> Lyude Paul (she/her)
> Software Engineer at Red Hat
>
> Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
> asked me a question, are waiting for a review/merge on a patch, etc. and I
> haven't responded in a while, please feel free to send me another email to check
> on my status. I don't bite!
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 7:52 ` Imre Deak
0 siblings, 0 replies; 19+ messages in thread
From: Imre Deak @ 2021-02-17 7:52 UTC (permalink / raw)
To: Lyude Paul; +Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
On Tue, Feb 16, 2021 at 09:36:01PM -0500, Lyude Paul wrote:
> On Tue, 2021-02-16 at 20:08 +0200, Imre Deak wrote:
> > Hi,
> >
> > thanks for respinning this patchset, some comments below.
> >
> > On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> > > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > >
> > > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > > setup TGP PCH.
> > >
> > > v2:
> > > * Move Wa_14010685332 into it's own function - vsyrjala
> > > * Add TODO comment about figuring out if we can move this workaround - imre
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > Signed-off-by: Lyude Paul <lyude@redhat.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> > > 1 file changed, 36 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 98145a7f28a4..7d912aa950ee 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
> >
> > Maybe a better name is cnp_display_clock_wa.
> >
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > +
> > > + /*
> > > + * Wa_14010685332:cnp/cmp,tgp,adp
> >
> > Bspec says this WA applies ICL onwards and it's not PCH specific, for
> > instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
> > add a 'clarify platforms where this applies' todo item.
> >
> > > + * TODO: Figure out if this workaround can be applied in the s0ix
> > > suspend/resume handlers as
> > > + * on earlier platforms and whether the workaround is also needed
> > > for runtime suspend/resume
> > > + */
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> > > +}
> > > +
> > > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > > {
> > > struct intel_uncore *uncore = &dev_priv->uncore;
> > > @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private
> > > *dev_priv)
> > > GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > > GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > >
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >
> > It was mentioned already earlier, why is this check necessary and can't we
> > just call ibx_irq_reset() for all PCHs?
> >
> > > + GEN3_IRQ_RESET(uncore, SDE);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_reset(dev_priv);
> > > +
> > > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1))
> >
> > The check could be also moved to the helper.
> >
> > > + cnp_irq_post_reset(dev_priv);
> > > }
> > >
> > > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > GEN3_IRQ_RESET(uncore, SDE);
> > >
> > > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > > if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS, 0);
> > > - }
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1))
> > > + cnp_irq_post_reset(dev_priv);
> > > }
> > >
> > > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private
> > > *dev_priv)
> > > ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> > >
> > > spt_hpd_detection_setup(dev_priv);
> > > +
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_hpd_irq_setup(dev_priv);
> >
> > This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
> > setup done already earlier in this function and
> > spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
> > like for ICP+ we need to call icp_hpd_irq_setup() instead of
> > spt_hpd_irq_setup(), but haven't checked in detail.
>
> Could you please check :)? I don't work at Intel so you have far more access to
> this information then I do.
>
> FWIW the code -looks- mostly equivalent to me (SHOTPLUG_CTL_DDI and
> SHOTPLUG_CTL_TC seem to be equivalent registers to what's set in
> spt_hpd_irq_setup()), but the icelake point codepath enables an additional port,
> and changes an additional register called SHPD_FILTER_CNT.
The register definitions for SHOTPLUG_CTL_DDI wrt. PCH_PORT_HOTPLUG and
SHOTPLUG_CTL_TC wrt. PCH_PORT_HOTPLUG2 are different even though their
addresses match.
> I'll update it to use this in the next patch, but please definitely
> confirm this. I would very much like to avoid potentially breaking
> unrelated ICP systems with this.
>
> >
> > > }
> > >
> > > static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> > > @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > }
> > > }
> > >
> > > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > + u32 mask = SDE_GMBUS_ICP;
> > > +
> > > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > > +}
> > > +
> > > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_irq_postinstall(dev_priv);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_postinstall(dev_priv);
> > >
> > > gen8_gt_irq_postinstall(&dev_priv->gt);
> > > @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > gen8_master_intr_enable(dev_priv->uncore.regs);
> > > }
> > >
> > > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > -{
> > > - struct intel_uncore *uncore = &dev_priv->uncore;
> > > - u32 mask = SDE_GMBUS_ICP;
> > > -
> > > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > > -}
> > >
> > > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > --
> > > 2.29.2
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
>
> --
> Sincerely,
> Lyude Paul (she/her)
> Software Engineer at Red Hat
>
> Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
> asked me a question, are waiting for a review/merge on a patch, etc. and I
> haven't responded in a while, please feel free to send me another email to check
> on my status. I don't bite!
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 7:52 ` Imre Deak
0 siblings, 0 replies; 19+ messages in thread
From: Imre Deak @ 2021-02-17 7:52 UTC (permalink / raw)
To: Lyude Paul; +Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
On Tue, Feb 16, 2021 at 09:36:01PM -0500, Lyude Paul wrote:
> On Tue, 2021-02-16 at 20:08 +0200, Imre Deak wrote:
> > Hi,
> >
> > thanks for respinning this patchset, some comments below.
> >
> > On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> > > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > >
> > > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > > setup TGP PCH.
> > >
> > > v2:
> > > * Move Wa_14010685332 into it's own function - vsyrjala
> > > * Add TODO comment about figuring out if we can move this workaround - imre
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > Signed-off-by: Lyude Paul <lyude@redhat.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> > > 1 file changed, 36 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 98145a7f28a4..7d912aa950ee 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
> >
> > Maybe a better name is cnp_display_clock_wa.
> >
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > +
> > > + /*
> > > + * Wa_14010685332:cnp/cmp,tgp,adp
> >
> > Bspec says this WA applies ICL onwards and it's not PCH specific, for
> > instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
> > add a 'clarify platforms where this applies' todo item.
> >
> > > + * TODO: Figure out if this workaround can be applied in the s0ix
> > > suspend/resume handlers as
> > > + * on earlier platforms and whether the workaround is also needed
> > > for runtime suspend/resume
> > > + */
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> > > +}
> > > +
> > > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > > {
> > > struct intel_uncore *uncore = &dev_priv->uncore;
> > > @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private
> > > *dev_priv)
> > > GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > > GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > >
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >
> > It was mentioned already earlier, why is this check necessary and can't we
> > just call ibx_irq_reset() for all PCHs?
> >
> > > + GEN3_IRQ_RESET(uncore, SDE);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_reset(dev_priv);
> > > +
> > > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1))
> >
> > The check could be also moved to the helper.
> >
> > > + cnp_irq_post_reset(dev_priv);
> > > }
> > >
> > > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > GEN3_IRQ_RESET(uncore, SDE);
> > >
> > > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > > if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS, 0);
> > > - }
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1))
> > > + cnp_irq_post_reset(dev_priv);
> > > }
> > >
> > > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private
> > > *dev_priv)
> > > ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> > >
> > > spt_hpd_detection_setup(dev_priv);
> > > +
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_hpd_irq_setup(dev_priv);
> >
> > This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
> > setup done already earlier in this function and
> > spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
> > like for ICP+ we need to call icp_hpd_irq_setup() instead of
> > spt_hpd_irq_setup(), but haven't checked in detail.
>
> Could you please check :)? I don't work at Intel so you have far more access to
> this information then I do.
>
> FWIW the code -looks- mostly equivalent to me (SHOTPLUG_CTL_DDI and
> SHOTPLUG_CTL_TC seem to be equivalent registers to what's set in
> spt_hpd_irq_setup()), but the icelake point codepath enables an additional port,
> and changes an additional register called SHPD_FILTER_CNT.
The register definitions for SHOTPLUG_CTL_DDI wrt. PCH_PORT_HOTPLUG and
SHOTPLUG_CTL_TC wrt. PCH_PORT_HOTPLUG2 are different even though their
addresses match.
> I'll update it to use this in the next patch, but please definitely
> confirm this. I would very much like to avoid potentially breaking
> unrelated ICP systems with this.
>
> >
> > > }
> > >
> > > static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> > > @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > }
> > > }
> > >
> > > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > + u32 mask = SDE_GMBUS_ICP;
> > > +
> > > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > > +}
> > > +
> > > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_irq_postinstall(dev_priv);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_postinstall(dev_priv);
> > >
> > > gen8_gt_irq_postinstall(&dev_priv->gt);
> > > @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > gen8_master_intr_enable(dev_priv->uncore.regs);
> > > }
> > >
> > > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > -{
> > > - struct intel_uncore *uncore = &dev_priv->uncore;
> > > - u32 mask = SDE_GMBUS_ICP;
> > > -
> > > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > > -}
> > >
> > > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > --
> > > 2.29.2
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
>
> --
> Sincerely,
> Lyude Paul (she/her)
> Software Engineer at Red Hat
>
> Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
> asked me a question, are waiting for a review/merge on a patch, etc. and I
> haven't responded in a while, please feel free to send me another email to check
> on my status. I don't bite!
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2021-02-17 7:53 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-12 18:50 [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume Lyude Paul
2021-02-12 18:50 ` [Intel-gfx] " Lyude Paul
2021-02-12 18:50 ` Lyude Paul
2021-02-12 19:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev2) Patchwork
2021-02-12 21:04 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-02-12 23:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev3) Patchwork
2021-02-13 1:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-02-16 18:08 ` [Intel-gfx] [PATCH v2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume Imre Deak
2021-02-16 18:08 ` Imre Deak
2021-02-16 18:08 ` Imre Deak
2021-02-17 2:36 ` Lyude Paul
2021-02-17 2:36 ` Lyude Paul
2021-02-17 2:36 ` Lyude Paul
2021-02-17 2:37 ` Lyude Paul
2021-02-17 2:37 ` Lyude Paul
2021-02-17 2:37 ` Lyude Paul
2021-02-17 7:52 ` Imre Deak
2021-02-17 7:52 ` Imre Deak
2021-02-17 7:52 ` Imre Deak
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