[PATCH] drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x

[PATCH] drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x

[Alex Deucher]

Commit 098214999c8f added fetching of the AUX_DPHY register
values from the vbios, but it also changed the default values
in the case when there are no values in the vbios.  This causes
problems with displays with high refresh rates.  To fix this,
switch back to the original default value for AUX_DPHY_TX_CONTROL.

Fixes: 098214999c8f ("drm/amd/display: Read VBIOS Golden Settings Tbl")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1426
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Igor Kravchenko <Igor.Kravchenko@amd.com>
Cc: Aric Cyr <Aric.Cyr@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
index fa013496e26b..2f9bfaeaba8d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
@@ -341,8 +341,7 @@ void enc2_hw_init(struct link_encoder *enc)
 	} else {
 		AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
 
-		AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c4d);
-
+		AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
 	}
 
 	//AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
-- 
2.29.2

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Re: [PATCH] drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x

[Harry Wentland]

On 2021-02-16 12:28 p.m., Alex Deucher wrote:
> Commit 098214999c8f added fetching of the AUX_DPHY register
> values from the vbios, but it also changed the default values
> in the case when there are no values in the vbios.  This causes
> problems with displays with high refresh rates.  To fix this,
> switch back to the original default value for AUX_DPHY_TX_CONTROL.

I don't see how this impacts displays with high refresh rates 
specifically. This is a change that only affects our AUX pre-charge time 
and was provided to us by the HW team. It does depend on another 
register being programmed by the VBIOS/DMCUBFW at boot.

Before we revert this I would like confirmation that this is the root of 
the problem.

Harry

> 
> Fixes: 098214999c8f ("drm/amd/display: Read VBIOS Golden Settings Tbl")
> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1426
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> Cc: Igor Kravchenko <Igor.Kravchenko@amd.com>
> Cc: Aric Cyr <Aric.Cyr@amd.com>
> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
> ---
>   drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
> index fa013496e26b..2f9bfaeaba8d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
> @@ -341,8 +341,7 @@ void enc2_hw_init(struct link_encoder *enc)
>   	} else {
>   		AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
>   
> -		AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c4d);
> -
> +		AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
>   	}
>   
>   	//AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
> 
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Re: [PATCH] drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x

[Alex Deucher]

On Wed, Feb 17, 2021 at 11:53 AM Harry Wentland <harry.wentland@amd.com> wrote:
>
> On 2021-02-16 12:28 p.m., Alex Deucher wrote:
> > Commit 098214999c8f added fetching of the AUX_DPHY register
> > values from the vbios, but it also changed the default values
> > in the case when there are no values in the vbios.  This causes
> > problems with displays with high refresh rates.  To fix this,
> > switch back to the original default value for AUX_DPHY_TX_CONTROL.
>
> I don't see how this impacts displays with high refresh rates
> specifically. This is a change that only affects our AUX pre-charge time
> and was provided to us by the HW team. It does depend on another
> register being programmed by the VBIOS/DMCUBFW at boot.
>
> Before we revert this I would like confirmation that this is the root of
> the problem.

Hi Harry, any progress on this?

Thanks,

Alex


>
> Harry
>
> >
> > Fixes: 098214999c8f ("drm/amd/display: Read VBIOS Golden Settings Tbl")
> > Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1426
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > Cc: Igor Kravchenko <Igor.Kravchenko@amd.com>
> > Cc: Aric Cyr <Aric.Cyr@amd.com>
> > Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
> > ---
> >   drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c | 3 +--
> >   1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
> > index fa013496e26b..2f9bfaeaba8d 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
> > @@ -341,8 +341,7 @@ void enc2_hw_init(struct link_encoder *enc)
> >       } else {
> >               AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
> >
> > -             AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c4d);
> > -
> > +             AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
> >       }
> >
> >       //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
> >
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Re: [PATCH] drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x

[Alex Deucher]

On Wed, Feb 17, 2021 at 11:53 AM Harry Wentland <harry.wentland@amd.com> wrote:
>
> On 2021-02-16 12:28 p.m., Alex Deucher wrote:
> > Commit 098214999c8f added fetching of the AUX_DPHY register
> > values from the vbios, but it also changed the default values
> > in the case when there are no values in the vbios.  This causes
> > problems with displays with high refresh rates.  To fix this,
> > switch back to the original default value for AUX_DPHY_TX_CONTROL.
>
> I don't see how this impacts displays with high refresh rates
> specifically. This is a change that only affects our AUX pre-charge time
> and was provided to us by the HW team. It does depend on another
> register being programmed by the VBIOS/DMCUBFW at boot.
>
> Before we revert this I would like confirmation that this is the root of
> the problem.

Any updates on this?  Can we apply this in the meantime?

Thanks,

Alex

>
> Harry
>
> >
> > Fixes: 098214999c8f ("drm/amd/display: Read VBIOS Golden Settings Tbl")
> > Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1426
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > Cc: Igor Kravchenko <Igor.Kravchenko@amd.com>
> > Cc: Aric Cyr <Aric.Cyr@amd.com>
> > Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
> > ---
> >   drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c | 3 +--
> >   1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
> > index fa013496e26b..2f9bfaeaba8d 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
> > @@ -341,8 +341,7 @@ void enc2_hw_init(struct link_encoder *enc)
> >       } else {
> >               AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
> >
> > -             AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c4d);
> > -
> > +             AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
> >       }
> >
> >       //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
> >
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Re: [PATCH] drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x

[Harry Wentland]

On 2021-03-11 9:22 a.m., Alex Deucher wrote:
> On Wed, Feb 17, 2021 at 11:53 AM Harry Wentland <harry.wentland@amd.com> wrote:
>>
>> On 2021-02-16 12:28 p.m., Alex Deucher wrote:
>>> Commit 098214999c8f added fetching of the AUX_DPHY register
>>> values from the vbios, but it also changed the default values
>>> in the case when there are no values in the vbios.  This causes
>>> problems with displays with high refresh rates.  To fix this,
>>> switch back to the original default value for AUX_DPHY_TX_CONTROL.
>>
>> I don't see how this impacts displays with high refresh rates
>> specifically. This is a change that only affects our AUX pre-charge time
>> and was provided to us by the HW team. It does depend on another
>> register being programmed by the VBIOS/DMCUBFW at boot.
>>
>> Before we revert this I would like confirmation that this is the root of
>> the problem.
> 
> Any updates on this?  Can we apply this in the meantime?
> 

Sorry for the late response.

Looks like the other two patches I had were flaky, though I don't fully 
understand why. Let's just revert this change for NV1x (i.e. your change).

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> Thanks,
> 
> Alex
> 
>>
>> Harry
>>
>>>
>>> Fixes: 098214999c8f ("drm/amd/display: Read VBIOS Golden Settings Tbl")
>>> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1426>>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>> Cc: Igor Kravchenko <Igor.Kravchenko@amd.com>
>>> Cc: Aric Cyr <Aric.Cyr@amd.com>
>>> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
>>> ---
>>>    drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c | 3 +--
>>>    1 file changed, 1 insertion(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
>>> index fa013496e26b..2f9bfaeaba8d 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
>>> @@ -341,8 +341,7 @@ void enc2_hw_init(struct link_encoder *enc)
>>>        } else {
>>>                AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
>>>
>>> -             AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c4d);
>>> -
>>> +             AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
>>>        }
>>>
>>>        //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
>>>

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