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From: Like Xu <like.xu@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Borislav Petkov <bp@alien8.de>,
	Kan Liang <kan.liang@linux.intel.com>,
	x86@kernel.org, linux-kernel@vger.kernel.org,
	Like Xu <like.xu@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>
Subject: [PATCH v4 RESEND 2/5] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers
Date: Mon, 22 Mar 2021 14:06:32 +0800	[thread overview]
Message-ID: <20210322060635.821531-3-like.xu@linux.intel.com> (raw)
In-Reply-To: <20210322060635.821531-1-like.xu@linux.intel.com>

If the platform supports LBR_INFO register, the x86_pmu.lbr_info will
be assigned in intel_pmu_?_lbr_init_?() and it's safe to expose LBR_INFO
in the x86_perf_get_lbr() directly, instead of relying on lbr_format check.

Also Architectural LBR has IA32_LBR_x_INFO instead of LBR_FORMAT_INFO_x
to hold metadata for the operation, including mispredict, TSX, and
elapsed cycle time information.

Signed-off-by: Like Xu <like.xu@linux.intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
---
 arch/x86/events/intel/lbr.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 21890dacfcfe..355ea70f1879 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1832,12 +1832,10 @@ void __init intel_pmu_arch_lbr_init(void)
  */
 int x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
 {
-	int lbr_fmt = x86_pmu.intel_cap.lbr_format;
-
 	lbr->nr = x86_pmu.lbr_nr;
 	lbr->from = x86_pmu.lbr_from;
 	lbr->to = x86_pmu.lbr_to;
-	lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0;
+	lbr->info = x86_pmu.lbr_info;
 
 	return 0;
 }
-- 
2.29.2


  parent reply	other threads:[~2021-03-22  6:15 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-22  6:06 [PATCH v4 RESEND 0/5] x86: The perf/x86 changes to support guest Arch LBR Like Xu
2021-03-22  6:06 ` [PATCH v4 RESEND 1/5] perf/x86/intel: Fix the comment about guest LBR support on KVM Like Xu
2021-03-22  6:06 ` Like Xu [this message]
2021-03-23 21:38   ` [PATCH v4 RESEND 2/5] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Peter Zijlstra
2021-03-24  2:02     ` Like Xu
2021-03-22  6:06 ` [PATCH v4 RESEND 3/5] perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region Like Xu
2021-03-23 20:56   ` Liang, Kan
2021-03-23 21:41   ` Peter Zijlstra
2021-03-23 23:03     ` Liang, Kan
2021-03-24  1:32   ` Namhyung Kim
2021-03-24  3:46     ` Like Xu
2021-03-24  4:04       ` Namhyung Kim
2021-03-24  5:42         ` Like Xu
2021-03-22  6:06 ` [PATCH v4 RESEND 4/5] perf/x86/lbr: Skip checking for the existence of LBR_TOS for Arch LBR Like Xu
2021-03-23 21:49   ` Peter Zijlstra
2021-03-24  3:32     ` Like Xu
2021-03-22  6:06 ` [PATCH v4 RESEND 5/5] perf/x86: Move ARCH_LBR_CTL_MASK definition to include/asm/msr-index.h Like Xu

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