* [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc
@ 2021-04-07 7:12 Stefan Roese
2021-04-07 7:12 ` [PATCH v1 01/15] mips: octeon: Move CVMX_SYNC from octeon_ddr.h to cvmx-regs.h Stefan Roese
` (15 more replies)
0 siblings, 16 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
This patchset adds the following updates / fixes for Marvell MIPS Octeon:
- MIPS Octeon NIC23 base support
- Add serial_octeon_pcie_console to support the Marvell remote tool
"oct-remote-console"
- Add serial_octeon_bootcmd to support the Marvell remote tools
"oct-remote-load" & "oct-remote-bootcmd"
- Fix AHCI driver to support big-endian platforms
- Misc minor updates & fixes to the MIPS Octeon platform code
- EBB7304: Enable USB storage support
- EBB7304: Add I2C support (devices & commands)
This patchset requires the MIPS Octeon serdes & PCIe patchset which was
posted to the list 2020-12-11.
Thanks,
Stefan
Aaron Williams (2):
mips: octeon: dts/dtsi: Change UART DT node to use clocks property
mips: octeon: ebb7304: Add support for some I2C devices
Stefan Roese (13):
mips: octeon: Move CVMX_SYNC from octeon_ddr.h to cvmx-regs.h
mips: octeon: cvmx-bootmem: Fix compare in "if" statement
mips: octeon: cvmx-coremask.h: Fix cvmx_coremask_dprint() with DEBUG
defined
serial: serial_octeon_pcie_console.c: Add PCI remote console support
serial: serial_octeon_bootcmd.c: Add PCI remote console support
mips: octeon: cpu.c: Add arch_misc_init() for pci-console &
pci-bootcmd
mips: octeon: cpu.c: Enable AHCI/SATA support
sata: ahci_mvebu.c: Enable AHCI/SATA driver for MIPS Octeon
ata: ahci: Fix usage on big-endian platforms
scsi: Add ata_swap_buf_le16() to support big-endian platforms
mips: octeon: mrvl,cn73xx.dtsi: Add AHCI/SATA DT node
mips: octeon: Add Octeon III NIC23 board support
mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support
arch/mips/dts/Makefile | 1 +
arch/mips/dts/mrvl,cn73xx.dtsi | 21 +
arch/mips/dts/mrvl,octeon-ebb7304.dts | 15 +-
arch/mips/dts/mrvl,octeon-nic23.dts | 162 ++++++++
arch/mips/mach-octeon/Kconfig | 7 +
arch/mips/mach-octeon/cpu.c | 348 ++++++++++++++++-
arch/mips/mach-octeon/cvmx-bootmem.c | 4 +-
.../mach-octeon/include/mach/cvmx-coremask.h | 5 +-
.../mips/mach-octeon/include/mach/cvmx-regs.h | 1 +
.../mach-octeon/include/mach/octeon_ddr.h | 2 -
board/Marvell/octeon_nic23/Kconfig | 19 +
board/Marvell/octeon_nic23/MAINTAINERS | 7 +
board/Marvell/octeon_nic23/Makefile | 8 +
board/Marvell/octeon_nic23/board.c | 106 +++++
board/Marvell/octeon_nic23/board_ddr.h | 269 +++++++++++++
configs/octeon_ebb7304_defconfig | 9 +-
configs/octeon_nic23_defconfig | 70 ++++
drivers/ata/Kconfig | 2 +-
drivers/ata/ahci.c | 23 +-
drivers/ata/ahci_mvebu.c | 3 +-
drivers/scsi/scsi.c | 6 +
drivers/serial/Kconfig | 24 ++
drivers/serial/Makefile | 2 +
drivers/serial/serial_octeon_bootcmd.c | 182 +++++++++
drivers/serial/serial_octeon_pcie_console.c | 365 ++++++++++++++++++
include/configs/octeon_nic23.h | 21 +
26 files changed, 1656 insertions(+), 26 deletions(-)
create mode 100644 arch/mips/dts/mrvl,octeon-nic23.dts
create mode 100644 board/Marvell/octeon_nic23/Kconfig
create mode 100644 board/Marvell/octeon_nic23/MAINTAINERS
create mode 100644 board/Marvell/octeon_nic23/Makefile
create mode 100644 board/Marvell/octeon_nic23/board.c
create mode 100644 board/Marvell/octeon_nic23/board_ddr.h
create mode 100644 configs/octeon_nic23_defconfig
create mode 100644 drivers/serial/serial_octeon_bootcmd.c
create mode 100644 drivers/serial/serial_octeon_pcie_console.c
create mode 100644 include/configs/octeon_nic23.h
--
2.31.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v1 01/15] mips: octeon: Move CVMX_SYNC from octeon_ddr.h to cvmx-regs.h
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 02/15] mips: octeon: cvmx-bootmem: Fix compare in "if" statement Stefan Roese
` (14 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
This makes is easier to use this macro from non-DDR related files.
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/mips/mach-octeon/include/mach/cvmx-regs.h | 1 +
arch/mips/mach-octeon/include/mach/octeon_ddr.h | 2 --
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-regs.h b/arch/mips/mach-octeon/include/mach/cvmx-regs.h
index 56528bc1bfde..9e86be8f6342 100644
--- a/arch/mips/mach-octeon/include/mach/cvmx-regs.h
+++ b/arch/mips/mach-octeon/include/mach/cvmx-regs.h
@@ -68,6 +68,7 @@
#define CVMX_POP(result, input) \
asm("pop %[rd],%[rs]" : [rd] "=d"(result) : [rs] "d"(input))
+#define CVMX_SYNC asm volatile("sync\n" : : : "memory")
#define CVMX_SYNCW asm volatile("syncw\nsyncw\n" : : : "memory")
#define CVMX_SYNCS asm volatile("syncs\n" : : : "memory")
#define CVMX_SYNCWS asm volatile("syncws\n" : : : "memory")
diff --git a/arch/mips/mach-octeon/include/mach/octeon_ddr.h b/arch/mips/mach-octeon/include/mach/octeon_ddr.h
index 97e7b554ff78..0b5be06daab9 100644
--- a/arch/mips/mach-octeon/include/mach/octeon_ddr.h
+++ b/arch/mips/mach-octeon/include/mach/octeon_ddr.h
@@ -120,8 +120,6 @@ static inline int ddr_verbose(void)
#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
#define CVMX_TMP_STR2(x) #x
-#define CVMX_SYNC asm volatile ("sync" : : : "memory")
-
#define CVMX_CACHE(op, address, offset) \
asm volatile ("cache " CVMX_TMP_STR(op) ", " \
CVMX_TMP_STR(offset) "(%[rbase])" \
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 02/15] mips: octeon: cvmx-bootmem: Fix compare in "if" statement
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
2021-04-07 7:12 ` [PATCH v1 01/15] mips: octeon: Move CVMX_SYNC from octeon_ddr.h to cvmx-regs.h Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 03/15] mips: octeon: cvmx-coremask.h: Fix cvmx_coremask_dprint() with DEBUG defined Stefan Roese
` (13 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
While porting from the Marvell source, I introduced a bug by misplacing
the parenthesis. This patch fixes this issue.
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/mips/mach-octeon/cvmx-bootmem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mach-octeon/cvmx-bootmem.c b/arch/mips/mach-octeon/cvmx-bootmem.c
index 4b10effefb7d..12695df9bca6 100644
--- a/arch/mips/mach-octeon/cvmx-bootmem.c
+++ b/arch/mips/mach-octeon/cvmx-bootmem.c
@@ -283,8 +283,8 @@ static int __cvmx_bootmem_check_version(int exact_match)
int major_version;
major_version = CVMX_BOOTMEM_DESC_GET_FIELD(major_version);
- if (major_version > 3 ||
- (exact_match && major_version) != exact_match) {
+ if ((major_version > 3) ||
+ (exact_match && major_version != exact_match)) {
debug("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: 0x%llx\n",
major_version,
(int)CVMX_BOOTMEM_DESC_GET_FIELD(minor_version),
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 03/15] mips: octeon: cvmx-coremask.h: Fix cvmx_coremask_dprint() with DEBUG defined
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
2021-04-07 7:12 ` [PATCH v1 01/15] mips: octeon: Move CVMX_SYNC from octeon_ddr.h to cvmx-regs.h Stefan Roese
2021-04-07 7:12 ` [PATCH v1 02/15] mips: octeon: cvmx-bootmem: Fix compare in "if" statement Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 04/15] serial: serial_octeon_pcie_console.c: Add PCI remote console support Stefan Roese
` (12 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
As DEBUG is no Kconfig symbol, we can't use the IS_ENABLED() macros.
This patch switches to the unfortunately necessary #ifdef usage again
to make it work correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/mips/mach-octeon/include/mach/cvmx-coremask.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-coremask.h b/arch/mips/mach-octeon/include/mach/cvmx-coremask.h
index c34ff46d3afe..314b6d9789a5 100644
--- a/arch/mips/mach-octeon/include/mach/cvmx-coremask.h
+++ b/arch/mips/mach-octeon/include/mach/cvmx-coremask.h
@@ -741,8 +741,9 @@ void cvmx_coremask_print(const struct cvmx_coremask *pcm);
static inline void cvmx_coremask_dprint(const struct cvmx_coremask *pcm)
{
- if (IS_ENABLED(DEBUG))
- cvmx_coremask_print(pcm);
+#if defined(DEBUG)
+ cvmx_coremask_print(pcm);
+#endif
}
struct cvmx_coremask *octeon_get_available_coremask(struct cvmx_coremask *pcm);
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 04/15] serial: serial_octeon_pcie_console.c: Add PCI remote console support
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (2 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 03/15] mips: octeon: cvmx-coremask.h: Fix cvmx_coremask_dprint() with DEBUG defined Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 05/15] serial: serial_octeon_bootcmd.c: " Stefan Roese
` (11 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
This patch adds the PCI remote console feature for MIPS Octeon, which
will be used by the upcoming Octeon III NIC23 board support. It enables
the use of the "oct-remote-console" tool on host PC's to communicate
with the PCIe target.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
drivers/serial/Kconfig | 13 +
drivers/serial/Makefile | 1 +
drivers/serial/serial_octeon_pcie_console.c | 365 ++++++++++++++++++++
3 files changed, 379 insertions(+)
create mode 100644 drivers/serial/serial_octeon_pcie_console.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 24413d14f9ce..d6fe1dc7b1a8 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -788,6 +788,19 @@ config MSM_SERIAL
for example APQ8016 and MSM8916.
Single baudrate is supported in current implementation (115200).
+config OCTEON_SERIAL_PCIE_CONSOLE
+ bool "MIPS Octeon PCIe remote console"
+ depends on ARCH_OCTEON
+ depends on (DM_SERIAL && DM_STDIO)
+ select SYS_STDIO_DEREGISTER
+ select SYS_CONSOLE_IS_IN_ENV
+ select CONSOLE_MUX
+ help
+ This driver supports remote console over the PCIe bus when the
+ Octeon is running in PCIe target mode. The host program
+ 'oct-remote-console' can be used to connect to this console.
+ The console number will likely be 0 or 1.
+
config OMAP_SERIAL
bool "Support for OMAP specific UART"
depends on DM_SERIAL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 92bcb30b8509..4900e9cb27dc 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
+obj-$(CONFIG_OCTEON_SERIAL_PCIE_CONSOLE) += serial_octeon_pcie_console.o
obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o
diff --git a/drivers/serial/serial_octeon_pcie_console.c b/drivers/serial/serial_octeon_pcie_console.c
new file mode 100644
index 000000000000..c76e787d0308
--- /dev/null
+++ b/drivers/serial/serial_octeon_pcie_console.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ * Copyright (C) 2021 Stefan Roese <sr@denx.de>
+ */
+
+#include <dm.h>
+#include <dm/uclass.h>
+#include <errno.h>
+#include <input.h>
+#include <iomux.h>
+#include <log.h>
+#include <serial.h>
+#include <stdio_dev.h>
+#include <string.h>
+#include <watchdog.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <mach/cvmx-regs.h>
+#include <mach/cvmx-bootmem.h>
+
+#define DRIVER_NAME "pci-console"
+#define OCTEONTX_PCIE_CONSOLE_NAME_LEN 16
+
+/* Current versions */
+#define OCTEON_PCIE_CONSOLE_MAJOR_VERSION 1
+#define OCTEON_PCIE_CONSOLE_MINOR_VERSION 0
+
+#define OCTEON_PCIE_CONSOLE_BLOCK_NAME "__pci_console"
+
+/*
+ * Structure that defines a single console.
+ * Note: when read_index == write_index, the buffer is empty.
+ * The actual usable size of each console is console_buf_size -1;
+ */
+struct octeon_pcie_console {
+ u64 input_base_addr;
+ u32 input_read_index;
+ u32 input_write_index;
+ u64 output_base_addr;
+ u32 output_read_index;
+ u32 output_write_index;
+ u32 lock;
+ u32 buf_size;
+};
+
+/*
+ * This is the main container structure that contains all the information
+ * about all PCI consoles. The address of this structure is passed to various
+ * routines that operation on PCI consoles.
+ */
+struct octeon_pcie_console_desc {
+ u32 major_version;
+ u32 minor_version;
+ u32 lock;
+ u32 flags;
+ u32 num_consoles;
+ u32 pad;
+ /* must be 64 bit aligned here... */
+ /* Array of addresses of octeon_pcie_console_t structures */
+ u64 console_addr_array[0];
+ /* Implicit storage for console_addr_array */
+};
+
+struct octeon_pcie_console_priv {
+ struct octeon_pcie_console *console;
+ int console_num;
+ bool console_active;
+};
+
+/* Flag definitions for read/write functions */
+enum {
+ /*
+ * If set, read/write functions won't block waiting for space or data.
+ * For reads, 0 bytes may be read, and for writes not all of the
+ * supplied data may be written.
+ */
+ OCT_PCI_CON_FLAG_NONBLOCK = 1 << 0,
+};
+
+static int buffer_free_bytes(u32 buffer_size, u32 wr_idx, u32 rd_idx)
+{
+ if (rd_idx >= buffer_size || wr_idx >= buffer_size)
+ return -1;
+
+ return ((buffer_size - 1) - (wr_idx - rd_idx)) % buffer_size;
+}
+
+static int buffer_avail_bytes(u32 buffer_size, u32 wr_idx, u32 rd_idx)
+{
+ if (rd_idx >= buffer_size || wr_idx >= buffer_size)
+ return -1;
+
+ return buffer_size - 1 - buffer_free_bytes(buffer_size, wr_idx, rd_idx);
+}
+
+static int buffer_read_avail(struct udevice *dev, unsigned int console_num)
+{
+ struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
+ struct octeon_pcie_console *cons_ptr = priv->console;
+ int avail;
+
+ avail = buffer_avail_bytes(cons_ptr->buf_size,
+ cons_ptr->input_write_index,
+ cons_ptr->input_read_index);
+ if (avail >= 0)
+ return avail;
+
+ return 0;
+}
+
+static int octeon_pcie_console_read(struct udevice *dev,
+ unsigned int console_num, char *buffer,
+ int buffer_size, u32 flags)
+{
+ struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
+ struct octeon_pcie_console *cons_ptr = priv->console;
+ int avail;
+ char *buf_ptr;
+ int bytes_read;
+ int read_size;
+
+ buf_ptr = (char *)cvmx_phys_to_ptr(cons_ptr->input_base_addr);
+
+ avail = buffer_avail_bytes(cons_ptr->buf_size,
+ cons_ptr->input_write_index,
+ cons_ptr->input_read_index);
+ if (avail < 0)
+ return avail;
+
+ if (!(flags & OCT_PCI_CON_FLAG_NONBLOCK)) {
+ /* Wait for some data to be available */
+ while (0 == (avail = buffer_avail_bytes(cons_ptr->buf_size,
+ cons_ptr->input_write_index,
+ cons_ptr->input_read_index))) {
+ mdelay(10);
+ WATCHDOG_RESET();
+ }
+ }
+
+ bytes_read = 0;
+
+ /* Don't overflow the buffer passed to us */
+ read_size = min_t(int, avail, buffer_size);
+
+ /* Limit ourselves to what we can input in a contiguous block */
+ if (cons_ptr->input_read_index + read_size >= cons_ptr->buf_size)
+ read_size = cons_ptr->buf_size - cons_ptr->input_read_index;
+
+ memcpy(buffer, buf_ptr + cons_ptr->input_read_index, read_size);
+ cons_ptr->input_read_index =
+ (cons_ptr->input_read_index + read_size) % cons_ptr->buf_size;
+ bytes_read += read_size;
+
+ /* Mark the PCIe console to be active from now on */
+ if (bytes_read)
+ priv->console_active = true;
+
+ return bytes_read;
+}
+
+static int octeon_pcie_console_write(struct udevice *dev,
+ unsigned int console_num,
+ const char *buffer,
+ int bytes_to_write, u32 flags)
+{
+ struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
+ struct octeon_pcie_console *cons_ptr = priv->console;
+ int avail;
+ char *buf_ptr;
+ int bytes_written;
+
+ buf_ptr = (char *)cvmx_phys_to_ptr(cons_ptr->output_base_addr);
+ bytes_written = 0;
+ while (bytes_to_write > 0) {
+ avail = buffer_free_bytes(cons_ptr->buf_size,
+ cons_ptr->output_write_index,
+ cons_ptr->output_read_index);
+
+ if (avail > 0) {
+ int write_size = min_t(int, avail, bytes_to_write);
+
+ /*
+ * Limit ourselves to what we can output in a contiguous
+ * block
+ */
+ if (cons_ptr->output_write_index + write_size >=
+ cons_ptr->buf_size) {
+ write_size = cons_ptr->buf_size -
+ cons_ptr->output_write_index;
+ }
+
+ memcpy(buf_ptr + cons_ptr->output_write_index,
+ buffer + bytes_written, write_size);
+ /*
+ * Make sure data is visible before changing write
+ * index
+ */
+ CVMX_SYNCW;
+ cons_ptr->output_write_index =
+ (cons_ptr->output_write_index + write_size) %
+ cons_ptr->buf_size;
+ bytes_to_write -= write_size;
+ bytes_written += write_size;
+ } else if (avail == 0) {
+ /*
+ * Check to see if we should wait for room, or return
+ * after a partial write
+ */
+ if (flags & OCT_PCI_CON_FLAG_NONBLOCK)
+ goto done;
+
+ WATCHDOG_RESET();
+ mdelay(10); /* Delay if we are spinning */
+ } else {
+ bytes_written = -1;
+ goto done;
+ }
+ }
+
+done:
+ return bytes_written;
+}
+
+static struct octeon_pcie_console_desc *octeon_pcie_console_init(int num_consoles,
+ int buffer_size)
+{
+ struct octeon_pcie_console_desc *cons_desc_ptr;
+ struct octeon_pcie_console *cons_ptr;
+ s64 addr;
+ u64 avail_addr;
+ int alloc_size;
+ int i;
+
+ /* Compute size required for pci console structure */
+ alloc_size = num_consoles *
+ (buffer_size * 2 + sizeof(struct octeon_pcie_console) +
+ sizeof(u64)) + sizeof(struct octeon_pcie_console_desc);
+
+ /*
+ * Allocate memory for the consoles. This must be in the range
+ * addresssible by the bootloader.
+ * Try to do so in a manner which minimizes fragmentation. We try to
+ * put it at the top of DDR0 or bottom of DDR2 first, and only do
+ * generic allocation if those fail
+ */
+ addr = cvmx_bootmem_phy_named_block_alloc(alloc_size,
+ OCTEON_DDR0_SIZE - alloc_size - 128,
+ OCTEON_DDR0_SIZE, 128,
+ OCTEON_PCIE_CONSOLE_BLOCK_NAME,
+ CVMX_BOOTMEM_FLAG_END_ALLOC);
+ if (addr < 0) {
+ addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0,
+ 0x1fffffff, 128,
+ OCTEON_PCIE_CONSOLE_BLOCK_NAME,
+ CVMX_BOOTMEM_FLAG_END_ALLOC);
+ }
+ if (addr < 0)
+ return 0;
+
+ cons_desc_ptr = cvmx_phys_to_ptr(addr);
+
+ /* Clear entire alloc'ed memory */
+ memset(cons_desc_ptr, 0, alloc_size);
+
+ /* Initialize as locked until we are done */
+ cons_desc_ptr->lock = 1;
+ CVMX_SYNCW;
+ cons_desc_ptr->num_consoles = num_consoles;
+ cons_desc_ptr->flags = 0;
+ cons_desc_ptr->major_version = OCTEON_PCIE_CONSOLE_MAJOR_VERSION;
+ cons_desc_ptr->minor_version = OCTEON_PCIE_CONSOLE_MINOR_VERSION;
+
+ avail_addr = addr + sizeof(struct octeon_pcie_console_desc) +
+ num_consoles * sizeof(u64);
+
+ for (i = 0; i < num_consoles; i++) {
+ cons_desc_ptr->console_addr_array[i] = avail_addr;
+ cons_ptr = (void *)cons_desc_ptr->console_addr_array[i];
+ avail_addr += sizeof(struct octeon_pcie_console);
+ cons_ptr->input_base_addr = avail_addr;
+ avail_addr += buffer_size;
+ cons_ptr->output_base_addr = avail_addr;
+ avail_addr += buffer_size;
+ cons_ptr->buf_size = buffer_size;
+ }
+ CVMX_SYNCW;
+ cons_desc_ptr->lock = 0;
+
+ return cvmx_phys_to_ptr(addr);
+}
+
+static int octeon_pcie_console_getc(struct udevice *dev)
+{
+ char c;
+
+ octeon_pcie_console_read(dev, 0, &c, 1, 0);
+ return c;
+}
+
+static int octeon_pcie_console_putc(struct udevice *dev, const char c)
+{
+ struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
+
+ if (priv->console_active)
+ octeon_pcie_console_write(dev, 0, (char *)&c, 1, 0);
+
+ return 0;
+}
+
+static int octeon_pcie_console_pending(struct udevice *dev, bool input)
+{
+ if (input) {
+ udelay(100);
+ return buffer_read_avail(dev, 0) > 0;
+ }
+
+ return 0;
+}
+
+static const struct dm_serial_ops octeon_pcie_console_ops = {
+ .getc = octeon_pcie_console_getc,
+ .putc = octeon_pcie_console_putc,
+ .pending = octeon_pcie_console_pending,
+};
+
+static int octeon_pcie_console_probe(struct udevice *dev)
+{
+ struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
+ struct octeon_pcie_console_desc *cons_desc;
+ int console_count;
+ int console_size;
+ int console_num;
+
+ /*
+ * Currently only 1 console is supported. Perhaps we need to add
+ * a console nexus if more than one needs to be supported.
+ */
+ console_count = 1;
+ console_size = 1024;
+ console_num = 0;
+
+ cons_desc = octeon_pcie_console_init(console_count, console_size);
+ priv->console =
+ cvmx_phys_to_ptr(cons_desc->console_addr_array[console_num]);
+
+ debug("PCI console init succeeded, %d consoles, %d bytes each\n",
+ console_count, console_size);
+
+ return 0;
+}
+
+static const struct udevice_id octeon_pcie_console_serial_id[] = {
+ { .compatible = "marvell,pci-console", },
+ { },
+};
+
+U_BOOT_DRIVER(octeon_pcie_console) = {
+ .name = DRIVER_NAME,
+ .id = UCLASS_SERIAL,
+ .ops = &octeon_pcie_console_ops,
+ .of_match = of_match_ptr(octeon_pcie_console_serial_id),
+ .probe = octeon_pcie_console_probe,
+ .priv_auto = sizeof(struct octeon_pcie_console_priv),
+};
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 05/15] serial: serial_octeon_bootcmd.c: Add PCI remote console support
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (3 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 04/15] serial: serial_octeon_pcie_console.c: Add PCI remote console support Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 06/15] mips: octeon: cpu.c: Add arch_misc_init() for pci-console & pci-bootcmd Stefan Roese
` (10 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
This patch adds the PCI bootcmd feature for MIPS Octeon, which will be
used by the upcoming Octeon III NIC23 board support. It enables the use
of the "oct-remote-load" and "oct-remote-bootcmd" on host PC's to
communicate with the PCIe target and load images into the onboard
memory and issue commands.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
drivers/serial/Kconfig | 11 ++
drivers/serial/Makefile | 1 +
drivers/serial/serial_octeon_bootcmd.c | 182 +++++++++++++++++++++++++
3 files changed, 194 insertions(+)
create mode 100644 drivers/serial/serial_octeon_bootcmd.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index d6fe1dc7b1a8..782bc61bbb8a 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -788,6 +788,17 @@ config MSM_SERIAL
for example APQ8016 and MSM8916.
Single baudrate is supported in current implementation (115200).
+config OCTEON_SERIAL_BOOTCMD
+ bool "MIPS Octeon PCI remote bootcmd input"
+ depends on ARCH_OCTEON
+ depends on DM_SERIAL
+ select SYS_IS_IN_ENV
+ select CONSOLE_MUX
+ help
+ This driver supports remote input over the PCIe bus from a host
+ to U-Boot for entering commands. It is utilized by the host
+ commands 'oct-remote-load' and 'oct-remote-bootcmd'.
+
config OCTEON_SERIAL_PCIE_CONSOLE
bool "MIPS Octeon PCIe remote console"
depends on ARCH_OCTEON
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 4900e9cb27dc..6c0fdca5861e 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
+obj-$(CONFIG_OCTEON_SERIAL_BOOTCMD) += serial_octeon_bootcmd.o
obj-$(CONFIG_OCTEON_SERIAL_PCIE_CONSOLE) += serial_octeon_pcie_console.o
obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
diff --git a/drivers/serial/serial_octeon_bootcmd.c b/drivers/serial/serial_octeon_bootcmd.c
new file mode 100644
index 000000000000..4bcff77eb887
--- /dev/null
+++ b/drivers/serial/serial_octeon_bootcmd.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ * Copyright (C) 2021 Stefan Roese <sr@denx.de>
+ */
+
+#include <dm.h>
+#include <dm/uclass.h>
+#include <errno.h>
+#include <input.h>
+#include <iomux.h>
+#include <log.h>
+#include <serial.h>
+#include <stdio_dev.h>
+#include <string.h>
+#include <watchdog.h>
+#include <linux/delay.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <mach/cvmx-regs.h>
+#include <mach/cvmx-bootmem.h>
+
+#define DRIVER_NAME "pci-bootcmd"
+
+/*
+ * Important:
+ * This address cannot be changed as the PCI console tool relies on exactly
+ * this value!
+ */
+#define BOOTLOADER_PCI_READ_BUFFER_BASE 0x6c000
+#define BOOTLOADER_PCI_READ_BUFFER_SIZE 256
+#define BOOTLOADER_PCI_WRITE_BUFFER_SIZE 256
+
+#define BOOTLOADER_PCI_READ_BUFFER_STR_LEN \
+ (BOOTLOADER_PCI_READ_BUFFER_SIZE - 8)
+#define BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN \
+ (BOOTLOADER_PCI_WRITE_BUFFER_SIZE - 8)
+
+#define BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR \
+ (BOOTLOADER_PCI_READ_BUFFER_BASE + 0)
+#define BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR \
+ (BOOTLOADER_PCI_READ_BUFFER_BASE + 4)
+#define BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR \
+ (BOOTLOADER_PCI_READ_BUFFER_BASE + 8)
+
+enum octeon_pci_io_buf_owner {
+ /* Must be zero, set when memory cleared */
+ OCTEON_PCI_IO_BUF_OWNER_INVALID = 0,
+ OCTEON_PCI_IO_BUF_OWNER_OCTEON = 1,
+ OCTEON_PCI_IO_BUF_OWNER_HOST = 2,
+};
+
+/* Structure for bootloader PCI IO buffers */
+struct octeon_pci_io_buf {
+ u32 owner;
+ u32 len;
+ char data[0];
+};
+
+struct octeon_bootcmd_priv {
+ bool started;
+ int copy_offset;
+ bool eol;
+ bool unlocked;
+ struct octeon_pci_io_buf *buf;
+};
+
+static int octeon_bootcmd_pending(struct udevice *dev, bool input)
+{
+ struct octeon_bootcmd_priv *priv = dev_get_priv(dev);
+
+ if (!input)
+ return 0;
+
+ if (priv->eol)
+ return 1;
+
+ CVMX_SYNC;
+ if (priv->buf->owner != OCTEON_PCI_IO_BUF_OWNER_OCTEON)
+ return 0;
+
+ if (priv->buf->len > priv->copy_offset &&
+ (priv->buf->data[priv->copy_offset] != '\0'))
+ return 1;
+
+ return 0;
+}
+
+static int octeon_bootcmd_getc(struct udevice *dev)
+{
+ struct octeon_bootcmd_priv *priv = dev_get_priv(dev);
+ char c;
+
+ /* There's no EOL for boot commands so we fake it. */
+ if (priv->eol) {
+ priv->eol = false;
+ return '\n';
+ }
+
+ while (!octeon_bootcmd_pending(dev, true)) {
+ WATCHDOG_RESET();
+ /*
+ * ToDo:
+ * The original code calls octeon_board_poll() here. We may
+ * need to implement something similar here.
+ */
+ udelay(100);
+ }
+
+ c = priv->buf->data[priv->copy_offset];
+ priv->buf->data[priv->copy_offset++] = '\0';
+
+ if (priv->copy_offset >= min_t(int, CONFIG_SYS_CBSIZE - 1,
+ BOOTLOADER_PCI_READ_BUFFER_STR_LEN - 1) ||
+ (priv->buf->data[priv->copy_offset] == '\0')) {
+ priv->copy_offset = 0;
+ priv->buf->len = 0;
+ priv->buf->owner = OCTEON_PCI_IO_BUF_OWNER_HOST;
+ priv->eol = true;
+ CVMX_SYNC;
+ }
+
+ return c;
+}
+
+static const struct dm_serial_ops octeon_bootcmd_ops = {
+ .getc = octeon_bootcmd_getc,
+ .pending = octeon_bootcmd_pending,
+};
+
+static int octeon_bootcmd_probe(struct udevice *dev)
+{
+ struct octeon_bootcmd_priv *priv = dev_get_priv(dev);
+
+ priv->buf = (void *)CKSEG0ADDR(BOOTLOADER_PCI_READ_BUFFER_BASE);
+ memset(priv->buf, 0, BOOTLOADER_PCI_READ_BUFFER_SIZE);
+ priv->eol = false;
+
+ /*
+ * When the bootcmd console is first started it is started as locked to
+ * block any calls sending a command until U-Boot is ready to accept
+ * commands. Just before the main loop starts to accept commands the
+ * bootcmd console is unlocked.
+ */
+ if (priv->unlocked)
+ priv->buf->owner = OCTEON_PCI_IO_BUF_OWNER_HOST;
+ else
+ priv->buf->owner = OCTEON_PCI_IO_BUF_OWNER_OCTEON;
+
+ debug("%s called, buffer ptr: 0x%p, owner: %s\n", __func__,
+ priv->buf,
+ priv->buf->owner == OCTEON_PCI_IO_BUF_OWNER_HOST ?
+ "host" : "octeon");
+ debug("&priv->copy_offset: 0x%p\n", &priv->copy_offset);
+ CVMX_SYNC;
+
+ /*
+ * Perhaps reinvestige this: In the original code, "unlocked" etc
+ * is set in the octeon_pci_bootcmd_unlock() function called very
+ * late.
+ */
+ priv->buf->owner = OCTEON_PCI_IO_BUF_OWNER_HOST;
+ priv->unlocked = true;
+ priv->started = true;
+ CVMX_SYNC;
+
+ return 0;
+}
+
+static const struct udevice_id octeon_bootcmd_serial_id[] = {
+ { .compatible = "marvell,pci-bootcmd", },
+ { },
+};
+
+U_BOOT_DRIVER(octeon_bootcmd) = {
+ .name = DRIVER_NAME,
+ .id = UCLASS_SERIAL,
+ .ops = &octeon_bootcmd_ops,
+ .of_match = of_match_ptr(octeon_bootcmd_serial_id),
+ .probe = octeon_bootcmd_probe,
+ .priv_auto = sizeof(struct octeon_bootcmd_priv),
+};
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 06/15] mips: octeon: cpu.c: Add arch_misc_init() for pci-console & pci-bootcmd
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (4 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 05/15] serial: serial_octeon_bootcmd.c: " Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 07/15] mips: octeon: cpu.c: Enable AHCI/SATA support Stefan Roese
` (9 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
This patch adds the necessary platform infrastructure code, so that the
MIPS Octeon drivers "serial_octeon_pcie_console" & "serial_bootcmd" can
be used. This is e.g. the bootmem initialization in a compatible way to
the Marvell 2013 U-Boot, so that the exisiting PC remote tools like
"oct-remote-console" & "oct-remote-load" can be used. This is be done in
the newly introduced arch_misc_init(), which calls the necessary init
functions when enabled.
These patches are in preparation for the MIPS Octeon NIC23 board
support, which is a desktop PCIe target board enabling these features.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
arch/mips/mach-octeon/cpu.c | 327 ++++++++++++++++++++++++++++++++++++
1 file changed, 327 insertions(+)
diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c
index 6f87a4ef8cbb..3fde9fbc4708 100644
--- a/arch/mips/mach-octeon/cpu.c
+++ b/arch/mips/mach-octeon/cpu.c
@@ -3,6 +3,10 @@
* Copyright (C) 2020 Marvell International Ltd.
*/
+#include <dm.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <iomux.h>
#include <asm/global_data.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
@@ -10,9 +14,24 @@
#include <linux/io.h>
#include <mach/clock.h>
#include <mach/cavm-reg.h>
+#include <mach/cvmx-bootmem.h>
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Important:
+ * This address cannot be changed as the PCI console tool relies on exactly
+ * this value!
+ */
+#define BOOTLOADER_BOOTMEM_DESC_ADDR 0x6c100
+#define BOOTLOADER_BOOTMEM_DESC_SPACE (BOOTLOADER_BOOTMEM_DESC_ADDR + 0x8)
+
+#define OCTEON_RESERVED_LOW_BOOT_MEM_SIZE (1024 * 1024)
+
+#define BOOTCMD_NAME "pci-bootcmd"
+#define CONSOLE_NAME "pci-console at 0"
+#define OCTEON_BOOTLOADER_LOAD_MEM_NAME "__tmp_load"
+
/*
* TRUE for devices having registers with little-endian byte
* order, FALSE for registers with native-endian byte order.
@@ -85,3 +104,311 @@ int print_cpuinfo(void)
return 0;
}
+
+static int octeon_bootmem_init(void)
+{
+ int ret;
+
+ /* Call old single-node func: it uses only gd->ram_size */
+ ret = cvmx_bootmem_phy_mem_list_init(gd->ram_size,
+ OCTEON_RESERVED_LOW_BOOT_MEM_SIZE,
+ (void *)CKSEG0ADDR(BOOTLOADER_BOOTMEM_DESC_SPACE));
+ if (!ret) {
+ printf("FATAL: Error initializing bootmem list\n");
+ return -ENOSPC;
+ }
+
+ /*
+ * Put bootmem descriptor address in known location for host.
+ * Make sure it is not in kseg0, as we want physical address
+ */
+ writeq((u64)__cvmx_bootmem_internal_get_desc_ptr() & 0x7fffffffull,
+ (void *)CKSEG0ADDR(BOOTLOADER_BOOTMEM_DESC_ADDR));
+
+ debug("Reserving first 1MB of memory\n");
+ ret = cvmx_bootmem_reserve_memory(0, OCTEON_RESERVED_LOW_BOOT_MEM_SIZE,
+ "__low_reserved", 0);
+ if (!ret)
+ puts("Error reserving low 1MB of memory\n");
+
+#ifdef DEBUG
+ cvmx_bootmem_phy_list_print();
+#endif
+
+ return 0;
+}
+
+static int octeon_configure_load_memory(void)
+{
+ char *eptr;
+ u32 addr;
+ u32 size;
+ int ret;
+
+ eptr = env_get("octeon_reserved_mem_load_size");
+ if (!eptr || !strcmp("auto", eptr)) {
+ /*
+ * Pick a size that we think is appropriate.
+ * Please note that for small memory boards this guess
+ * will likely not be ideal.
+ * Please pick a specific size for boards/applications
+ * that require it.
+ */
+ if (gd->ram_size <= (256 << 20)) {
+ size = min_t(u64, (128 << 20),
+ ((gd->ram_size * 2) / 5) & ~0xFFFFF);
+ } else {
+ size = min_t(u64, (256 << 20),
+ ((gd->ram_size - (256 << 20)) / 3) & ~0xFFFFF);
+ }
+ } else {
+ size = simple_strtol(eptr, NULL, 16);
+ debug("octeon_reserved_mem_load_size=0x%08x\n", size);
+ }
+
+ if (size) {
+ debug("Linux reserved load size 0x%08x\n", size);
+ eptr = env_get("octeon_reserved_mem_load_base");
+ if (!eptr || !strcmp("auto", eptr)) {
+ u64 mem_top;
+ /*
+ * Leave some room for previous allocations that
+ * are made starting@the top of the low
+ * 256 Mbytes of DRAM
+ */
+ int adjust = (1 << 20);
+
+ if (gd->ram_size <= (512 << 20))
+ adjust = (17 << 20);
+
+ /* Put block@the top of DDR0, or bottom of DDR2 */
+ if ((gd->ram_size <= (256 << 20)) ||
+ (size > (gd->ram_size - (256 << 20)))) {
+ mem_top = min_t(u64, gd->ram_size - adjust,
+ (256 << 20) - adjust);
+ } else if ((gd->ram_size <= (512 << 20)) ||
+ (size > (gd->ram_size - (512 << 20)))) {
+ mem_top = min_t(u64, gd->ram_size - adjust,
+ (512 << 20) - adjust);
+ } else {
+ /*
+ * We have enough room, so set
+ * mem_top so that the block is
+ *@the base of the DDR2
+ * segment
+ */
+ mem_top = (512 << 20) + size;
+ }
+
+ /*
+ * Adjust for boot bus memory hole on OCTEON II
+ * and later.
+ */
+ if ((gd->ram_size > (256 << 20)))
+ mem_top += (256 << 20);
+
+ debug("Adjusted memory top is 0x%llx\n", mem_top);
+ addr = mem_top - size;
+ if (addr > (512 << 20))
+ addr = (512 << 20);
+ if ((addr >= (256 << 20)) && addr < (512 << 20)) {
+ /*
+ * The address landed in the boot-bus
+ * memory hole. Dig it out of the hole.
+ */
+ addr = (512 << 20);
+ }
+ } else {
+ addr = simple_strtol(eptr, NULL, 16);
+ }
+
+ ret = cvmx_bootmem_phy_named_block_alloc(size, addr,
+ addr + size, 0,
+ OCTEON_BOOTLOADER_LOAD_MEM_NAME,
+ 0);
+ if (ret < 0) {
+ printf("ERROR: Unable to allocate bootloader reserved memory (addr: 0x%x, size: 0x%x).\n",
+ addr, size);
+ } else {
+ /*
+ * Set default load address to base of memory
+ * reserved for loading. The setting of the
+ * env. variable also sets the load_addr global
+ * variable.
+ * This environment variable is overridden each
+ * boot if a reserved block is created.
+ */
+ char str[20];
+
+ snprintf(str, sizeof(str), "0x%x", addr);
+ env_set("loadaddr", str);
+ debug("Setting load address to 0x%08x, size 0x%x\n",
+ addr, size);
+ }
+ return 0;
+ }
+
+ printf("WARNING: No reserved memory for image loading.\n");
+ return -1;
+}
+
+static int init_pcie_console(void)
+{
+ char *stdinname = env_get("stdin");
+ char *stdoutname = env_get("stdout");
+ char *stderrname = env_get("stderr");
+ struct udevice *pcie_console_dev = NULL;
+ bool stdin_set, stdout_set, stderr_set;
+ char iomux_name[128];
+ int ret = 0;
+
+ debug("%s: stdin: %s, stdout: %s, stderr: %s\n", __func__, stdinname,
+ stdoutname, stderrname);
+ if (!stdinname) {
+ env_set("stdin", "serial");
+ stdinname = env_get("stdin");
+ }
+ if (!stdoutname) {
+ env_set("stdout", "serial");
+ stdoutname = env_get("stdout");
+ }
+ if (!stderrname) {
+ env_set("stderr", "serial");
+ stderrname = env_get("stderr");
+ }
+
+ if (!stdinname || !stdoutname || !stderrname) {
+ printf("%s: Error setting environment variables for serial\n",
+ __func__);
+ return -1;
+ }
+
+ stdin_set = !!strstr(stdinname, CONSOLE_NAME);
+ stdout_set = !!strstr(stdoutname, CONSOLE_NAME);
+ stderr_set = !!strstr(stderrname, CONSOLE_NAME);
+
+ log_debug("stdin: %d, \"%s\", stdout: %d, \"%s\", stderr: %d, \"%s\"\n",
+ stdin_set, stdinname, stdout_set, stdoutname,
+ stderr_set, stderrname);
+ ret = uclass_get_device_by_name(UCLASS_SERIAL, CONSOLE_NAME,
+ &pcie_console_dev);
+ if (ret || !pcie_console_dev) {
+ debug("%s: No PCI console device %s found\n", __func__,
+ CONSOLE_NAME);
+ return 0;
+ }
+
+ if (stdin_set)
+ strncpy(iomux_name, stdinname, sizeof(iomux_name));
+ else
+ snprintf(iomux_name, sizeof(iomux_name), "%s,%s",
+ stdinname, pcie_console_dev->name);
+
+ ret = iomux_doenv(stdin, iomux_name);
+ if (ret) {
+ log_err("%s: Error setting I/O stdin MUX to %s\n",
+ __func__, iomux_name);
+ return ret;
+ }
+
+ if (!stdin_set)
+ env_set("stdin", iomux_name);
+
+ if (stdout_set)
+ strncpy(iomux_name, stdoutname, sizeof(iomux_name));
+ else
+ snprintf(iomux_name, sizeof(iomux_name), "%s,%s", stdoutname,
+ pcie_console_dev->name);
+
+ ret = iomux_doenv(stdout, iomux_name);
+ if (ret) {
+ log_err("%s: Error setting I/O stdout MUX to %s\n",
+ __func__, iomux_name);
+ return ret;
+ }
+ if (!stdout_set)
+ env_set("stdout", iomux_name);
+
+ if (stderr_set)
+ strncpy(iomux_name, stderrname, sizeof(iomux_name));
+ else
+ snprintf(iomux_name, sizeof(iomux_name), "%s,%s", stderrname,
+ pcie_console_dev->name);
+
+ ret = iomux_doenv(stderr, iomux_name);
+ if (ret) {
+ log_err("%s: Error setting I/O stderr MUX to %s\n",
+ __func__, iomux_name);
+ return ret;
+ }
+
+ if (!stderr_set)
+ env_set("stderr", iomux_name);
+
+ debug("%s: stdin: %s, stdout: %s, stderr: %s, ret: %d\n",
+ __func__, env_get("stdin"), env_get("stdout"),
+ env_get("stderr"), ret);
+
+ return ret;
+}
+
+static int init_bootcmd_console(void)
+{
+ char *stdinname = env_get("stdin");
+ struct udevice *bootcmd_dev = NULL;
+ bool stdin_set;
+ char iomux_name[128];
+ int ret = 0;
+
+ debug("%s: stdin before: %s\n", __func__,
+ stdinname ? stdinname : "NONE");
+ if (!stdinname) {
+ env_set("stdin", "serial");
+ stdinname = env_get("stdin");
+ }
+ stdin_set = !!strstr(stdinname, BOOTCMD_NAME);
+ ret = uclass_get_device_by_driver(UCLASS_SERIAL,
+ DM_DRIVER_GET(octeon_bootcmd),
+ &bootcmd_dev);
+ if (ret) {
+ log_err("%s: Error getting %s serial class\n", __func__,
+ BOOTCMD_NAME);
+ } else if (bootcmd_dev) {
+ if (stdin_set)
+ strncpy(iomux_name, stdinname, sizeof(iomux_name));
+ else
+ snprintf(iomux_name, sizeof(iomux_name), "%s,%s",
+ stdinname, bootcmd_dev->name);
+ ret = iomux_doenv(stdin, iomux_name);
+ if (ret)
+ log_err("%s: Error %d enabling the PCI bootcmd input console \"%s\"\n",
+ __func__, ret, iomux_name);
+ if (!stdin_set)
+ env_set("stdin", iomux_name);
+ }
+
+ debug("%s: Set iomux and stdin to %s (ret: %d)\n",
+ __func__, iomux_name, ret);
+ return ret;
+}
+
+int arch_misc_init(void)
+{
+ int ret;
+
+ ret = octeon_bootmem_init();
+ if (ret)
+ return ret;
+
+ ret = octeon_configure_load_memory();
+ if (ret)
+ return ret;
+
+ if (CONFIG_IS_ENABLED(OCTEON_SERIAL_PCIE_CONSOLE))
+ init_pcie_console();
+
+ if (CONFIG_IS_ENABLED(OCTEON_SERIAL_BOOTCMD))
+ init_bootcmd_console();
+
+ return 0;
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 07/15] mips: octeon: cpu.c: Enable AHCI/SATA support
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (5 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 06/15] mips: octeon: cpu.c: Add arch_misc_init() for pci-console & pci-bootcmd Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 08/15] sata: ahci_mvebu.c: Enable AHCI/SATA driver for MIPS Octeon Stefan Roese
` (8 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
For easy AHCI/ SATA integration, this patch adds board_ahci_enable()
for the MVEBU AHCI driver, which will be used by this platform. This
platform specific "enable" function will setup the proper endian
swapping in the AHCI controller so that it can be used by the common
AHCI code.
Additionally the endian swizzle entry for AHCI in
octeon_should_swizzle_table[] is removed, as this enabled the original
lowlevel code function, e.g. octeon_configure_qlm(), for the QLM setup
to work correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
arch/mips/mach-octeon/cpu.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c
index 3fde9fbc4708..f56beb896414 100644
--- a/arch/mips/mach-octeon/cpu.c
+++ b/arch/mips/mach-octeon/cpu.c
@@ -15,6 +15,8 @@
#include <mach/clock.h>
#include <mach/cavm-reg.h>
#include <mach/cvmx-bootmem.h>
+#include <mach/cvmx-regs.h>
+#include <mach/cvmx-sata-defs.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -49,7 +51,6 @@ const bool octeon_should_swizzle_table[256] = {
[0x1e] = true, /* PCI mmio window */
[0x68] = true, /* OCTEON III USB */
[0x69] = true, /* OCTEON III USB */
- [0x6c] = true, /* OCTEON III SATA */
[0x6f] = true, /* OCTEON II USB */
};
@@ -412,3 +413,21 @@ int arch_misc_init(void)
return 0;
}
+
+int board_ahci_enable(void)
+{
+ cvmx_sata_uctl_shim_cfg_t shim_cfg;
+
+ /*
+ * Configure proper endian swapping for the AHCI port so that the
+ * common AHCI code can be used
+ */
+ shim_cfg.u64 = csr_rd(CVMX_SATA_UCTL_SHIM_CFG);
+ shim_cfg.s.dma_endian_mode = 1;
+ /* Use 1 for LE mode when running BE, or 3 for BE mode running BE */
+ shim_cfg.s.csr_endian_mode = 3; /* Don't byte swap */
+ shim_cfg.s.dma_read_cmd = 1; /* No allocate L2C */
+ csr_wr(CVMX_SATA_UCTL_SHIM_CFG, shim_cfg.u64);
+
+ return 0;
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 08/15] sata: ahci_mvebu.c: Enable AHCI/SATA driver for MIPS Octeon
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (6 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 07/15] mips: octeon: cpu.c: Enable AHCI/SATA support Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 09/15] ata: ahci: Fix usage on big-endian platforms Stefan Roese
` (7 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
This patch enables the usage of the MVEBU AHCI/SATA driver. The only
changes necessary to support MIPS Octeon via DT based probing are, to
add the compatible DT property and the use of dev_remap_addr() so that
the correct mapped address is used in the Octeon case (phys != virt).
Please note that this driver supports the usage of the "scsi" command
and not the "sata" command, since it does not provide an own "scan"
function, which is needed for the "sata" cmd support.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
drivers/ata/Kconfig | 2 +-
drivers/ata/ahci_mvebu.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index f2f8275aeca8..6e47964cdc8f 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -121,7 +121,7 @@ config SUNXI_AHCI
config AHCI_MVEBU
bool "Marvell EBU AHCI SATA support"
- depends on ARCH_MVEBU
+ depends on ARCH_MVEBU || ARCH_OCTEON
depends on AHCI
select SCSI_AHCI
select DM_SCSI
diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c
index 7d82d2ea3fff..f05150d61ddf 100644
--- a/drivers/ata/ahci_mvebu.c
+++ b/drivers/ata/ahci_mvebu.c
@@ -39,7 +39,7 @@ static int mvebu_ahci_probe(struct udevice *dev)
*/
board_ahci_enable();
- ahci_probe_scsi(dev, dev_read_addr(dev));
+ ahci_probe_scsi(dev, (ulong)dev_remap_addr(dev));
return 0;
}
@@ -48,6 +48,7 @@ static const struct udevice_id mvebu_ahci_ids[] = {
{ .compatible = "marvell,armada-380-ahci" },
{ .compatible = "marvell,armada-3700-ahci" },
{ .compatible = "marvell,armada-8k-ahci" },
+ { .compatible = "cavium,octeon-7130-ahci" },
{ }
};
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 09/15] ata: ahci: Fix usage on big-endian platforms
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (7 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 08/15] sata: ahci_mvebu.c: Enable AHCI/SATA driver for MIPS Octeon Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 10/15] scsi: Add ata_swap_buf_le16() to support " Stefan Roese
` (6 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
This patch adds a few missing virt_to_phys() to use the correct physical
address for DMA operations in the common AHCI code. This is done to
support the big-endian MIPS Octeon platform.
Additionally the code a cleaned up a bit (remove some empty lines) and
made a bit better readable.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
drivers/ata/ahci.c | 23 +++++++++++------------
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 2ef21ec508a2..81d0e367264c 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -500,6 +500,7 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
{
struct ahci_ioports *pp = &(uc_priv->port[port]);
struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
+ phys_addr_t pa = virt_to_phys(buf);
u32 sg_count;
int i;
@@ -510,9 +511,6 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
}
for (i = 0; i < sg_count; i++) {
- /* We assume virt=phys */
- phys_addr_t pa = (unsigned long)buf + i * MAX_DATA_BYTE_COUNT;
-
ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) {
@@ -520,25 +518,26 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
return -1;
}
ahci_sg->flags_size = cpu_to_le32(0x3fffff &
- (buf_len < MAX_DATA_BYTE_COUNT
- ? (buf_len - 1)
- : (MAX_DATA_BYTE_COUNT - 1)));
+ (buf_len < MAX_DATA_BYTE_COUNT ?
+ (buf_len - 1) :
+ (MAX_DATA_BYTE_COUNT - 1)));
ahci_sg++;
buf_len -= MAX_DATA_BYTE_COUNT;
+ pa += MAX_DATA_BYTE_COUNT;
}
return sg_count;
}
-
static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
{
+ phys_addr_t pa = virt_to_phys((void *)pp->cmd_tbl);
+
pp->cmd_slot->opts = cpu_to_le32(opts);
pp->cmd_slot->status = 0;
- pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
+ pp->cmd_slot->tbl_addr = cpu_to_le32(lower_32_bits(pa));
#ifdef CONFIG_PHYS_64BIT
- pp->cmd_slot->tbl_addr_hi =
- cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
+ pp->cmd_slot->tbl_addr_hi = cpu_to_le32(upper_32_bits(pa));
#endif
}
@@ -674,12 +673,12 @@ static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
ahci_dcache_invalidate_range((unsigned long)buf,
(unsigned long)buf_len);
- debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
+ debug("%s: %d byte transferred.\n", __func__,
+ le32_to_cpu(pp->cmd_slot->status));
return 0;
}
-
static char *ata_id_strcpy(u16 *target, u16 *src, int len)
{
int i;
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 10/15] scsi: Add ata_swap_buf_le16() to support big-endian platforms
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (8 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 09/15] ata: ahci: Fix usage on big-endian platforms Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 11/15] mips: octeon: mrvl, cn73xx.dtsi: Add AHCI/SATA DT node Stefan Roese
` (5 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
Otherwise the output will look like this on MIPS Octeon NIC23:
Device 0: (0:0) Vendor: ATA Prod.: aSDnsi klUrt aII Rev: 4X11
Type: Hard Disk
Capacity: 457862.8 MB = 447.1 GB (937703088 x 512)
instead of this version:
Device 0: (0:0) Vendor: TA Prod.: SanDisk Ultra II Rev: X411
Type: Hard Disk
Capacity: 457862.8 MB = 447.1 GB (937703088 x 512)
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
drivers/scsi/scsi.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 738948449053..ce69750c7ff0 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -9,6 +9,7 @@
#include <bootstage.h>
#include <dm.h>
#include <env.h>
+#include <libata.h>
#include <log.h>
#include <part.h>
#include <pci.h>
@@ -594,6 +595,11 @@ static int do_scsi_scan_one(struct udevice *dev, int id, int lun, bool verbose)
memcpy(&bdesc->vendor, &bd.vendor, sizeof(bd.vendor));
memcpy(&bdesc->product, &bd.product, sizeof(bd.product));
memcpy(&bdesc->revision, &bd.revision, sizeof(bd.revision));
+ if (IS_ENABLED(CONFIG_SYS_BIG_ENDIAN)) {
+ ata_swap_buf_le16((u16 *)&bdesc->vendor, sizeof(bd.vendor) / 2);
+ ata_swap_buf_le16((u16 *)&bdesc->product, sizeof(bd.product) / 2);
+ ata_swap_buf_le16((u16 *)&bdesc->revision, sizeof(bd.revision) / 2);
+ }
if (verbose) {
printf(" Device %d: ", bdesc->devnum);
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 11/15] mips: octeon: mrvl, cn73xx.dtsi: Add AHCI/SATA DT node
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (9 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 10/15] scsi: Add ata_swap_buf_le16() to support " Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 12/15] mips: octeon: Add Octeon III NIC23 board support Stefan Roese
` (4 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
Add the AHCI compatible SATA DT node to the Octeon CN73xx dtsi file.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
arch/mips/dts/mrvl,cn73xx.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
index 9f3dc615d66d..83e5cde044a7 100644
--- a/arch/mips/dts/mrvl,cn73xx.dtsi
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -246,5 +246,24 @@
0x02000000 0x00000000 0xe0000000 0x00011b00 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
0x43000000 0x00011c00 0x00000000 0x00011c00 0x00000000 0x00000010 0x00000000>;/* prefetchable memory */
};
+
+ uctl at 118006c000000 {
+ compatible = "cavium,octeon-7130-sata-uctl", "simple-bus";
+ reg = <0x11800 0x6c000000 0x0 0x100>;
+ ranges; /* Direct mapping */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ portmap = <0x3>;
+ staggered-spinup;
+ cavium,qlm-trim = "4,sata";
+
+ sata: sata at 16c0000000000 {
+ compatible = "cavium,octeon-7130-ahci";
+ reg = <0x16c00 0x00000000 0x0 0x200>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupts = <0x6c010 4>;
+ };
+ };
};
};
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 12/15] mips: octeon: Add Octeon III NIC23 board support
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (10 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 11/15] mips: octeon: mrvl, cn73xx.dtsi: Add AHCI/SATA DT node Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 13/15] mips: octeon: dts/dtsi: Change UART DT node to use clocks property Stefan Roese
` (3 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
This patch adds the basic support for the PCIe target board equipped
with the Octeon III CN2350 SoC.
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/mips/dts/Makefile | 1 +
arch/mips/dts/mrvl,octeon-nic23.dts | 162 +++++++++++++++
arch/mips/mach-octeon/Kconfig | 7 +
board/Marvell/octeon_nic23/Kconfig | 19 ++
board/Marvell/octeon_nic23/MAINTAINERS | 7 +
board/Marvell/octeon_nic23/Makefile | 8 +
board/Marvell/octeon_nic23/board.c | 106 ++++++++++
board/Marvell/octeon_nic23/board_ddr.h | 269 +++++++++++++++++++++++++
configs/octeon_nic23_defconfig | 70 +++++++
include/configs/octeon_nic23.h | 21 ++
10 files changed, 670 insertions(+)
create mode 100644 arch/mips/dts/mrvl,octeon-nic23.dts
create mode 100644 board/Marvell/octeon_nic23/Kconfig
create mode 100644 board/Marvell/octeon_nic23/MAINTAINERS
create mode 100644 board/Marvell/octeon_nic23/Makefile
create mode 100644 board/Marvell/octeon_nic23/board.c
create mode 100644 board/Marvell/octeon_nic23/board_ddr.h
create mode 100644 configs/octeon_nic23_defconfig
create mode 100644 include/configs/octeon_nic23.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 7c429231340c..215283cfa05b 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -20,6 +20,7 @@ dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb
dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb
+dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb
dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f at st1704.dtb
diff --git a/arch/mips/dts/mrvl,octeon-nic23.dts b/arch/mips/dts/mrvl,octeon-nic23.dts
new file mode 100644
index 000000000000..72ef56d834e4
--- /dev/null
+++ b/arch/mips/dts/mrvl,octeon-nic23.dts
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell / Cavium Inc. NIC23
+ */
+
+/dts-v1/;
+
+#include "mrvl,cn73xx.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "cavium,nic23";
+ compatible = "cavium,nic23";
+
+ aliases {
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ spi0 = &spi;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Power on GPIO 8, active high */
+ reg_mmc_3v3: regulator at 0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "mmc-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&bootbus {
+ /*
+ * bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000)
+ * as the initial size is too small for the 8MiB flash device
+ */
+ ranges = <0 0 0 0x1f400000 0xc00000>,
+ <1 0 0x10000 0x10000000 0>,
+ <2 0 0x10000 0x20000000 0>,
+ <3 0 0x10000 0x30000000 0>,
+ <4 0 0 0x1d020000 0x10000>,
+ <5 0 0x10000 0x50000000 0>,
+ <6 0 0x10000 0x60000000 0>,
+ <7 0 0x10000 0x70000000 0>;
+
+ cavium,cs-config at 0 {
+ compatible = "cavium,octeon-3860-bootbus-config";
+ cavium,cs-index = <0>;
+ cavium,t-adr = <10>;
+ cavium,t-ce = <50>;
+ cavium,t-oe = <50>;
+ cavium,t-we = <35>;
+ cavium,t-rd-hld = <25>;
+ cavium,t-wr-hld = <35>;
+ cavium,t-pause = <0>;
+ cavium,t-wait = <50>;
+ cavium,t-page = <30>;
+ cavium,t-rd-dly = <0>;
+ cavium,page-mode = <1>;
+ cavium,pages = <8>;
+ cavium,bus-width = <8>;
+ };
+
+ cavium,cs-config at 4 {
+ compatible = "cavium,octeon-3860-bootbus-config";
+ cavium,cs-index = <4>;
+ cavium,t-adr = <10>;
+ cavium,t-ce = <10>;
+ cavium,t-oe = <160>;
+ cavium,t-we = <100>;
+ cavium,t-rd-hld = <10>;
+ cavium,t-wr-hld = <0>;
+ cavium,t-pause = <50>;
+ cavium,t-wait = <50>;
+ cavium,t-page = <10>;
+ cavium,t-rd-dly = <10>;
+ cavium,pages = <0>;
+ cavium,bus-width = <8>;
+ };
+
+ flash0: nor at 0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition at 0 {
+ label = "bootloader";
+ reg = <0 0x340000>;
+ read-only;
+ };
+ partition at 300000 {
+ label = "storage";
+ reg = <0x340000 0x4be000>;
+ };
+ partition at 7fe000 {
+ label = "environment";
+ reg = <0x7fe000 0x2000>;
+ read-only;
+ };
+ };
+};
+
+&uart0 {
+ clock-frequency = <800000000>;
+};
+
+&i2c0 {
+ u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
+ clock-frequency = <100000>;
+};
+
+&i2c1 {
+ u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
+ clock-frequency = <100000>;
+};
+
+&mmc {
+ status = "okay";
+
+ mmc0: mmc-slot at 0 {
+ compatible = "cavium,octeon-6130-mmc-slot", "mmc-slot";
+ reg = <0>;
+ vqmmc-supply = <®_mmc_3v3>;
+ voltage-ranges = <3300 3300>;
+ spi-max-frequency = <52000000>;
+ /* bus width can be 1, 4 or 8 */
+ bus-width = <8>; /* new std property */
+ cavium,bus-max-width = <8>; /* custom property */
+ non-removable;
+ };
+};
+
+&soc0 {
+ pci-console at 0 {
+ compatible = "marvell,pci-console";
+ status = "okay";
+ };
+
+ pci-bootcmd at 0 {
+ compatible = "marvell,pci-bootcmd";
+ status = "okay";
+ };
+};
+
+&spi {
+ flash at 0 {
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
+ spi-max-frequency = <2000000>;
+ reg = <0>;
+ };
+};
diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig
index d69408cc2753..624039df2536 100644
--- a/arch/mips/mach-octeon/Kconfig
+++ b/arch/mips/mach-octeon/Kconfig
@@ -41,6 +41,12 @@ config TARGET_OCTEON_EBB7304
help
Choose this for the Octeon EBB7304 board
+config TARGET_OCTEON_NIC23
+ bool "Marvell Octeon NIC23"
+ select OCTEON_CN73XX
+ help
+ Choose this for the Octeon NIC23 board
+
endchoice
config SYS_DCACHE_SIZE
@@ -60,5 +66,6 @@ config SYS_PCI_64BIT
default y
source "board/Marvell/octeon_ebb7304/Kconfig"
+source "board/Marvell/octeon_nic23/Kconfig"
endmenu
diff --git a/board/Marvell/octeon_nic23/Kconfig b/board/Marvell/octeon_nic23/Kconfig
new file mode 100644
index 000000000000..3c42e8acdadc
--- /dev/null
+++ b/board/Marvell/octeon_nic23/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_OCTEON_NIC23
+
+config SYS_BOARD
+ string
+ default "octeon_nic23"
+
+config SYS_VENDOR
+ string
+ default "Marvell"
+
+config SYS_CONFIG_NAME
+ string
+ default "octeon_nic23"
+
+config DEFAULT_DEVICE_TREE
+ string
+ default "mrvl,octeon-nic23"
+
+endif
diff --git a/board/Marvell/octeon_nic23/MAINTAINERS b/board/Marvell/octeon_nic23/MAINTAINERS
new file mode 100644
index 000000000000..cd5148dcfee9
--- /dev/null
+++ b/board/Marvell/octeon_nic23/MAINTAINERS
@@ -0,0 +1,7 @@
+OCTEON_NIC23 BOARD
+M: Aaron Williams <awilliams@marvell.com>
+S: Maintained
+F: board/Marvell/octeon_nic23/*
+F: configs/octeon_nic23_defconfig
+F: include/configs/octeon_nic23.h
+F: arch/mips/dts/mrvl,octeon-nic23.dts
diff --git a/board/Marvell/octeon_nic23/Makefile b/board/Marvell/octeon_nic23/Makefile
new file mode 100644
index 000000000000..a79b94ec6f1b
--- /dev/null
+++ b/board/Marvell/octeon_nic23/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2021 Stefan Roese <sr@denx.de>
+# Copyright (C) 2019-2020 Marvell International Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
diff --git a/board/Marvell/octeon_nic23/board.c b/board/Marvell/octeon_nic23/board.c
new file mode 100644
index 000000000000..9f5eb2e2a182
--- /dev/null
+++ b/board/Marvell/octeon_nic23/board.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Stefan Roese <sr@denx.de>
+ */
+
+#include <dm.h>
+#include <ram.h>
+
+#include <mach/octeon_ddr.h>
+#include <mach/cvmx-qlm.h>
+#include <mach/octeon_qlm.h>
+#include <mach/octeon_fdt.h>
+#include <mach/cvmx-helper.h>
+#include <mach/cvmx-helper-cfg.h>
+#include <mach/cvmx-helper-util.h>
+#include <mach/cvmx-bgxx-defs.h>
+
+#include "board_ddr.h"
+
+#define NIC23_DEF_DRAM_FREQ 800
+
+static u8 octeon_nic23_cfg0_spd_values[512] = {
+ OCTEON_NIC23_CFG0_SPD_VALUES
+};
+
+static struct ddr_conf board_ddr_conf[] = {
+ OCTEON_NIC23_DDR_CONFIGURATION
+};
+
+struct ddr_conf *octeon_ddr_conf_table_get(int *count, int *def_ddr_freq)
+{
+ *count = ARRAY_SIZE(board_ddr_conf);
+ *def_ddr_freq = NIC23_DEF_DRAM_FREQ;
+
+ return board_ddr_conf;
+}
+
+int board_fix_fdt(void *fdt)
+{
+ u32 range_data[5 * 8];
+ bool rev4;
+ int node;
+ int rc;
+
+ /*
+ * ToDo:
+ * Read rev4 info from EEPROM or where the original U-Boot does
+ * and don't hard-code it here.
+ */
+ rev4 = true;
+
+ debug("%s() rev4: %s\n", __func__, rev4 ? "true" : "false");
+ /* Patch the PHY configuration based on board revision */
+ rc = octeon_fdt_patch_rename(fdt,
+ rev4 ? "4,nor-flash" : "4,no-nor-flash",
+ "cavium,board-trim", false, NULL, NULL);
+ if (!rev4) {
+ /* Modify the ranges for CS 0 */
+ node = fdt_node_offset_by_compatible(fdt, -1,
+ "cavium,octeon-3860-bootbus");
+ if (node < 0) {
+ printf("%s: Error: cannot find boot bus in device tree!\n",
+ __func__);
+ return -1;
+ }
+
+ rc = fdtdec_get_int_array(fdt, node, "ranges",
+ range_data, 5 * 8);
+ if (rc) {
+ printf("%s: Error reading ranges from boot bus FDT\n",
+ __func__);
+ return -1;
+ }
+ range_data[2] = cpu_to_fdt32(0x10000);
+ range_data[3] = 0;
+ range_data[4] = 0;
+ rc = fdt_setprop(fdt, node, "ranges", range_data,
+ sizeof(range_data));
+ if (rc) {
+ printf("%s: Error updating boot bus ranges in fdt\n",
+ __func__);
+ }
+ }
+ return rc;
+}
+
+void board_configure_qlms(void)
+{
+ octeon_configure_qlm(4, 3000, CVMX_QLM_MODE_SATA_2X1, 0, 0, 0, 0);
+ octeon_configure_qlm(5, 103125, CVMX_QLM_MODE_XFI_1X2, 0, 0, 2, 0);
+ /* Apply amplitude tuning to 10G interface */
+ octeon_qlm_tune_v3(0, 4, 3000, -1, -1, 7, -1);
+ octeon_qlm_tune_v3(0, 5, 103125, 0x19, 0x0, -1, -1);
+ octeon_qlm_set_channel_v3(0, 5, 0);
+ octeon_qlm_dfe_disable(0, 5, -1, 103125, CVMX_QLM_MODE_XFI_1X2);
+ debug("QLM 4 reference clock: %d\n"
+ "DLM 5 reference clock: %d\n",
+ cvmx_qlm_measure_clock(4), cvmx_qlm_measure_clock(5));
+}
+
+int board_late_init(void)
+{
+ board_configure_qlms();
+
+ return 0;
+}
diff --git a/board/Marvell/octeon_nic23/board_ddr.h b/board/Marvell/octeon_nic23/board_ddr.h
new file mode 100644
index 000000000000..eac877faf853
--- /dev/null
+++ b/board/Marvell/octeon_nic23/board_ddr.h
@@ -0,0 +1,269 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __BOARD_DDR_H__
+#define __BOARD_DDR_H__
+
+#define OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0 \
+ { {0x0, 0x0}, {octeon_nic23_cfg0_spd_values, NULL} }
+
+#define NIC23_MTA8ATF51264AZ2G3_SPD_VALUES \
+ 0x23, 0x10, 0x0c, 0x02, 0x84, 0x19, 0x00, 0x08, \
+ 0x00, 0x00, 0x00, 0x03, 0x01, 0x0b, 0x80, 0x00, \
+ 0x00, 0x00, 0x08, 0x0c, 0xf4, 0x1b, 0x00, 0x00, \
+ 0x6c, 0x6c, 0x6c, 0x11, 0x08, 0x74, 0x20, 0x08, \
+ 0x00, 0x05, 0x70, 0x03, 0x00, 0xa8, 0x1e, 0x2b, \
+ 0x2b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x0c, 0x2c, 0x15, 0x35, \
+ 0x15, 0x35, 0x0b, 0x2c, 0x15, 0x35, 0x0b, 0x35, \
+ 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xec, 0xb5, 0xce, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x30, 0x0e, \
+ 0x11, 0x11, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x2e, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x80, 0x2c, 0x0f, 0x14, 0x50, 0x0e, 0x08, 0x18, \
+ 0xc8, 0x31, 0x38, 0x41, 0x53, 0x46, 0x31, 0x47, \
+ 0x37, 0x32, 0x41, 0x5a, 0x2d, 0x32, 0x47, 0x31, \
+ 0x41, 0x31, 0x20, 0x20, 0x20, 0x31, 0x80, 0x2c, \
+ 0x41, 0x44, 0x50, 0x41, 0x45, 0x4e, 0x43, 0x39, \
+ 0x30, 0x30, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+#define OCTEON_NIC23_CFG0_SPD_VALUES NIC23_MTA8ATF51264AZ2G3_SPD_VALUES
+
+#define OCTEON_NIC23_BOARD_EEPROM_TWSI_ADDR 0x56
+
+#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT \
+{ \
+ .cn78xx = { \
+ .pasr_00 = 0, \
+ .asr_00 = 0, \
+ .srt_00 = 0, \
+ .rtt_wr_00 = ddr4_rttwr_80ohm & 3, \
+ .rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
+ .dic_00 = ddr4_dic_34ohm, \
+ .rtt_nom_00 = 0, \
+ .pasr_01 = 0, \
+ .asr_01 = 0, \
+ .srt_01 = 0, \
+ .rtt_wr_01 = 0, \
+ .dic_01 = ddr4_dic_34ohm, \
+ .rtt_nom_01 = 0, \
+ .pasr_10 = 0, \
+ .asr_10 = 0, \
+ .srt_10 = 0, \
+ .rtt_wr_10 = 0, \
+ .dic_10 = ddr4_dic_34ohm, \
+ .rtt_nom_10 = 0, \
+ .pasr_11 = 0, \
+ .asr_11 = 0, \
+ .srt_11 = 0, \
+ .rtt_wr_11 = 0, \
+ .dic_11 = ddr4_dic_34ohm, \
+ .rtt_nom_11 = 0, \
+ } \
+ }
+
+#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT \
+{ \
+ .cn78xx = { \
+ .pasr_00 = 0, \
+ .asr_00 = 0, \
+ .srt_00 = 0, \
+ .rtt_wr_00 = ddr4_rttwr_80ohm & 3, \
+ .rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
+ .dic_00 = ddr4_dic_34ohm, \
+ .rtt_nom_00 = 0, \
+ .pasr_01 = 0, \
+ .asr_01 = 0, \
+ .srt_01 = 0, \
+ .rtt_wr_01 = 0, \
+ .dic_01 = ddr4_dic_34ohm, \
+ .rtt_nom_01 = 0, \
+ .pasr_10 = 0, \
+ .asr_10 = 0, \
+ .srt_10 = 0, \
+ .rtt_wr_10 = ddr4_rttwr_80ohm & 3, \
+ .rtt_wr_10_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
+ .dic_10 = ddr4_dic_34ohm, \
+ .rtt_nom_10 = 0, \
+ .pasr_11 = 0, \
+ .asr_11 = 0, \
+ .srt_11 = 0, \
+ .rtt_wr_11 = 0, \
+ .dic_11 = ddr4_dic_34ohm, \
+ .rtt_nom_11 = 0 \
+ } \
+}
+
+#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT \
+{ \
+ .cn78xx = { \
+ .rtt_park_00 = ddr4_rttpark_60ohm, \
+ .vref_value_00 = 0x22, \
+ .vref_range_00 = 0, \
+ .rtt_park_01 = 0, \
+ .vref_value_01 = 0, \
+ .vref_range_01 = 0, \
+ .rtt_park_10 = 0, \
+ .vref_value_10 = 0, \
+ .vref_range_10 = 0, \
+ .rtt_park_11 = 0, \
+ .vref_value_11 = 0, \
+ .vref_range_11 = 0 \
+ } \
+}
+
+#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT \
+{ \
+ .cn78xx = { \
+ .rtt_park_00 = ddr4_rttpark_48ohm, \
+ .vref_value_00 = 0x1f, \
+ .vref_range_00 = 0, \
+ .rtt_park_01 = 0, \
+ .vref_value_01 = 0, \
+ .vref_range_01 = 0, \
+ .rtt_park_10 = ddr4_rttpark_48ohm, \
+ .vref_value_10 = 0x1f, \
+ .vref_range_10 = 0, \
+ .rtt_park_11 = 0, \
+ .vref_value_11 = 0, \
+ .vref_range_11 = 0 \
+ } \
+}
+
+#define OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION \
+ /* 1 */ \
+ { \
+ ddr4_dqx_driver_34_ohm, \
+ 0x00000000ULL, \
+ OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT, \
+ OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT, \
+ ddr4_rodt_ctl_48_ohm, \
+ 0x00000000ULL, \
+ 0 \
+ }, \
+ /* 2 */ \
+ { \
+ ddr4_dqx_driver_34_ohm, \
+ 0x00000000ULL, \
+ OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT, \
+ OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT, \
+ ddr4_rodt_ctl_80_ohm, \
+ 0x00000000ULL, \
+ 0 \
+ }
+
+/*
+ * Construct a static initializer for the ddr_configuration_t variable that
+ * holds (almost) all of the information required for DDR initialization.
+ */
+
+/*
+ * The parameters below make up the custom_lmc_config data structure.
+ * This structure is used to customize the way that the LMC DRAM
+ * Controller is configured for a particular board design.
+ *
+ * Refer to the file lib_octeon_board_table_entry.h for a description
+ * of the custom board settings. It is usually kept in the following
+ * location... arch/mips/include/asm/arch-octeon/
+ *
+ */
+
+#define OCTEON_NIC23_DDR_CONFIGURATION \
+/* Interface 0 */ \
+{ \
+ .custom_lmc_config = { \
+ .min_rtt_nom_idx = 2, \
+ .max_rtt_nom_idx = 5, \
+ .min_rodt_ctl = 2, \
+ .max_rodt_ctl = 4, \
+ .ck_ctl = ddr4_driver_34_ohm, \
+ .cmd_ctl = ddr4_driver_34_ohm, \
+ .ctl_ctl = ddr4_driver_34_ohm, \
+ .min_cas_latency = 7, \
+ .offset_en = 1, \
+ .offset_udimm = 2, \
+ .offset_rdimm = 2, \
+ .ddr_rtt_nom_auto = 0, \
+ .ddr_rodt_ctl_auto = 0, \
+ .rlevel_compute = 0, \
+ .ddr2t_udimm = 1, \
+ .ddr2t_rdimm = 1, \
+ .maximum_adjacent_rlevel_delay_increment = 2, \
+ .fprch2 = 2, \
+ .dll_write_offset = NULL, \
+ .dll_read_offset = NULL, \
+ .disable_sequential_delay_check = 1, \
+ .parity = 0 \
+ }, \
+ .dimm_config_table = { \
+ OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0, \
+ DIMM_CONFIG_TERMINATOR \
+ }, \
+ .unbuffered = { \
+ .ddr_board_delay = 0, \
+ .lmc_delay_clk = 0, \
+ .lmc_delay_cmd = 0, \
+ .lmc_delay_dq = 0 \
+ }, \
+ .registered = { \
+ .ddr_board_delay = 0, \
+ .lmc_delay_clk = 0, \
+ .lmc_delay_cmd = 0, \
+ .lmc_delay_dq = 0 \
+ }, \
+ .odt_1rank_config = { \
+ OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION \
+ }, \
+},
+
+#endif /* __BOARD_DDR_H__ */
diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig
new file mode 100644
index 000000000000..f36af437c029
--- /dev/null
+++ b/configs/octeon_nic23_defconfig
@@ -0,0 +1,70 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0xffffffff80000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xe000
+CONFIG_ENV_SECT_SIZE=0x100
+CONFIG_DEBUG_UART_BASE=0x8001180000000800
+CONFIG_DEBUG_UART_CLOCK=800000000
+CONFIG_ARCH_OCTEON=y
+CONFIG_TARGET_OCTEON_NIC23=y
+# CONFIG_MIPS_CACHE_SETUP is not set
+# CONFIG_MIPS_CACHE_DISABLE is not set
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_ADDR=0xe000
+CONFIG_SATA=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_CLK=y
+# CONFIG_INPUT is not set
+CONFIG_MISC=y
+CONFIG_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_OCTEONTX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_NETDEVICES is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_RAM=y
+CONFIG_RAM_OCTEON=y
+CONFIG_RAM_OCTEON_DDR4=y
+CONFIG_SCSI=y
+CONFIG_DEBUG_UART_SHIFT=3
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_OCTEON_SERIAL_BOOTCMD=y
+CONFIG_OCTEON_SERIAL_PCIE_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_OCTEON_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_OCTEON=y
+CONFIG_HEXDUMP=y
diff --git a/include/configs/octeon_nic23.h b/include/configs/octeon_nic23.h
new file mode 100644
index 000000000000..0a7b4d8f93e2
--- /dev/null
+++ b/include/configs/octeon_nic23.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-2020
+ * Marvell <www.marvell.com>
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/*
+ * SATA/SCSI/AHCI configuration
+ */
+/* AHCI support Definitions */
+/** Enable 48-bit SATA addressing */
+#define CONFIG_LBA48
+/** Enable 64-bit addressing */
+#define CONFIG_SYS_64BIT_LBA
+
+#include "octeon_common.h"
+
+#endif /* __CONFIG_H__ */
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 13/15] mips: octeon: dts/dtsi: Change UART DT node to use clocks property
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (11 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 12/15] mips: octeon: Add Octeon III NIC23 board support Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 14/15] mips: octeon: ebb7304: Add support for some I2C devices Stefan Roese
` (2 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
From: Aaron Williams <awilliams@marvell.com>
We already have a clock driver for MIPS Octeon. This patch changes the
Octeon DT nodes to supply the clock property via the clock driver
instead of using an hard-coded value, which is not correct in all cases.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
arch/mips/dts/mrvl,cn73xx.dtsi | 2 ++
arch/mips/dts/mrvl,octeon-ebb7304.dts | 4 ----
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
index 83e5cde044a7..2a17f7a6a63e 100644
--- a/arch/mips/dts/mrvl,cn73xx.dtsi
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -97,6 +97,7 @@
uart0: serial at 1180000000800 {
compatible = "cavium,octeon-3860-uart","ns16550";
reg = <0x11800 0x00000800 0x0 0x400>;
+ clocks = <&clk OCTEON_CLK_IO>;
clock-frequency = <0>;
current-speed = <115200>;
reg-shift = <3>;
@@ -106,6 +107,7 @@
uart1: serial at 1180000000c00 {
compatible = "cavium,octeon-3860-uart","ns16550";
reg = <0x11800 0x00000c00 0x0 0x400>;
+ clocks = <&clk OCTEON_CLK_IO>;
clock-frequency = <0>;
current-speed = <115200>;
reg-shift = <3>;
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts
index 1bb34e1329f1..b95c18d34482 100644
--- a/arch/mips/dts/mrvl,octeon-ebb7304.dts
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -112,10 +112,6 @@
};
};
-&uart0 {
- clock-frequency = <1200000000>;
-};
-
&i2c0 {
u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
clock-frequency = <100000>;
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 14/15] mips: octeon: ebb7304: Add support for some I2C devices
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (12 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 13/15] mips: octeon: dts/dtsi: Change UART DT node to use clocks property Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-07 7:12 ` [PATCH v1 15/15] mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support Stefan Roese
2021-04-24 22:49 ` [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Daniel Schwierzeck
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
From: Aaron Williams <awilliams@marvell.com>
This patch adds support for the following I2C devices connected to
I2C bus 0 on the Octeon EBB7304:
- Dallas DS1337 RTC
- TLV EEPROM
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
arch/mips/dts/mrvl,octeon-ebb7304.dts | 11 +++++++++++
configs/octeon_ebb7304_defconfig | 4 ++++
2 files changed, 15 insertions(+)
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts
index b95c18d34482..fda559d8629d 100644
--- a/arch/mips/dts/mrvl,octeon-ebb7304.dts
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -115,6 +115,17 @@
&i2c0 {
u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
clock-frequency = <100000>;
+
+ rtc at 68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ };
+
+ tlv-eeprom at 56 {
+ compatible = "atmel,24c256", "microchip,24lc256";
+ reg = <0x56>;
+ pagesize = <64>;
+ };
};
&i2c1 {
diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig
index 4b25a4068245..8f0847fd0701 100644
--- a/configs/octeon_ebb7304_defconfig
+++ b/configs/octeon_ebb7304_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_CLOCK=1200000000
CONFIG_ARCH_OCTEON=y
# CONFIG_MIPS_CACHE_SETUP is not set
# CONFIG_MIPS_CACHE_DISABLE is not set
+CONFIG_MIPS_RELOCATION_TABLE_SIZE=0xc000
CONFIG_DEBUG_UART=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -23,6 +24,7 @@ CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_CMD_RTC=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
@@ -57,6 +59,8 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_RAM=y
CONFIG_RAM_OCTEON=y
CONFIG_RAM_OCTEON_DDR4=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_DS1307=y
CONFIG_DEBUG_UART_SHIFT=3
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 15/15] mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (13 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 14/15] mips: octeon: ebb7304: Add support for some I2C devices Stefan Roese
@ 2021-04-07 7:12 ` Stefan Roese
2021-04-24 22:49 ` [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Daniel Schwierzeck
15 siblings, 0 replies; 17+ messages in thread
From: Stefan Roese @ 2021-04-07 7:12 UTC (permalink / raw)
To: u-boot
This patch enables USB storage support with the necessary partition
support on the MIPS Octeon EBB7304.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
---
configs/octeon_ebb7304_defconfig | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig
index 8f0847fd0701..f614e95ad166 100644
--- a/configs/octeon_ebb7304_defconfig
+++ b/configs/octeon_ebb7304_defconfig
@@ -29,7 +29,9 @@ CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-# CONFIG_DOS_PARTITION is not set
+CONFIG_AMIGA_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x1FBFE000
CONFIG_CLK=y
@@ -72,6 +74,7 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
` (14 preceding siblings ...)
2021-04-07 7:12 ` [PATCH v1 15/15] mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support Stefan Roese
@ 2021-04-24 22:49 ` Daniel Schwierzeck
15 siblings, 0 replies; 17+ messages in thread
From: Daniel Schwierzeck @ 2021-04-24 22:49 UTC (permalink / raw)
To: u-boot
Am Mittwoch, den 07.04.2021, 09:12 +0200 schrieb Stefan Roese:
> This patchset adds the following updates / fixes for Marvell MIPS
> Octeon:
> - MIPS Octeon NIC23 base support
> - Add serial_octeon_pcie_console to support the Marvell remote tool
> "oct-remote-console"
> - Add serial_octeon_bootcmd to support the Marvell remote tools
> "oct-remote-load" & "oct-remote-bootcmd"
> - Fix AHCI driver to support big-endian platforms
> - Misc minor updates & fixes to the MIPS Octeon platform code
> - EBB7304: Enable USB storage support
> - EBB7304: Add I2C support (devices & commands)
>
> This patchset requires the MIPS Octeon serdes & PCIe patchset which
> was
> posted to the list 2020-12-11.
>
> Thanks,
> Stefan
>
>
> Aaron Williams (2):
> mips: octeon: dts/dtsi: Change UART DT node to use clocks property
> mips: octeon: ebb7304: Add support for some I2C devices
>
> Stefan Roese (13):
> mips: octeon: Move CVMX_SYNC from octeon_ddr.h to cvmx-regs.h
> mips: octeon: cvmx-bootmem: Fix compare in "if" statement
> mips: octeon: cvmx-coremask.h: Fix cvmx_coremask_dprint() with
> DEBUG
> defined
> serial: serial_octeon_pcie_console.c: Add PCI remote console
> support
> serial: serial_octeon_bootcmd.c: Add PCI remote console support
> mips: octeon: cpu.c: Add arch_misc_init() for pci-console &
> pci-bootcmd
> mips: octeon: cpu.c: Enable AHCI/SATA support
> sata: ahci_mvebu.c: Enable AHCI/SATA driver for MIPS Octeon
> ata: ahci: Fix usage on big-endian platforms
> scsi: Add ata_swap_buf_le16() to support big-endian platforms
> mips: octeon: mrvl,cn73xx.dtsi: Add AHCI/SATA DT node
> mips: octeon: Add Octeon III NIC23 board support
> mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support
series applied to u-boot-mips, thanks.
>
> arch/mips/dts/Makefile | 1 +
> arch/mips/dts/mrvl,cn73xx.dtsi | 21 +
> arch/mips/dts/mrvl,octeon-ebb7304.dts | 15 +-
> arch/mips/dts/mrvl,octeon-nic23.dts | 162 ++++++++
> arch/mips/mach-octeon/Kconfig | 7 +
> arch/mips/mach-octeon/cpu.c | 348
> ++++++++++++++++-
> arch/mips/mach-octeon/cvmx-bootmem.c | 4 +-
> .../mach-octeon/include/mach/cvmx-coremask.h | 5 +-
> .../mips/mach-octeon/include/mach/cvmx-regs.h | 1 +
> .../mach-octeon/include/mach/octeon_ddr.h | 2 -
> board/Marvell/octeon_nic23/Kconfig | 19 +
> board/Marvell/octeon_nic23/MAINTAINERS | 7 +
> board/Marvell/octeon_nic23/Makefile | 8 +
> board/Marvell/octeon_nic23/board.c | 106 +++++
> board/Marvell/octeon_nic23/board_ddr.h | 269 +++++++++++++
> configs/octeon_ebb7304_defconfig | 9 +-
> configs/octeon_nic23_defconfig | 70 ++++
> drivers/ata/Kconfig | 2 +-
> drivers/ata/ahci.c | 23 +-
> drivers/ata/ahci_mvebu.c | 3 +-
> drivers/scsi/scsi.c | 6 +
> drivers/serial/Kconfig | 24 ++
> drivers/serial/Makefile | 2 +
> drivers/serial/serial_octeon_bootcmd.c | 182 +++++++++
> drivers/serial/serial_octeon_pcie_console.c | 365
> ++++++++++++++++++
> include/configs/octeon_nic23.h | 21 +
> 26 files changed, 1656 insertions(+), 26 deletions(-)
> create mode 100644 arch/mips/dts/mrvl,octeon-nic23.dts
> create mode 100644 board/Marvell/octeon_nic23/Kconfig
> create mode 100644 board/Marvell/octeon_nic23/MAINTAINERS
> create mode 100644 board/Marvell/octeon_nic23/Makefile
> create mode 100644 board/Marvell/octeon_nic23/board.c
> create mode 100644 board/Marvell/octeon_nic23/board_ddr.h
> create mode 100644 configs/octeon_nic23_defconfig
> create mode 100644 drivers/serial/serial_octeon_bootcmd.c
> create mode 100644 drivers/serial/serial_octeon_pcie_console.c
> create mode 100644 include/configs/octeon_nic23.h
>
--
- Daniel
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2021-04-24 22:49 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-07 7:12 [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Stefan Roese
2021-04-07 7:12 ` [PATCH v1 01/15] mips: octeon: Move CVMX_SYNC from octeon_ddr.h to cvmx-regs.h Stefan Roese
2021-04-07 7:12 ` [PATCH v1 02/15] mips: octeon: cvmx-bootmem: Fix compare in "if" statement Stefan Roese
2021-04-07 7:12 ` [PATCH v1 03/15] mips: octeon: cvmx-coremask.h: Fix cvmx_coremask_dprint() with DEBUG defined Stefan Roese
2021-04-07 7:12 ` [PATCH v1 04/15] serial: serial_octeon_pcie_console.c: Add PCI remote console support Stefan Roese
2021-04-07 7:12 ` [PATCH v1 05/15] serial: serial_octeon_bootcmd.c: " Stefan Roese
2021-04-07 7:12 ` [PATCH v1 06/15] mips: octeon: cpu.c: Add arch_misc_init() for pci-console & pci-bootcmd Stefan Roese
2021-04-07 7:12 ` [PATCH v1 07/15] mips: octeon: cpu.c: Enable AHCI/SATA support Stefan Roese
2021-04-07 7:12 ` [PATCH v1 08/15] sata: ahci_mvebu.c: Enable AHCI/SATA driver for MIPS Octeon Stefan Roese
2021-04-07 7:12 ` [PATCH v1 09/15] ata: ahci: Fix usage on big-endian platforms Stefan Roese
2021-04-07 7:12 ` [PATCH v1 10/15] scsi: Add ata_swap_buf_le16() to support " Stefan Roese
2021-04-07 7:12 ` [PATCH v1 11/15] mips: octeon: mrvl, cn73xx.dtsi: Add AHCI/SATA DT node Stefan Roese
2021-04-07 7:12 ` [PATCH v1 12/15] mips: octeon: Add Octeon III NIC23 board support Stefan Roese
2021-04-07 7:12 ` [PATCH v1 13/15] mips: octeon: dts/dtsi: Change UART DT node to use clocks property Stefan Roese
2021-04-07 7:12 ` [PATCH v1 14/15] mips: octeon: ebb7304: Add support for some I2C devices Stefan Roese
2021-04-07 7:12 ` [PATCH v1 15/15] mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support Stefan Roese
2021-04-24 22:49 ` [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc Daniel Schwierzeck
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