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* [PATCH 0/2] ppc/pnv: Add support for the POWER10 DD2 CPU
@ 2021-05-05  9:06 Cédric Le Goater
  2021-05-05  9:06 ` [PATCH 1/2] ppc: Add a " Cédric Le Goater
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Cédric Le Goater @ 2021-05-05  9:06 UTC (permalink / raw)
  To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel

Hello,

The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit which is a requirement
to support the scv instruction on PowerNV POWER10 platforms (glibc-2.33).

These changes add a POWER10 DD2 CPU and switch the default chip model
of the powernv10 machine to use this CPU. This to make sure that the
machine can boot the latest distros.

Thanks,

C.


Cédric Le Goater (2):
  ppc: Add a POWER10 DD2 CPU
  ppc/pnv: Add support for the POWER10 DD2 CPU

 include/hw/ppc/pnv.h            | 2 +-
 target/ppc/cpu-models.h         | 1 +
 hw/ppc/pnv.c                    | 2 +-
 hw/ppc/pnv_core.c               | 2 +-
 target/ppc/cpu-models.c         | 4 +++-
 target/ppc/translate_init.c.inc | 2 +-
 6 files changed, 8 insertions(+), 5 deletions(-)

-- 
2.26.3



^ permalink raw reply	[flat|nested] 4+ messages in thread
* [PATCH 1/2] ppc: Add a POWER10 DD2 CPU
  2021-05-05  9:06 [PATCH 0/2] ppc/pnv: Add support for the POWER10 DD2 CPU Cédric Le Goater
@ 2021-05-05  9:06 ` Cédric Le Goater
  2021-05-05  9:06 ` [PATCH 2/2] ppc/pnv: Add support for the " Cédric Le Goater
  2021-05-10  5:53 ` [PATCH 0/2] " David Gibson
  2 siblings, 0 replies; 4+ messages in thread
From: Cédric Le Goater @ 2021-05-05  9:06 UTC (permalink / raw)
  To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel

The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. The required change
of the LPCR mask impacts all the POWER10 family. It is incorrect for
DD1 but it does not break the modeling.

Setting the HAIL bit is a requirement to support the scv instruction
on PowerNV POWER10 platforms since glibc-2.33.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 target/ppc/cpu-models.h         | 1 +
 target/ppc/cpu-models.c         | 4 +++-
 target/ppc/translate_init.c.inc | 2 +-
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index fc5e21728d7e..095259275941 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -375,6 +375,7 @@ enum {
     CPU_POWERPC_POWER9_DD20        = 0x004E1200,
     CPU_POWERPC_POWER10_BASE       = 0x00800000,
     CPU_POWERPC_POWER10_DD1        = 0x00800100,
+    CPU_POWERPC_POWER10_DD20       = 0x00800200,
     CPU_POWERPC_970_v22            = 0x00390202,
     CPU_POWERPC_970FX_v10          = 0x00391100,
     CPU_POWERPC_970FX_v20          = 0x003C0200,
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 87e4228614b0..4baa111713b0 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -776,6 +776,8 @@
                 "POWER9 v2.0")
     POWERPC_DEF("power10_v1.0",  CPU_POWERPC_POWER10_DD1,            POWER10,
                 "POWER10 v1.0")
+    POWERPC_DEF("power10_v2.0",  CPU_POWERPC_POWER10_DD20,           POWER10,
+                "POWER10 v2.0")
 #endif /* defined (TARGET_PPC64) */
 
 /***************************************************************************/
@@ -952,7 +954,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
     { "power8", "power8_v2.0" },
     { "power8nvl", "power8nvl_v1.0" },
     { "power9", "power9_v2.0" },
-    { "power10", "power10_v1.0" },
+    { "power10", "power10_v2.0" },
 #endif
 
     /* Generic PowerPCs */
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 76d82cc2f6bf..3cb0478df993 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -9302,7 +9302,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
                     (1ull << MSR_RI) |
                     (1ull << MSR_LE);
     pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
-        (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+        (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE |  LPCR_HAIL | LPCR_AIL |
         LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
         (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
                              LPCR_DEE | LPCR_OEE))
-- 
2.26.3



^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH 2/2] ppc/pnv: Add support for the POWER10 DD2 CPU
  2021-05-05  9:06 [PATCH 0/2] ppc/pnv: Add support for the POWER10 DD2 CPU Cédric Le Goater
  2021-05-05  9:06 ` [PATCH 1/2] ppc: Add a " Cédric Le Goater
@ 2021-05-05  9:06 ` Cédric Le Goater
  2021-05-10  5:53 ` [PATCH 0/2] " David Gibson
  2 siblings, 0 replies; 4+ messages in thread
From: Cédric Le Goater @ 2021-05-05  9:06 UTC (permalink / raw)
  To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel

The chip model of the powernv10 machine now uses the latest POWER10
DD2 CPU. The DD1 chip model is undefined and considered invalid.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ppc/pnv.h | 2 +-
 hw/ppc/pnv.c         | 2 +-
 hw/ppc/pnv_core.c    | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index d69cee17b232..3fec7c87d82d 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -170,7 +170,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
                          TYPE_PNV_CHIP_POWER9)
 
-#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0")
+#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0")
 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
                          TYPE_PNV_CHIP_POWER10)
 
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 77af846cdfea..0a1a518844f8 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1919,7 +1919,7 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
     static const char compat[] = "qemu,powernv10\0ibm,powernv";
 
     mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
-    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
+    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
 
     pmc->compat = compat;
     pmc->compat_size = sizeof(compat);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index bd2bf2e04472..5896b97e33f4 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -346,7 +346,7 @@ static const TypeInfo pnv_core_infos[] = {
     DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
     DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
     DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
-    DEFINE_PNV_CORE_TYPE(power10, "power10_v1.0"),
+    DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"),
 };
 
 DEFINE_TYPES(pnv_core_infos)
-- 
2.26.3



^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH 0/2] ppc/pnv: Add support for the POWER10 DD2 CPU
  2021-05-05  9:06 [PATCH 0/2] ppc/pnv: Add support for the POWER10 DD2 CPU Cédric Le Goater
  2021-05-05  9:06 ` [PATCH 1/2] ppc: Add a " Cédric Le Goater
  2021-05-05  9:06 ` [PATCH 2/2] ppc/pnv: Add support for the " Cédric Le Goater
@ 2021-05-10  5:53 ` David Gibson
  2 siblings, 0 replies; 4+ messages in thread
From: David Gibson @ 2021-05-10  5:53 UTC (permalink / raw)
  To: Cédric Le Goater; +Cc: qemu-ppc, Greg Kurz, qemu-devel

[-- Attachment #1: Type: text/plain, Size: 1175 bytes --]

On Wed, May 05, 2021 at 11:06:07AM +0200, Cédric Le Goater wrote:
> Hello,
> 
> The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit which is a requirement
> to support the scv instruction on PowerNV POWER10 platforms (glibc-2.33).
> 
> These changes add a POWER10 DD2 CPU and switch the default chip model
> of the powernv10 machine to use this CPU. This to make sure that the
> machine can boot the latest distros.

LGTM as far as it goes.  Couple of points

 * I'd prefer to combine the two patches together, basically
   atomically replacing DD1 with DD2
 * I'd like to sort out the DAWR1 support first, or at the same time.
   I think it's reasonable to treat anything about POWER10 emulation
   as experimental and unstable until we put an actually publically
   available chip in there.  If we sort out DAWR1 support now, it
   means we can avoid having another spapr capability flag to handle
   the case of qemu versions that support DD2, but not DAWR1.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-05-10  5:55 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-05  9:06 [PATCH 0/2] ppc/pnv: Add support for the POWER10 DD2 CPU Cédric Le Goater
2021-05-05  9:06 ` [PATCH 1/2] ppc: Add a " Cédric Le Goater
2021-05-05  9:06 ` [PATCH 2/2] ppc/pnv: Add support for the " Cédric Le Goater
2021-05-10  5:53 ` [PATCH 0/2] " David Gibson

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