* [intel-linux-intel-lts:5.4/yocto 40/1142] drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types)
@ 2021-06-10 14:12 kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2021-06-10 14:12 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 10727 bytes --]
tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto
head: eeb611e5394c56d45c5cc8f7dc484c9f19e93143
commit: 94e13c2880167751eb5cbbcb0e7be68ca83f0653 [40/1142] dmaengine: dw-axi-dma: support cyclic mode
config: powerpc-randconfig-s031-20210610 (attached as .config)
compiler: powerpc-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/intel/linux-intel-lts/commit/94e13c2880167751eb5cbbcb0e7be68ca83f0653
git remote add intel-linux-intel-lts https://github.com/intel/linux-intel-lts.git
git fetch --no-tags intel-linux-intel-lts 5.4/yocto
git checkout 94e13c2880167751eb5cbbcb0e7be68ca83f0653
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned int @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: got unsigned int
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned int @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: got unsigned int
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned int @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: got unsigned int
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: sparse: incorrect type in argument 2 (different base types) @@ expected unsigned int [usertype] irq_mask @@ got restricted __le32 [usertype] status_lo @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: expected unsigned int [usertype] irq_mask
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: got restricted __le32 [usertype] status_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: sparse: invalid assignment: |=
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: left side has type restricted __le32
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: right side has type unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1111:22: sparse: sparse: context imbalance in 'axi_chan_handle_err' - different lock contexts for basic block
vim +993 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
912
913 static struct dma_async_tx_descriptor *
914 dw_chan_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr,
915 size_t buf_len, size_t period_len,
916 enum dma_transfer_direction direction,
917 unsigned long flags)
918 {
919 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
920 struct axi_dma_desc *first = NULL, *prev = NULL;
921 unsigned int reg_width;
922 unsigned int mem_width;
923 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
924 dma_addr_t reg;
925 u32 reg_value = 0;
926 unsigned int i = 0;
927 u32 ctllo, ctlhi;
928 size_t total_len = 0;
929 size_t block_ts, max_block_ts;
930 u8 lms = 0; // Select AXI0 master for LLI fetching
931 u32 offset;
932
933 if (unlikely(!is_slave_direction(direction)))
934 return NULL;
935
936 chan->direction = direction;
937 chan->cyclic = 0x1;
938
939 max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
940
941 axi_set_hw_channel(chan->chip, chan->hw_hs_num);
942
943 switch (direction) {
944 case DMA_MEM_TO_DEV:
945 reg_width = __ffs(chan->slave_config.dst_addr_width);
946
947 chan->reg_width = reg_width;
948 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
949 offset = DMAC_APB_HALFWORD_WR_CH_EN;
950 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
951 reg_value |= 0x1 << chan->id;
952 axi_dma_apb_iowrite32(chan->chip,
953 DMAC_APB_HALFWORD_WR_CH_EN, reg_value);
954 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
955 offset = DMAC_APB_BYTE_WR_CH_EN;
956 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
957 reg_value |= 0x1 << chan->id;
958 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
959 }
960 reg = chan->slave_config.dst_addr;
961
962 ctllo = axi_dma_prepare_ctllo(chan) |
963 reg_width << CH_CTL_L_DST_WIDTH_POS |
964 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
965 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
966
967 for (i = 0; i < buf_len / period_len; i++) {
968 struct axi_dma_desc *desc;
969 size_t xfer_len;
970 u32 mem, len;
971
972 mem_width = __ffs(data_width | mem | len);
973 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
974 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
975
976 xfer_len = period_len;
977 block_ts = period_len;
978
979 desc = axi_desc_get(chan);
980 if (unlikely(!desc))
981 goto err_desc_get;
982
983 if (block_ts > max_block_ts) {
984 block_ts = max_block_ts;
985 xfer_len = max_block_ts << mem_width;
986 }
987
988 ctlhi = axi_dma_prepare_ctlhi(chan);
989
990 ctllo |= mem_width << CH_CTL_L_SRC_WIDTH_POS;
991 write_desc_sar(desc, buf_addr + i * period_len);
992 write_desc_dar(desc, reg);
> 993 desc->lli.block_ts_lo = period_len / 4;
994 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
995 desc->lli.ctl_lo = cpu_to_le32(ctllo);
996
997 set_desc_src_master(desc);
998 set_desc_src_master(desc);
999
1000 // Manage transfer list (xfer_list)
1001 if (!first) {
1002 first = desc;
1003 } else {
1004 write_desc_llp(prev, desc->vd.tx.phys | lms);
1005 list_add_tail(&desc->xfer_list,
1006 &first->xfer_list);
1007 }
1008 prev = desc;
1009 if (i == ((buf_len / period_len) - 1))
1010 write_desc_llp(prev, first->vd.tx.phys | lms);
1011
1012 total_len += xfer_len;
1013
1014 set_desc_last(desc);
1015 }
1016 break;
1017 case DMA_DEV_TO_MEM:
1018 reg_width = __ffs(chan->slave_config.src_addr_width);
1019
1020 chan->reg_width = reg_width;
1021 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
1022 offset = DMAC_APB_HALFWORD_WR_CH_EN;
1023 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
1024 reg_value |= 0x1 << chan->id;
1025 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
1026 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
1027 offset = DMAC_APB_BYTE_WR_CH_EN;
1028 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
1029 reg_value |= 0x1 << chan->id;
1030 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
1031 }
1032 reg = chan->slave_config.src_addr;
1033 if (reg_width > DWAXIDMAC_TRANS_WIDTH_32)
1034 reg_width = DWAXIDMAC_TRANS_WIDTH_32;
1035 ctllo = axi_dma_prepare_ctllo(chan) |
1036 reg_width << CH_CTL_L_SRC_WIDTH_POS |
1037 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
1038 // Workaround
1039 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
1040
1041 for (i = 0; i < buf_len / period_len; i++) {
1042 struct axi_dma_desc *desc;
1043 size_t xfer_len;
1044 u32 mem, len;
1045
1046 desc = axi_desc_get(chan);
1047 if (unlikely(!desc))
1048 goto err_desc_get;
1049
1050 xfer_len = len;
1051 block_ts = xfer_len >> reg_width;
1052 if (block_ts > max_block_ts) {
1053 block_ts = max_block_ts;
1054 xfer_len = max_block_ts << reg_width;
1055 }
1056 xfer_len = period_len;
1057 block_ts = period_len;
1058 mem_width = __ffs(data_width | mem | xfer_len);
1059 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
1060 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
1061
1062 ctlhi = axi_dma_prepare_ctlhi(chan);
1063 ctllo |= mem_width << CH_CTL_L_DST_WIDTH_POS;
1064
1065 write_desc_sar(desc, reg);
1066 write_desc_dar(desc, buf_addr + i * period_len);
1067 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
1068 desc->lli.block_ts_lo = period_len / 2;
1069 else if (reg_width >= DWAXIDMAC_TRANS_WIDTH_32)
1070 desc->lli.block_ts_lo = period_len / 4;
1071 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
1072 desc->lli.ctl_lo = cpu_to_le32(ctllo);
1073
1074 set_desc_src_master(desc);
1075 set_desc_src_master(desc);
1076
1077 // Manage transfer list (xfer_list)
1078 if (!first) {
1079 first = desc;
1080 } else {
1081 write_desc_llp(prev, desc->vd.tx.phys | lms);
1082 list_add_tail(&desc->xfer_list,
1083 &first->xfer_list);
1084 }
1085 prev = desc;
1086 if (i == ((buf_len / period_len) - 1))
1087 write_desc_llp(prev, first->vd.tx.phys | lms);
1088
1089 total_len += xfer_len;
1090
1091 // TODO: check if needed
1092 set_desc_last(desc);
1093 }
1094 break;
1095 default:
1096 return NULL;
1097 }
1098
1099 if (unlikely(!first))
1100 return NULL;
1101
1102 return vchan_tx_prep(&chan->vc, &first->vd, flags);
1103
1104 err_desc_get:
1105 if (first)
1106 axi_desc_put(first);
1107
1108 return NULL;
1109 }
1110
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 25109 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [intel-linux-intel-lts:5.4/yocto 40/1142] drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types)
@ 2021-09-04 20:09 kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2021-09-04 20:09 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 10701 bytes --]
tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto
head: eeb611e5394c56d45c5cc8f7dc484c9f19e93143
commit: 94e13c2880167751eb5cbbcb0e7be68ca83f0653 [40/1142] dmaengine: dw-axi-dma: support cyclic mode
config: arc-randconfig-s031-20210904 (attached as .config)
compiler: arc-elf-gcc (GCC) 11.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.4-rc1-dirty
# https://github.com/intel/linux-intel-lts/commit/94e13c2880167751eb5cbbcb0e7be68ca83f0653
git remote add intel-linux-intel-lts https://github.com/intel/linux-intel-lts.git
git fetch --no-tags intel-linux-intel-lts 5.4/yocto
git checkout 94e13c2880167751eb5cbbcb0e7be68ca83f0653
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=arc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned int @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: got unsigned int
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned int @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: got unsigned int
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned int @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: got unsigned int
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: sparse: incorrect type in argument 2 (different base types) @@ expected unsigned int [usertype] irq_mask @@ got restricted __le32 [usertype] status_lo @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: expected unsigned int [usertype] irq_mask
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: got restricted __le32 [usertype] status_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: sparse: invalid assignment: |=
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: left side has type restricted __le32
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: right side has type unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1111:22: sparse: sparse: context imbalance in 'axi_chan_handle_err' - different lock contexts for basic block
vim +993 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
912
913 static struct dma_async_tx_descriptor *
914 dw_chan_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr,
915 size_t buf_len, size_t period_len,
916 enum dma_transfer_direction direction,
917 unsigned long flags)
918 {
919 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
920 struct axi_dma_desc *first = NULL, *prev = NULL;
921 unsigned int reg_width;
922 unsigned int mem_width;
923 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
924 dma_addr_t reg;
925 u32 reg_value = 0;
926 unsigned int i = 0;
927 u32 ctllo, ctlhi;
928 size_t total_len = 0;
929 size_t block_ts, max_block_ts;
930 u8 lms = 0; // Select AXI0 master for LLI fetching
931 u32 offset;
932
933 if (unlikely(!is_slave_direction(direction)))
934 return NULL;
935
936 chan->direction = direction;
937 chan->cyclic = 0x1;
938
939 max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
940
941 axi_set_hw_channel(chan->chip, chan->hw_hs_num);
942
943 switch (direction) {
944 case DMA_MEM_TO_DEV:
945 reg_width = __ffs(chan->slave_config.dst_addr_width);
946
947 chan->reg_width = reg_width;
948 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
949 offset = DMAC_APB_HALFWORD_WR_CH_EN;
950 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
951 reg_value |= 0x1 << chan->id;
952 axi_dma_apb_iowrite32(chan->chip,
953 DMAC_APB_HALFWORD_WR_CH_EN, reg_value);
954 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
955 offset = DMAC_APB_BYTE_WR_CH_EN;
956 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
957 reg_value |= 0x1 << chan->id;
958 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
959 }
960 reg = chan->slave_config.dst_addr;
961
962 ctllo = axi_dma_prepare_ctllo(chan) |
963 reg_width << CH_CTL_L_DST_WIDTH_POS |
964 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
965 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
966
967 for (i = 0; i < buf_len / period_len; i++) {
968 struct axi_dma_desc *desc;
969 size_t xfer_len;
970 u32 mem, len;
971
972 mem_width = __ffs(data_width | mem | len);
973 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
974 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
975
976 xfer_len = period_len;
977 block_ts = period_len;
978
979 desc = axi_desc_get(chan);
980 if (unlikely(!desc))
981 goto err_desc_get;
982
983 if (block_ts > max_block_ts) {
984 block_ts = max_block_ts;
985 xfer_len = max_block_ts << mem_width;
986 }
987
988 ctlhi = axi_dma_prepare_ctlhi(chan);
989
990 ctllo |= mem_width << CH_CTL_L_SRC_WIDTH_POS;
991 write_desc_sar(desc, buf_addr + i * period_len);
992 write_desc_dar(desc, reg);
> 993 desc->lli.block_ts_lo = period_len / 4;
994 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
995 desc->lli.ctl_lo = cpu_to_le32(ctllo);
996
997 set_desc_src_master(desc);
998 set_desc_src_master(desc);
999
1000 // Manage transfer list (xfer_list)
1001 if (!first) {
1002 first = desc;
1003 } else {
1004 write_desc_llp(prev, desc->vd.tx.phys | lms);
1005 list_add_tail(&desc->xfer_list,
1006 &first->xfer_list);
1007 }
1008 prev = desc;
1009 if (i == ((buf_len / period_len) - 1))
1010 write_desc_llp(prev, first->vd.tx.phys | lms);
1011
1012 total_len += xfer_len;
1013
1014 set_desc_last(desc);
1015 }
1016 break;
1017 case DMA_DEV_TO_MEM:
1018 reg_width = __ffs(chan->slave_config.src_addr_width);
1019
1020 chan->reg_width = reg_width;
1021 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
1022 offset = DMAC_APB_HALFWORD_WR_CH_EN;
1023 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
1024 reg_value |= 0x1 << chan->id;
1025 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
1026 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
1027 offset = DMAC_APB_BYTE_WR_CH_EN;
1028 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
1029 reg_value |= 0x1 << chan->id;
1030 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
1031 }
1032 reg = chan->slave_config.src_addr;
1033 if (reg_width > DWAXIDMAC_TRANS_WIDTH_32)
1034 reg_width = DWAXIDMAC_TRANS_WIDTH_32;
1035 ctllo = axi_dma_prepare_ctllo(chan) |
1036 reg_width << CH_CTL_L_SRC_WIDTH_POS |
1037 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
1038 // Workaround
1039 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
1040
1041 for (i = 0; i < buf_len / period_len; i++) {
1042 struct axi_dma_desc *desc;
1043 size_t xfer_len;
1044 u32 mem, len;
1045
1046 desc = axi_desc_get(chan);
1047 if (unlikely(!desc))
1048 goto err_desc_get;
1049
1050 xfer_len = len;
1051 block_ts = xfer_len >> reg_width;
1052 if (block_ts > max_block_ts) {
1053 block_ts = max_block_ts;
1054 xfer_len = max_block_ts << reg_width;
1055 }
1056 xfer_len = period_len;
1057 block_ts = period_len;
1058 mem_width = __ffs(data_width | mem | xfer_len);
1059 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
1060 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
1061
1062 ctlhi = axi_dma_prepare_ctlhi(chan);
1063 ctllo |= mem_width << CH_CTL_L_DST_WIDTH_POS;
1064
1065 write_desc_sar(desc, reg);
1066 write_desc_dar(desc, buf_addr + i * period_len);
1067 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
1068 desc->lli.block_ts_lo = period_len / 2;
1069 else if (reg_width >= DWAXIDMAC_TRANS_WIDTH_32)
1070 desc->lli.block_ts_lo = period_len / 4;
1071 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
1072 desc->lli.ctl_lo = cpu_to_le32(ctllo);
1073
1074 set_desc_src_master(desc);
1075 set_desc_src_master(desc);
1076
1077 // Manage transfer list (xfer_list)
1078 if (!first) {
1079 first = desc;
1080 } else {
1081 write_desc_llp(prev, desc->vd.tx.phys | lms);
1082 list_add_tail(&desc->xfer_list,
1083 &first->xfer_list);
1084 }
1085 prev = desc;
1086 if (i == ((buf_len / period_len) - 1))
1087 write_desc_llp(prev, first->vd.tx.phys | lms);
1088
1089 total_len += xfer_len;
1090
1091 // TODO: check if needed
1092 set_desc_last(desc);
1093 }
1094 break;
1095 default:
1096 return NULL;
1097 }
1098
1099 if (unlikely(!first))
1100 return NULL;
1101
1102 return vchan_tx_prep(&chan->vc, &first->vd, flags);
1103
1104 err_desc_get:
1105 if (first)
1106 axi_desc_put(first);
1107
1108 return NULL;
1109 }
1110
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 30538 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [intel-linux-intel-lts:5.4/yocto 40/1142] drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types)
@ 2021-08-12 22:24 kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2021-08-12 22:24 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 28730 bytes --]
CC: kbuild-all(a)lists.01.org
TO: Sia Jee Heng <jee.heng.sia@intel.com>
CC: "Li, Yifan" <yifan2.li@intel.com>
tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto
head: eeb611e5394c56d45c5cc8f7dc484c9f19e93143
commit: 94e13c2880167751eb5cbbcb0e7be68ca83f0653 [40/1142] dmaengine: dw-axi-dma: support cyclic mode
:::::: branch date: 12 months ago
:::::: commit date: 12 months ago
config: h8300-randconfig-s032-20210812 (attached as .config)
compiler: h8300-linux-gcc (GCC) 10.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-348-gf0e6938b-dirty
# https://github.com/intel/linux-intel-lts/commit/94e13c2880167751eb5cbbcb0e7be68ca83f0653
git remote add intel-linux-intel-lts https://github.com/intel/linux-intel-lts.git
git fetch --no-tags intel-linux-intel-lts 5.4/yocto
git checkout 94e13c2880167751eb5cbbcb0e7be68ca83f0653
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=h8300
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned long @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: got unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned long @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: got unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned long @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: got unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: sparse: incorrect type in argument 2 (different base types) @@ expected unsigned int [usertype] irq_mask @@ got restricted __le32 [usertype] status_lo @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: expected unsigned int [usertype] irq_mask
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: got restricted __le32 [usertype] status_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: sparse: invalid assignment: |=
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: left side has type restricted __le32
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: right side has type unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through arch/h8300/include/asm/io.h, include/linux/scatterlist.h, include/linux/dmaengine.h):
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through include/linux/scatterlist.h, include/linux/dmaengine.h):
arch/h8300/include/asm/io.h:26:18: sparse: sparse: cast removes address space '<asn:2>' of expression
arch/h8300/include/asm/io.h:26:18: sparse: sparse: cast removes address space '<asn:2>' of expression
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through arch/h8300/include/asm/io.h, include/linux/scatterlist.h, include/linux/dmaengine.h):
include/asm-generic/io.h:225:22: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] b @@ got restricted __le32 [usertype] @@
include/asm-generic/io.h:225:22: sparse: expected unsigned int [usertype] b
include/asm-generic/io.h:225:22: sparse: got restricted __le32 [usertype]
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through include/linux/scatterlist.h, include/linux/dmaengine.h):
arch/h8300/include/asm/io.h:44:11: sparse: sparse: cast removes address space '<asn:2>' of expression
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through arch/h8300/include/asm/io.h, include/linux/scatterlist.h, include/linux/dmaengine.h):
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through include/linux/scatterlist.h, include/linux/dmaengine.h):
arch/h8300/include/asm/io.h:26:18: sparse: sparse: cast removes address space '<asn:2>' of expression
arch/h8300/include/asm/io.h:26:18: sparse: sparse: cast removes address space '<asn:2>' of expression
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through arch/h8300/include/asm/io.h, include/linux/scatterlist.h, include/linux/dmaengine.h):
include/asm-generic/io.h:225:22: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] b @@ got restricted __le32 [usertype] @@
include/asm-generic/io.h:225:22: sparse: expected unsigned int [usertype] b
include/asm-generic/io.h:225:22: sparse: got restricted __le32 [usertype]
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through include/linux/scatterlist.h, include/linux/dmaengine.h):
arch/h8300/include/asm/io.h:44:11: sparse: sparse: cast removes address space '<asn:2>' of expression
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through arch/h8300/include/asm/io.h, include/linux/scatterlist.h, include/linux/dmaengine.h):
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through include/linux/scatterlist.h, include/linux/dmaengine.h):
arch/h8300/include/asm/io.h:26:18: sparse: sparse: cast removes address space '<asn:2>' of expression
arch/h8300/include/asm/io.h:26:18: sparse: sparse: cast removes address space '<asn:2>' of expression
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through arch/h8300/include/asm/io.h, include/linux/scatterlist.h, include/linux/dmaengine.h):
include/asm-generic/io.h:225:22: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] b @@ got restricted __le32 [usertype] @@
include/asm-generic/io.h:225:22: sparse: expected unsigned int [usertype] b
include/asm-generic/io.h:225:22: sparse: got restricted __le32 [usertype]
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through include/linux/scatterlist.h, include/linux/dmaengine.h):
arch/h8300/include/asm/io.h:44:11: sparse: sparse: cast removes address space '<asn:2>' of expression
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through arch/h8300/include/asm/io.h, include/linux/scatterlist.h, include/linux/dmaengine.h):
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through include/linux/scatterlist.h, include/linux/dmaengine.h):
arch/h8300/include/asm/io.h:26:18: sparse: sparse: cast removes address space '<asn:2>' of expression
arch/h8300/include/asm/io.h:26:18: sparse: sparse: cast removes address space '<asn:2>' of expression
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through arch/h8300/include/asm/io.h, include/linux/scatterlist.h, include/linux/dmaengine.h):
include/asm-generic/io.h:225:22: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] b @@ got restricted __le32 [usertype] @@
include/asm-generic/io.h:225:22: sparse: expected unsigned int [usertype] b
include/asm-generic/io.h:225:22: sparse: got restricted __le32 [usertype]
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through include/linux/scatterlist.h, include/linux/dmaengine.h):
arch/h8300/include/asm/io.h:44:11: sparse: sparse: cast removes address space '<asn:2>' of expression
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through arch/h8300/include/asm/io.h, include/linux/scatterlist.h, include/linux/dmaengine.h):
include/asm-generic/io.h:225:22: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] b @@ got restricted __le32 [usertype] @@
include/asm-generic/io.h:225:22: sparse: expected unsigned int [usertype] b
include/asm-generic/io.h:225:22: sparse: got restricted __le32 [usertype]
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through include/linux/scatterlist.h, include/linux/dmaengine.h):
arch/h8300/include/asm/io.h:44:11: sparse: sparse: cast removes address space '<asn:2>' of expression
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through arch/h8300/include/asm/io.h, include/linux/scatterlist.h, include/linux/dmaengine.h):
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
include/asm-generic/io.h:179:15: sparse: sparse: cast to restricted __le32
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through include/linux/scatterlist.h, include/linux/dmaengine.h):
arch/h8300/include/asm/io.h:26:18: sparse: sparse: cast removes address space '<asn:2>' of expression
arch/h8300/include/asm/io.h:26:18: sparse: sparse: cast removes address space '<asn:2>' of expression
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through arch/h8300/include/asm/io.h, include/linux/scatterlist.h, include/linux/dmaengine.h):
include/asm-generic/io.h:225:22: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] b @@ got restricted __le32 [usertype] @@
include/asm-generic/io.h:225:22: sparse: expected unsigned int [usertype] b
include/asm-generic/io.h:225:22: sparse: got restricted __le32 [usertype]
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c: note: in included file (through include/linux/scatterlist.h, include/linux/dmaengine.h):
arch/h8300/include/asm/io.h:44:11: sparse: sparse: cast removes address space '<asn:2>' of expression
vim +993 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 912
94e13c28801677 Sia Jee Heng 2020-06-26 913 static struct dma_async_tx_descriptor *
94e13c28801677 Sia Jee Heng 2020-06-26 914 dw_chan_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr,
94e13c28801677 Sia Jee Heng 2020-06-26 915 size_t buf_len, size_t period_len,
94e13c28801677 Sia Jee Heng 2020-06-26 916 enum dma_transfer_direction direction,
94e13c28801677 Sia Jee Heng 2020-06-26 917 unsigned long flags)
94e13c28801677 Sia Jee Heng 2020-06-26 918 {
94e13c28801677 Sia Jee Heng 2020-06-26 919 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
94e13c28801677 Sia Jee Heng 2020-06-26 920 struct axi_dma_desc *first = NULL, *prev = NULL;
94e13c28801677 Sia Jee Heng 2020-06-26 921 unsigned int reg_width;
94e13c28801677 Sia Jee Heng 2020-06-26 922 unsigned int mem_width;
94e13c28801677 Sia Jee Heng 2020-06-26 923 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
94e13c28801677 Sia Jee Heng 2020-06-26 924 dma_addr_t reg;
94e13c28801677 Sia Jee Heng 2020-06-26 925 u32 reg_value = 0;
94e13c28801677 Sia Jee Heng 2020-06-26 926 unsigned int i = 0;
94e13c28801677 Sia Jee Heng 2020-06-26 927 u32 ctllo, ctlhi;
94e13c28801677 Sia Jee Heng 2020-06-26 928 size_t total_len = 0;
94e13c28801677 Sia Jee Heng 2020-06-26 929 size_t block_ts, max_block_ts;
94e13c28801677 Sia Jee Heng 2020-06-26 930 u8 lms = 0; // Select AXI0 master for LLI fetching
94e13c28801677 Sia Jee Heng 2020-06-26 931 u32 offset;
94e13c28801677 Sia Jee Heng 2020-06-26 932
94e13c28801677 Sia Jee Heng 2020-06-26 933 if (unlikely(!is_slave_direction(direction)))
94e13c28801677 Sia Jee Heng 2020-06-26 934 return NULL;
94e13c28801677 Sia Jee Heng 2020-06-26 935
94e13c28801677 Sia Jee Heng 2020-06-26 936 chan->direction = direction;
94e13c28801677 Sia Jee Heng 2020-06-26 937 chan->cyclic = 0x1;
94e13c28801677 Sia Jee Heng 2020-06-26 938
94e13c28801677 Sia Jee Heng 2020-06-26 939 max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
94e13c28801677 Sia Jee Heng 2020-06-26 940
94e13c28801677 Sia Jee Heng 2020-06-26 941 axi_set_hw_channel(chan->chip, chan->hw_hs_num);
94e13c28801677 Sia Jee Heng 2020-06-26 942
94e13c28801677 Sia Jee Heng 2020-06-26 943 switch (direction) {
94e13c28801677 Sia Jee Heng 2020-06-26 944 case DMA_MEM_TO_DEV:
94e13c28801677 Sia Jee Heng 2020-06-26 945 reg_width = __ffs(chan->slave_config.dst_addr_width);
94e13c28801677 Sia Jee Heng 2020-06-26 946
94e13c28801677 Sia Jee Heng 2020-06-26 947 chan->reg_width = reg_width;
94e13c28801677 Sia Jee Heng 2020-06-26 948 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
94e13c28801677 Sia Jee Heng 2020-06-26 949 offset = DMAC_APB_HALFWORD_WR_CH_EN;
94e13c28801677 Sia Jee Heng 2020-06-26 950 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
94e13c28801677 Sia Jee Heng 2020-06-26 951 reg_value |= 0x1 << chan->id;
94e13c28801677 Sia Jee Heng 2020-06-26 952 axi_dma_apb_iowrite32(chan->chip,
94e13c28801677 Sia Jee Heng 2020-06-26 953 DMAC_APB_HALFWORD_WR_CH_EN, reg_value);
94e13c28801677 Sia Jee Heng 2020-06-26 954 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
94e13c28801677 Sia Jee Heng 2020-06-26 955 offset = DMAC_APB_BYTE_WR_CH_EN;
94e13c28801677 Sia Jee Heng 2020-06-26 956 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
94e13c28801677 Sia Jee Heng 2020-06-26 957 reg_value |= 0x1 << chan->id;
94e13c28801677 Sia Jee Heng 2020-06-26 958 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
94e13c28801677 Sia Jee Heng 2020-06-26 959 }
94e13c28801677 Sia Jee Heng 2020-06-26 960 reg = chan->slave_config.dst_addr;
94e13c28801677 Sia Jee Heng 2020-06-26 961
94e13c28801677 Sia Jee Heng 2020-06-26 962 ctllo = axi_dma_prepare_ctllo(chan) |
94e13c28801677 Sia Jee Heng 2020-06-26 963 reg_width << CH_CTL_L_DST_WIDTH_POS |
94e13c28801677 Sia Jee Heng 2020-06-26 964 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
94e13c28801677 Sia Jee Heng 2020-06-26 965 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
94e13c28801677 Sia Jee Heng 2020-06-26 966
94e13c28801677 Sia Jee Heng 2020-06-26 967 for (i = 0; i < buf_len / period_len; i++) {
94e13c28801677 Sia Jee Heng 2020-06-26 968 struct axi_dma_desc *desc;
94e13c28801677 Sia Jee Heng 2020-06-26 969 size_t xfer_len;
94e13c28801677 Sia Jee Heng 2020-06-26 970 u32 mem, len;
94e13c28801677 Sia Jee Heng 2020-06-26 971
94e13c28801677 Sia Jee Heng 2020-06-26 972 mem_width = __ffs(data_width | mem | len);
94e13c28801677 Sia Jee Heng 2020-06-26 973 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
94e13c28801677 Sia Jee Heng 2020-06-26 974 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
94e13c28801677 Sia Jee Heng 2020-06-26 975
94e13c28801677 Sia Jee Heng 2020-06-26 976 xfer_len = period_len;
94e13c28801677 Sia Jee Heng 2020-06-26 977 block_ts = period_len;
94e13c28801677 Sia Jee Heng 2020-06-26 978
94e13c28801677 Sia Jee Heng 2020-06-26 979 desc = axi_desc_get(chan);
94e13c28801677 Sia Jee Heng 2020-06-26 980 if (unlikely(!desc))
94e13c28801677 Sia Jee Heng 2020-06-26 981 goto err_desc_get;
94e13c28801677 Sia Jee Heng 2020-06-26 982
94e13c28801677 Sia Jee Heng 2020-06-26 983 if (block_ts > max_block_ts) {
94e13c28801677 Sia Jee Heng 2020-06-26 984 block_ts = max_block_ts;
94e13c28801677 Sia Jee Heng 2020-06-26 985 xfer_len = max_block_ts << mem_width;
94e13c28801677 Sia Jee Heng 2020-06-26 986 }
94e13c28801677 Sia Jee Heng 2020-06-26 987
94e13c28801677 Sia Jee Heng 2020-06-26 988 ctlhi = axi_dma_prepare_ctlhi(chan);
94e13c28801677 Sia Jee Heng 2020-06-26 989
94e13c28801677 Sia Jee Heng 2020-06-26 990 ctllo |= mem_width << CH_CTL_L_SRC_WIDTH_POS;
94e13c28801677 Sia Jee Heng 2020-06-26 991 write_desc_sar(desc, buf_addr + i * period_len);
94e13c28801677 Sia Jee Heng 2020-06-26 992 write_desc_dar(desc, reg);
94e13c28801677 Sia Jee Heng 2020-06-26 @993 desc->lli.block_ts_lo = period_len / 4;
94e13c28801677 Sia Jee Heng 2020-06-26 994 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
94e13c28801677 Sia Jee Heng 2020-06-26 995 desc->lli.ctl_lo = cpu_to_le32(ctllo);
94e13c28801677 Sia Jee Heng 2020-06-26 996
94e13c28801677 Sia Jee Heng 2020-06-26 997 set_desc_src_master(desc);
94e13c28801677 Sia Jee Heng 2020-06-26 998 set_desc_src_master(desc);
94e13c28801677 Sia Jee Heng 2020-06-26 999
94e13c28801677 Sia Jee Heng 2020-06-26 1000 // Manage transfer list (xfer_list)
94e13c28801677 Sia Jee Heng 2020-06-26 1001 if (!first) {
94e13c28801677 Sia Jee Heng 2020-06-26 1002 first = desc;
94e13c28801677 Sia Jee Heng 2020-06-26 1003 } else {
94e13c28801677 Sia Jee Heng 2020-06-26 1004 write_desc_llp(prev, desc->vd.tx.phys | lms);
94e13c28801677 Sia Jee Heng 2020-06-26 1005 list_add_tail(&desc->xfer_list,
94e13c28801677 Sia Jee Heng 2020-06-26 1006 &first->xfer_list);
94e13c28801677 Sia Jee Heng 2020-06-26 1007 }
94e13c28801677 Sia Jee Heng 2020-06-26 1008 prev = desc;
94e13c28801677 Sia Jee Heng 2020-06-26 1009 if (i == ((buf_len / period_len) - 1))
94e13c28801677 Sia Jee Heng 2020-06-26 1010 write_desc_llp(prev, first->vd.tx.phys | lms);
94e13c28801677 Sia Jee Heng 2020-06-26 1011
94e13c28801677 Sia Jee Heng 2020-06-26 1012 total_len += xfer_len;
94e13c28801677 Sia Jee Heng 2020-06-26 1013
94e13c28801677 Sia Jee Heng 2020-06-26 1014 set_desc_last(desc);
94e13c28801677 Sia Jee Heng 2020-06-26 1015 }
94e13c28801677 Sia Jee Heng 2020-06-26 1016 break;
94e13c28801677 Sia Jee Heng 2020-06-26 1017 case DMA_DEV_TO_MEM:
94e13c28801677 Sia Jee Heng 2020-06-26 1018 reg_width = __ffs(chan->slave_config.src_addr_width);
94e13c28801677 Sia Jee Heng 2020-06-26 1019
94e13c28801677 Sia Jee Heng 2020-06-26 1020 chan->reg_width = reg_width;
94e13c28801677 Sia Jee Heng 2020-06-26 1021 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
94e13c28801677 Sia Jee Heng 2020-06-26 1022 offset = DMAC_APB_HALFWORD_WR_CH_EN;
94e13c28801677 Sia Jee Heng 2020-06-26 1023 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
94e13c28801677 Sia Jee Heng 2020-06-26 1024 reg_value |= 0x1 << chan->id;
94e13c28801677 Sia Jee Heng 2020-06-26 1025 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
94e13c28801677 Sia Jee Heng 2020-06-26 1026 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
94e13c28801677 Sia Jee Heng 2020-06-26 1027 offset = DMAC_APB_BYTE_WR_CH_EN;
94e13c28801677 Sia Jee Heng 2020-06-26 1028 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
94e13c28801677 Sia Jee Heng 2020-06-26 1029 reg_value |= 0x1 << chan->id;
94e13c28801677 Sia Jee Heng 2020-06-26 1030 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
94e13c28801677 Sia Jee Heng 2020-06-26 1031 }
94e13c28801677 Sia Jee Heng 2020-06-26 1032 reg = chan->slave_config.src_addr;
94e13c28801677 Sia Jee Heng 2020-06-26 1033 if (reg_width > DWAXIDMAC_TRANS_WIDTH_32)
94e13c28801677 Sia Jee Heng 2020-06-26 1034 reg_width = DWAXIDMAC_TRANS_WIDTH_32;
94e13c28801677 Sia Jee Heng 2020-06-26 1035 ctllo = axi_dma_prepare_ctllo(chan) |
94e13c28801677 Sia Jee Heng 2020-06-26 1036 reg_width << CH_CTL_L_SRC_WIDTH_POS |
94e13c28801677 Sia Jee Heng 2020-06-26 1037 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
94e13c28801677 Sia Jee Heng 2020-06-26 1038 // Workaround
94e13c28801677 Sia Jee Heng 2020-06-26 1039 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
94e13c28801677 Sia Jee Heng 2020-06-26 1040
94e13c28801677 Sia Jee Heng 2020-06-26 1041 for (i = 0; i < buf_len / period_len; i++) {
94e13c28801677 Sia Jee Heng 2020-06-26 1042 struct axi_dma_desc *desc;
94e13c28801677 Sia Jee Heng 2020-06-26 1043 size_t xfer_len;
94e13c28801677 Sia Jee Heng 2020-06-26 1044 u32 mem, len;
94e13c28801677 Sia Jee Heng 2020-06-26 1045
94e13c28801677 Sia Jee Heng 2020-06-26 1046 desc = axi_desc_get(chan);
94e13c28801677 Sia Jee Heng 2020-06-26 1047 if (unlikely(!desc))
94e13c28801677 Sia Jee Heng 2020-06-26 1048 goto err_desc_get;
94e13c28801677 Sia Jee Heng 2020-06-26 1049
94e13c28801677 Sia Jee Heng 2020-06-26 1050 xfer_len = len;
94e13c28801677 Sia Jee Heng 2020-06-26 1051 block_ts = xfer_len >> reg_width;
94e13c28801677 Sia Jee Heng 2020-06-26 1052 if (block_ts > max_block_ts) {
94e13c28801677 Sia Jee Heng 2020-06-26 1053 block_ts = max_block_ts;
94e13c28801677 Sia Jee Heng 2020-06-26 1054 xfer_len = max_block_ts << reg_width;
94e13c28801677 Sia Jee Heng 2020-06-26 1055 }
94e13c28801677 Sia Jee Heng 2020-06-26 1056 xfer_len = period_len;
94e13c28801677 Sia Jee Heng 2020-06-26 1057 block_ts = period_len;
94e13c28801677 Sia Jee Heng 2020-06-26 1058 mem_width = __ffs(data_width | mem | xfer_len);
94e13c28801677 Sia Jee Heng 2020-06-26 1059 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
94e13c28801677 Sia Jee Heng 2020-06-26 1060 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
94e13c28801677 Sia Jee Heng 2020-06-26 1061
94e13c28801677 Sia Jee Heng 2020-06-26 1062 ctlhi = axi_dma_prepare_ctlhi(chan);
94e13c28801677 Sia Jee Heng 2020-06-26 1063 ctllo |= mem_width << CH_CTL_L_DST_WIDTH_POS;
94e13c28801677 Sia Jee Heng 2020-06-26 1064
94e13c28801677 Sia Jee Heng 2020-06-26 1065 write_desc_sar(desc, reg);
94e13c28801677 Sia Jee Heng 2020-06-26 1066 write_desc_dar(desc, buf_addr + i * period_len);
94e13c28801677 Sia Jee Heng 2020-06-26 1067 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
94e13c28801677 Sia Jee Heng 2020-06-26 1068 desc->lli.block_ts_lo = period_len / 2;
94e13c28801677 Sia Jee Heng 2020-06-26 1069 else if (reg_width >= DWAXIDMAC_TRANS_WIDTH_32)
94e13c28801677 Sia Jee Heng 2020-06-26 1070 desc->lli.block_ts_lo = period_len / 4;
94e13c28801677 Sia Jee Heng 2020-06-26 1071 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
94e13c28801677 Sia Jee Heng 2020-06-26 1072 desc->lli.ctl_lo = cpu_to_le32(ctllo);
94e13c28801677 Sia Jee Heng 2020-06-26 1073
94e13c28801677 Sia Jee Heng 2020-06-26 1074 set_desc_src_master(desc);
94e13c28801677 Sia Jee Heng 2020-06-26 1075 set_desc_src_master(desc);
94e13c28801677 Sia Jee Heng 2020-06-26 1076
94e13c28801677 Sia Jee Heng 2020-06-26 1077 // Manage transfer list (xfer_list)
94e13c28801677 Sia Jee Heng 2020-06-26 1078 if (!first) {
94e13c28801677 Sia Jee Heng 2020-06-26 1079 first = desc;
94e13c28801677 Sia Jee Heng 2020-06-26 1080 } else {
94e13c28801677 Sia Jee Heng 2020-06-26 1081 write_desc_llp(prev, desc->vd.tx.phys | lms);
94e13c28801677 Sia Jee Heng 2020-06-26 1082 list_add_tail(&desc->xfer_list,
94e13c28801677 Sia Jee Heng 2020-06-26 1083 &first->xfer_list);
94e13c28801677 Sia Jee Heng 2020-06-26 1084 }
94e13c28801677 Sia Jee Heng 2020-06-26 1085 prev = desc;
94e13c28801677 Sia Jee Heng 2020-06-26 1086 if (i == ((buf_len / period_len) - 1))
94e13c28801677 Sia Jee Heng 2020-06-26 1087 write_desc_llp(prev, first->vd.tx.phys | lms);
94e13c28801677 Sia Jee Heng 2020-06-26 1088
94e13c28801677 Sia Jee Heng 2020-06-26 1089 total_len += xfer_len;
94e13c28801677 Sia Jee Heng 2020-06-26 1090
94e13c28801677 Sia Jee Heng 2020-06-26 1091 // TODO: check if needed
94e13c28801677 Sia Jee Heng 2020-06-26 1092 set_desc_last(desc);
94e13c28801677 Sia Jee Heng 2020-06-26 1093 }
94e13c28801677 Sia Jee Heng 2020-06-26 1094 break;
94e13c28801677 Sia Jee Heng 2020-06-26 1095 default:
94e13c28801677 Sia Jee Heng 2020-06-26 1096 return NULL;
94e13c28801677 Sia Jee Heng 2020-06-26 1097 }
94e13c28801677 Sia Jee Heng 2020-06-26 1098
94e13c28801677 Sia Jee Heng 2020-06-26 1099 if (unlikely(!first))
94e13c28801677 Sia Jee Heng 2020-06-26 1100 return NULL;
94e13c28801677 Sia Jee Heng 2020-06-26 1101
94e13c28801677 Sia Jee Heng 2020-06-26 1102 return vchan_tx_prep(&chan->vc, &first->vd, flags);
94e13c28801677 Sia Jee Heng 2020-06-26 1103
94e13c28801677 Sia Jee Heng 2020-06-26 1104 err_desc_get:
94e13c28801677 Sia Jee Heng 2020-06-26 1105 if (first)
94e13c28801677 Sia Jee Heng 2020-06-26 1106 axi_desc_put(first);
94e13c28801677 Sia Jee Heng 2020-06-26 1107
94e13c28801677 Sia Jee Heng 2020-06-26 1108 return NULL;
94e13c28801677 Sia Jee Heng 2020-06-26 1109 }
94e13c28801677 Sia Jee Heng 2020-06-26 1110
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 22562 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [intel-linux-intel-lts:5.4/yocto 40/1142] drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types)
@ 2021-06-19 17:42 kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2021-06-19 17:42 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 10535 bytes --]
tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto
head: eeb611e5394c56d45c5cc8f7dc484c9f19e93143
commit: 94e13c2880167751eb5cbbcb0e7be68ca83f0653 [40/1142] dmaengine: dw-axi-dma: support cyclic mode
config: x86_64-randconfig-s021-20210618 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/intel/linux-intel-lts/commit/94e13c2880167751eb5cbbcb0e7be68ca83f0653
git remote add intel-linux-intel-lts https://github.com/intel/linux-intel-lts.git
git fetch --no-tags intel-linux-intel-lts 5.4/yocto
git checkout 94e13c2880167751eb5cbbcb0e7be68ca83f0653
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned long @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: got unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned long @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: got unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned long @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: got unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: sparse: incorrect type in argument 2 (different base types) @@ expected unsigned int [usertype] irq_mask @@ got restricted __le32 [usertype] status_lo @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: expected unsigned int [usertype] irq_mask
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: got restricted __le32 [usertype] status_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: sparse: invalid assignment: |=
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: left side has type restricted __le32
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: right side has type unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1111:22: sparse: sparse: context imbalance in 'axi_chan_handle_err' - different lock contexts for basic block
vim +993 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
912
913 static struct dma_async_tx_descriptor *
914 dw_chan_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr,
915 size_t buf_len, size_t period_len,
916 enum dma_transfer_direction direction,
917 unsigned long flags)
918 {
919 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
920 struct axi_dma_desc *first = NULL, *prev = NULL;
921 unsigned int reg_width;
922 unsigned int mem_width;
923 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
924 dma_addr_t reg;
925 u32 reg_value = 0;
926 unsigned int i = 0;
927 u32 ctllo, ctlhi;
928 size_t total_len = 0;
929 size_t block_ts, max_block_ts;
930 u8 lms = 0; // Select AXI0 master for LLI fetching
931 u32 offset;
932
933 if (unlikely(!is_slave_direction(direction)))
934 return NULL;
935
936 chan->direction = direction;
937 chan->cyclic = 0x1;
938
939 max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
940
941 axi_set_hw_channel(chan->chip, chan->hw_hs_num);
942
943 switch (direction) {
944 case DMA_MEM_TO_DEV:
945 reg_width = __ffs(chan->slave_config.dst_addr_width);
946
947 chan->reg_width = reg_width;
948 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
949 offset = DMAC_APB_HALFWORD_WR_CH_EN;
950 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
951 reg_value |= 0x1 << chan->id;
952 axi_dma_apb_iowrite32(chan->chip,
953 DMAC_APB_HALFWORD_WR_CH_EN, reg_value);
954 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
955 offset = DMAC_APB_BYTE_WR_CH_EN;
956 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
957 reg_value |= 0x1 << chan->id;
958 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
959 }
960 reg = chan->slave_config.dst_addr;
961
962 ctllo = axi_dma_prepare_ctllo(chan) |
963 reg_width << CH_CTL_L_DST_WIDTH_POS |
964 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
965 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
966
967 for (i = 0; i < buf_len / period_len; i++) {
968 struct axi_dma_desc *desc;
969 size_t xfer_len;
970 u32 mem, len;
971
972 mem_width = __ffs(data_width | mem | len);
973 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
974 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
975
976 xfer_len = period_len;
977 block_ts = period_len;
978
979 desc = axi_desc_get(chan);
980 if (unlikely(!desc))
981 goto err_desc_get;
982
983 if (block_ts > max_block_ts) {
984 block_ts = max_block_ts;
985 xfer_len = max_block_ts << mem_width;
986 }
987
988 ctlhi = axi_dma_prepare_ctlhi(chan);
989
990 ctllo |= mem_width << CH_CTL_L_SRC_WIDTH_POS;
991 write_desc_sar(desc, buf_addr + i * period_len);
992 write_desc_dar(desc, reg);
> 993 desc->lli.block_ts_lo = period_len / 4;
994 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
995 desc->lli.ctl_lo = cpu_to_le32(ctllo);
996
997 set_desc_src_master(desc);
998 set_desc_src_master(desc);
999
1000 // Manage transfer list (xfer_list)
1001 if (!first) {
1002 first = desc;
1003 } else {
1004 write_desc_llp(prev, desc->vd.tx.phys | lms);
1005 list_add_tail(&desc->xfer_list,
1006 &first->xfer_list);
1007 }
1008 prev = desc;
1009 if (i == ((buf_len / period_len) - 1))
1010 write_desc_llp(prev, first->vd.tx.phys | lms);
1011
1012 total_len += xfer_len;
1013
1014 set_desc_last(desc);
1015 }
1016 break;
1017 case DMA_DEV_TO_MEM:
1018 reg_width = __ffs(chan->slave_config.src_addr_width);
1019
1020 chan->reg_width = reg_width;
1021 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
1022 offset = DMAC_APB_HALFWORD_WR_CH_EN;
1023 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
1024 reg_value |= 0x1 << chan->id;
1025 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
1026 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
1027 offset = DMAC_APB_BYTE_WR_CH_EN;
1028 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
1029 reg_value |= 0x1 << chan->id;
1030 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
1031 }
1032 reg = chan->slave_config.src_addr;
1033 if (reg_width > DWAXIDMAC_TRANS_WIDTH_32)
1034 reg_width = DWAXIDMAC_TRANS_WIDTH_32;
1035 ctllo = axi_dma_prepare_ctllo(chan) |
1036 reg_width << CH_CTL_L_SRC_WIDTH_POS |
1037 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
1038 // Workaround
1039 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
1040
1041 for (i = 0; i < buf_len / period_len; i++) {
1042 struct axi_dma_desc *desc;
1043 size_t xfer_len;
1044 u32 mem, len;
1045
1046 desc = axi_desc_get(chan);
1047 if (unlikely(!desc))
1048 goto err_desc_get;
1049
1050 xfer_len = len;
1051 block_ts = xfer_len >> reg_width;
1052 if (block_ts > max_block_ts) {
1053 block_ts = max_block_ts;
1054 xfer_len = max_block_ts << reg_width;
1055 }
1056 xfer_len = period_len;
1057 block_ts = period_len;
1058 mem_width = __ffs(data_width | mem | xfer_len);
1059 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
1060 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
1061
1062 ctlhi = axi_dma_prepare_ctlhi(chan);
1063 ctllo |= mem_width << CH_CTL_L_DST_WIDTH_POS;
1064
1065 write_desc_sar(desc, reg);
1066 write_desc_dar(desc, buf_addr + i * period_len);
1067 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
1068 desc->lli.block_ts_lo = period_len / 2;
1069 else if (reg_width >= DWAXIDMAC_TRANS_WIDTH_32)
1070 desc->lli.block_ts_lo = period_len / 4;
1071 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
1072 desc->lli.ctl_lo = cpu_to_le32(ctllo);
1073
1074 set_desc_src_master(desc);
1075 set_desc_src_master(desc);
1076
1077 // Manage transfer list (xfer_list)
1078 if (!first) {
1079 first = desc;
1080 } else {
1081 write_desc_llp(prev, desc->vd.tx.phys | lms);
1082 list_add_tail(&desc->xfer_list,
1083 &first->xfer_list);
1084 }
1085 prev = desc;
1086 if (i == ((buf_len / period_len) - 1))
1087 write_desc_llp(prev, first->vd.tx.phys | lms);
1088
1089 total_len += xfer_len;
1090
1091 // TODO: check if needed
1092 set_desc_last(desc);
1093 }
1094 break;
1095 default:
1096 return NULL;
1097 }
1098
1099 if (unlikely(!first))
1100 return NULL;
1101
1102 return vchan_tx_prep(&chan->vc, &first->vd, flags);
1103
1104 err_desc_get:
1105 if (first)
1106 axi_desc_put(first);
1107
1108 return NULL;
1109 }
1110
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 32396 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [intel-linux-intel-lts:5.4/yocto 40/1142] drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types)
@ 2021-05-17 16:38 kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2021-05-17 16:38 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 10525 bytes --]
tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto
head: eeb611e5394c56d45c5cc8f7dc484c9f19e93143
commit: 94e13c2880167751eb5cbbcb0e7be68ca83f0653 [40/1142] dmaengine: dw-axi-dma: support cyclic mode
config: i386-randconfig-s001-20210517 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/intel/linux-intel-lts/commit/94e13c2880167751eb5cbbcb0e7be68ca83f0653
git remote add intel-linux-intel-lts https://github.com/intel/linux-intel-lts.git
git fetch --no-tags intel-linux-intel-lts 5.4/yocto
git checkout 94e13c2880167751eb5cbbcb0e7be68ca83f0653
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned int @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: got unsigned int
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned int @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: got unsigned int
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned int @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: got unsigned int
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: sparse: incorrect type in argument 2 (different base types) @@ expected unsigned int [usertype] irq_mask @@ got restricted __le32 [usertype] status_lo @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: expected unsigned int [usertype] irq_mask
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: got restricted __le32 [usertype] status_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: sparse: invalid assignment: |=
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: left side has type restricted __le32
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: right side has type unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1111:22: sparse: sparse: context imbalance in 'axi_chan_handle_err' - different lock contexts for basic block
vim +993 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
912
913 static struct dma_async_tx_descriptor *
914 dw_chan_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr,
915 size_t buf_len, size_t period_len,
916 enum dma_transfer_direction direction,
917 unsigned long flags)
918 {
919 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
920 struct axi_dma_desc *first = NULL, *prev = NULL;
921 unsigned int reg_width;
922 unsigned int mem_width;
923 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
924 dma_addr_t reg;
925 u32 reg_value = 0;
926 unsigned int i = 0;
927 u32 ctllo, ctlhi;
928 size_t total_len = 0;
929 size_t block_ts, max_block_ts;
930 u8 lms = 0; // Select AXI0 master for LLI fetching
931 u32 offset;
932
933 if (unlikely(!is_slave_direction(direction)))
934 return NULL;
935
936 chan->direction = direction;
937 chan->cyclic = 0x1;
938
939 max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
940
941 axi_set_hw_channel(chan->chip, chan->hw_hs_num);
942
943 switch (direction) {
944 case DMA_MEM_TO_DEV:
945 reg_width = __ffs(chan->slave_config.dst_addr_width);
946
947 chan->reg_width = reg_width;
948 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
949 offset = DMAC_APB_HALFWORD_WR_CH_EN;
950 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
951 reg_value |= 0x1 << chan->id;
952 axi_dma_apb_iowrite32(chan->chip,
953 DMAC_APB_HALFWORD_WR_CH_EN, reg_value);
954 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
955 offset = DMAC_APB_BYTE_WR_CH_EN;
956 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
957 reg_value |= 0x1 << chan->id;
958 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
959 }
960 reg = chan->slave_config.dst_addr;
961
962 ctllo = axi_dma_prepare_ctllo(chan) |
963 reg_width << CH_CTL_L_DST_WIDTH_POS |
964 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
965 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
966
967 for (i = 0; i < buf_len / period_len; i++) {
968 struct axi_dma_desc *desc;
969 size_t xfer_len;
970 u32 mem, len;
971
972 mem_width = __ffs(data_width | mem | len);
973 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
974 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
975
976 xfer_len = period_len;
977 block_ts = period_len;
978
979 desc = axi_desc_get(chan);
980 if (unlikely(!desc))
981 goto err_desc_get;
982
983 if (block_ts > max_block_ts) {
984 block_ts = max_block_ts;
985 xfer_len = max_block_ts << mem_width;
986 }
987
988 ctlhi = axi_dma_prepare_ctlhi(chan);
989
990 ctllo |= mem_width << CH_CTL_L_SRC_WIDTH_POS;
991 write_desc_sar(desc, buf_addr + i * period_len);
992 write_desc_dar(desc, reg);
> 993 desc->lli.block_ts_lo = period_len / 4;
994 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
995 desc->lli.ctl_lo = cpu_to_le32(ctllo);
996
997 set_desc_src_master(desc);
998 set_desc_src_master(desc);
999
1000 // Manage transfer list (xfer_list)
1001 if (!first) {
1002 first = desc;
1003 } else {
1004 write_desc_llp(prev, desc->vd.tx.phys | lms);
1005 list_add_tail(&desc->xfer_list,
1006 &first->xfer_list);
1007 }
1008 prev = desc;
1009 if (i == ((buf_len / period_len) - 1))
1010 write_desc_llp(prev, first->vd.tx.phys | lms);
1011
1012 total_len += xfer_len;
1013
1014 set_desc_last(desc);
1015 }
1016 break;
1017 case DMA_DEV_TO_MEM:
1018 reg_width = __ffs(chan->slave_config.src_addr_width);
1019
1020 chan->reg_width = reg_width;
1021 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
1022 offset = DMAC_APB_HALFWORD_WR_CH_EN;
1023 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
1024 reg_value |= 0x1 << chan->id;
1025 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
1026 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
1027 offset = DMAC_APB_BYTE_WR_CH_EN;
1028 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
1029 reg_value |= 0x1 << chan->id;
1030 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
1031 }
1032 reg = chan->slave_config.src_addr;
1033 if (reg_width > DWAXIDMAC_TRANS_WIDTH_32)
1034 reg_width = DWAXIDMAC_TRANS_WIDTH_32;
1035 ctllo = axi_dma_prepare_ctllo(chan) |
1036 reg_width << CH_CTL_L_SRC_WIDTH_POS |
1037 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
1038 // Workaround
1039 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
1040
1041 for (i = 0; i < buf_len / period_len; i++) {
1042 struct axi_dma_desc *desc;
1043 size_t xfer_len;
1044 u32 mem, len;
1045
1046 desc = axi_desc_get(chan);
1047 if (unlikely(!desc))
1048 goto err_desc_get;
1049
1050 xfer_len = len;
1051 block_ts = xfer_len >> reg_width;
1052 if (block_ts > max_block_ts) {
1053 block_ts = max_block_ts;
1054 xfer_len = max_block_ts << reg_width;
1055 }
1056 xfer_len = period_len;
1057 block_ts = period_len;
1058 mem_width = __ffs(data_width | mem | xfer_len);
1059 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
1060 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
1061
1062 ctlhi = axi_dma_prepare_ctlhi(chan);
1063 ctllo |= mem_width << CH_CTL_L_DST_WIDTH_POS;
1064
1065 write_desc_sar(desc, reg);
1066 write_desc_dar(desc, buf_addr + i * period_len);
1067 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
1068 desc->lli.block_ts_lo = period_len / 2;
1069 else if (reg_width >= DWAXIDMAC_TRANS_WIDTH_32)
1070 desc->lli.block_ts_lo = period_len / 4;
1071 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
1072 desc->lli.ctl_lo = cpu_to_le32(ctllo);
1073
1074 set_desc_src_master(desc);
1075 set_desc_src_master(desc);
1076
1077 // Manage transfer list (xfer_list)
1078 if (!first) {
1079 first = desc;
1080 } else {
1081 write_desc_llp(prev, desc->vd.tx.phys | lms);
1082 list_add_tail(&desc->xfer_list,
1083 &first->xfer_list);
1084 }
1085 prev = desc;
1086 if (i == ((buf_len / period_len) - 1))
1087 write_desc_llp(prev, first->vd.tx.phys | lms);
1088
1089 total_len += xfer_len;
1090
1091 // TODO: check if needed
1092 set_desc_last(desc);
1093 }
1094 break;
1095 default:
1096 return NULL;
1097 }
1098
1099 if (unlikely(!first))
1100 return NULL;
1101
1102 return vchan_tx_prep(&chan->vc, &first->vd, flags);
1103
1104 err_desc_get:
1105 if (first)
1106 axi_desc_put(first);
1107
1108 return NULL;
1109 }
1110
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 37217 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [intel-linux-intel-lts:5.4/yocto 40/1142] drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types)
@ 2020-11-25 13:03 kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2020-11-25 13:03 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 10523 bytes --]
tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto
head: eeb611e5394c56d45c5cc8f7dc484c9f19e93143
commit: 94e13c2880167751eb5cbbcb0e7be68ca83f0653 [40/1142] dmaengine: dw-axi-dma: support cyclic mode
config: i386-randconfig-s001-20201125 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-151-g540c2c4b-dirty
# https://github.com/intel/linux-intel-lts/commit/94e13c2880167751eb5cbbcb0e7be68ca83f0653
git remote add intel-linux-intel-lts https://github.com/intel/linux-intel-lts.git
git fetch --no-tags intel-linux-intel-lts 5.4/yocto
git checkout 94e13c2880167751eb5cbbcb0e7be68ca83f0653
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
"sparse warnings: (new ones prefixed by >>)"
>> drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned int @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: expected restricted __le32 [usertype] block_ts_lo
>> drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: got unsigned int
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned int @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: got unsigned int
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned int @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: got unsigned int
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: sparse: incorrect type in argument 2 (different base types) @@ expected unsigned int [usertype] irq_mask @@ got restricted __le32 [usertype] status_lo @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: expected unsigned int [usertype] irq_mask
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: got restricted __le32 [usertype] status_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: sparse: invalid assignment: |=
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: left side has type restricted __le32
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: right side has type unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1111:22: sparse: sparse: context imbalance in 'axi_chan_handle_err' - different lock contexts for basic block
vim +993 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
912
913 static struct dma_async_tx_descriptor *
914 dw_chan_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr,
915 size_t buf_len, size_t period_len,
916 enum dma_transfer_direction direction,
917 unsigned long flags)
918 {
919 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
920 struct axi_dma_desc *first = NULL, *prev = NULL;
921 unsigned int reg_width;
922 unsigned int mem_width;
923 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
924 dma_addr_t reg;
925 u32 reg_value = 0;
926 unsigned int i = 0;
927 u32 ctllo, ctlhi;
928 size_t total_len = 0;
929 size_t block_ts, max_block_ts;
930 u8 lms = 0; // Select AXI0 master for LLI fetching
931 u32 offset;
932
933 if (unlikely(!is_slave_direction(direction)))
934 return NULL;
935
936 chan->direction = direction;
937 chan->cyclic = 0x1;
938
939 max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
940
941 axi_set_hw_channel(chan->chip, chan->hw_hs_num);
942
943 switch (direction) {
944 case DMA_MEM_TO_DEV:
945 reg_width = __ffs(chan->slave_config.dst_addr_width);
946
947 chan->reg_width = reg_width;
948 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
949 offset = DMAC_APB_HALFWORD_WR_CH_EN;
950 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
951 reg_value |= 0x1 << chan->id;
952 axi_dma_apb_iowrite32(chan->chip,
953 DMAC_APB_HALFWORD_WR_CH_EN, reg_value);
954 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
955 offset = DMAC_APB_BYTE_WR_CH_EN;
956 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
957 reg_value |= 0x1 << chan->id;
958 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
959 }
960 reg = chan->slave_config.dst_addr;
961
962 ctllo = axi_dma_prepare_ctllo(chan) |
963 reg_width << CH_CTL_L_DST_WIDTH_POS |
964 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
965 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
966
967 for (i = 0; i < buf_len / period_len; i++) {
968 struct axi_dma_desc *desc;
969 size_t xfer_len;
970 u32 mem, len;
971
972 mem_width = __ffs(data_width | mem | len);
973 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
974 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
975
976 xfer_len = period_len;
977 block_ts = period_len;
978
979 desc = axi_desc_get(chan);
980 if (unlikely(!desc))
981 goto err_desc_get;
982
983 if (block_ts > max_block_ts) {
984 block_ts = max_block_ts;
985 xfer_len = max_block_ts << mem_width;
986 }
987
988 ctlhi = axi_dma_prepare_ctlhi(chan);
989
990 ctllo |= mem_width << CH_CTL_L_SRC_WIDTH_POS;
991 write_desc_sar(desc, buf_addr + i * period_len);
992 write_desc_dar(desc, reg);
> 993 desc->lli.block_ts_lo = period_len / 4;
994 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
995 desc->lli.ctl_lo = cpu_to_le32(ctllo);
996
997 set_desc_src_master(desc);
998 set_desc_src_master(desc);
999
1000 // Manage transfer list (xfer_list)
1001 if (!first) {
1002 first = desc;
1003 } else {
1004 write_desc_llp(prev, desc->vd.tx.phys | lms);
1005 list_add_tail(&desc->xfer_list,
1006 &first->xfer_list);
1007 }
1008 prev = desc;
1009 if (i == ((buf_len / period_len) - 1))
1010 write_desc_llp(prev, first->vd.tx.phys | lms);
1011
1012 total_len += xfer_len;
1013
1014 set_desc_last(desc);
1015 }
1016 break;
1017 case DMA_DEV_TO_MEM:
1018 reg_width = __ffs(chan->slave_config.src_addr_width);
1019
1020 chan->reg_width = reg_width;
1021 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
1022 offset = DMAC_APB_HALFWORD_WR_CH_EN;
1023 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
1024 reg_value |= 0x1 << chan->id;
1025 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
1026 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
1027 offset = DMAC_APB_BYTE_WR_CH_EN;
1028 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
1029 reg_value |= 0x1 << chan->id;
1030 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
1031 }
1032 reg = chan->slave_config.src_addr;
1033 if (reg_width > DWAXIDMAC_TRANS_WIDTH_32)
1034 reg_width = DWAXIDMAC_TRANS_WIDTH_32;
1035 ctllo = axi_dma_prepare_ctllo(chan) |
1036 reg_width << CH_CTL_L_SRC_WIDTH_POS |
1037 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
1038 // Workaround
1039 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
1040
1041 for (i = 0; i < buf_len / period_len; i++) {
1042 struct axi_dma_desc *desc;
1043 size_t xfer_len;
1044 u32 mem, len;
1045
1046 desc = axi_desc_get(chan);
1047 if (unlikely(!desc))
1048 goto err_desc_get;
1049
1050 xfer_len = len;
1051 block_ts = xfer_len >> reg_width;
1052 if (block_ts > max_block_ts) {
1053 block_ts = max_block_ts;
1054 xfer_len = max_block_ts << reg_width;
1055 }
1056 xfer_len = period_len;
1057 block_ts = period_len;
1058 mem_width = __ffs(data_width | mem | xfer_len);
1059 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
1060 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
1061
1062 ctlhi = axi_dma_prepare_ctlhi(chan);
1063 ctllo |= mem_width << CH_CTL_L_DST_WIDTH_POS;
1064
1065 write_desc_sar(desc, reg);
1066 write_desc_dar(desc, buf_addr + i * period_len);
1067 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
1068 desc->lli.block_ts_lo = period_len / 2;
1069 else if (reg_width >= DWAXIDMAC_TRANS_WIDTH_32)
1070 desc->lli.block_ts_lo = period_len / 4;
1071 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
1072 desc->lli.ctl_lo = cpu_to_le32(ctllo);
1073
1074 set_desc_src_master(desc);
1075 set_desc_src_master(desc);
1076
1077 // Manage transfer list (xfer_list)
1078 if (!first) {
1079 first = desc;
1080 } else {
1081 write_desc_llp(prev, desc->vd.tx.phys | lms);
1082 list_add_tail(&desc->xfer_list,
1083 &first->xfer_list);
1084 }
1085 prev = desc;
1086 if (i == ((buf_len / period_len) - 1))
1087 write_desc_llp(prev, first->vd.tx.phys | lms);
1088
1089 total_len += xfer_len;
1090
1091 // TODO: check if needed
1092 set_desc_last(desc);
1093 }
1094 break;
1095 default:
1096 return NULL;
1097 }
1098
1099 if (unlikely(!first))
1100 return NULL;
1101
1102 return vchan_tx_prep(&chan->vc, &first->vd, flags);
1103
1104 err_desc_get:
1105 if (first)
1106 axi_desc_put(first);
1107
1108 return NULL;
1109 }
1110
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 37340 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [intel-linux-intel-lts:5.4/yocto 40/1142] drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types)
@ 2020-11-19 1:16 kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2020-11-19 1:16 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 10533 bytes --]
tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto
head: eeb611e5394c56d45c5cc8f7dc484c9f19e93143
commit: 94e13c2880167751eb5cbbcb0e7be68ca83f0653 [40/1142] dmaengine: dw-axi-dma: support cyclic mode
config: x86_64-randconfig-s022-20201118 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-123-g626c4742-dirty
# https://github.com/intel/linux-intel-lts/commit/94e13c2880167751eb5cbbcb0e7be68ca83f0653
git remote add intel-linux-intel-lts https://github.com/intel/linux-intel-lts.git
git fetch --no-tags intel-linux-intel-lts 5.4/yocto
git checkout 94e13c2880167751eb5cbbcb0e7be68ca83f0653
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
"sparse warnings: (new ones prefixed by >>)"
>> drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned long @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: expected restricted __le32 [usertype] block_ts_lo
>> drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: got unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned long @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: got unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned long @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: expected restricted __le32 [usertype] block_ts_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: got unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: sparse: incorrect type in argument 2 (different base types) @@ expected unsigned int [usertype] irq_mask @@ got restricted __le32 [usertype] status_lo @@
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: expected unsigned int [usertype] irq_mask
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: got restricted __le32 [usertype] status_lo
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: sparse: invalid assignment: |=
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: left side has type restricted __le32
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: right side has type unsigned long
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1111:22: sparse: sparse: context imbalance in 'axi_chan_handle_err' - different lock contexts for basic block
vim +993 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
912
913 static struct dma_async_tx_descriptor *
914 dw_chan_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr,
915 size_t buf_len, size_t period_len,
916 enum dma_transfer_direction direction,
917 unsigned long flags)
918 {
919 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
920 struct axi_dma_desc *first = NULL, *prev = NULL;
921 unsigned int reg_width;
922 unsigned int mem_width;
923 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
924 dma_addr_t reg;
925 u32 reg_value = 0;
926 unsigned int i = 0;
927 u32 ctllo, ctlhi;
928 size_t total_len = 0;
929 size_t block_ts, max_block_ts;
930 u8 lms = 0; // Select AXI0 master for LLI fetching
931 u32 offset;
932
933 if (unlikely(!is_slave_direction(direction)))
934 return NULL;
935
936 chan->direction = direction;
937 chan->cyclic = 0x1;
938
939 max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
940
941 axi_set_hw_channel(chan->chip, chan->hw_hs_num);
942
943 switch (direction) {
944 case DMA_MEM_TO_DEV:
945 reg_width = __ffs(chan->slave_config.dst_addr_width);
946
947 chan->reg_width = reg_width;
948 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
949 offset = DMAC_APB_HALFWORD_WR_CH_EN;
950 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
951 reg_value |= 0x1 << chan->id;
952 axi_dma_apb_iowrite32(chan->chip,
953 DMAC_APB_HALFWORD_WR_CH_EN, reg_value);
954 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
955 offset = DMAC_APB_BYTE_WR_CH_EN;
956 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
957 reg_value |= 0x1 << chan->id;
958 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
959 }
960 reg = chan->slave_config.dst_addr;
961
962 ctllo = axi_dma_prepare_ctllo(chan) |
963 reg_width << CH_CTL_L_DST_WIDTH_POS |
964 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
965 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
966
967 for (i = 0; i < buf_len / period_len; i++) {
968 struct axi_dma_desc *desc;
969 size_t xfer_len;
970 u32 mem, len;
971
972 mem_width = __ffs(data_width | mem | len);
973 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
974 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
975
976 xfer_len = period_len;
977 block_ts = period_len;
978
979 desc = axi_desc_get(chan);
980 if (unlikely(!desc))
981 goto err_desc_get;
982
983 if (block_ts > max_block_ts) {
984 block_ts = max_block_ts;
985 xfer_len = max_block_ts << mem_width;
986 }
987
988 ctlhi = axi_dma_prepare_ctlhi(chan);
989
990 ctllo |= mem_width << CH_CTL_L_SRC_WIDTH_POS;
991 write_desc_sar(desc, buf_addr + i * period_len);
992 write_desc_dar(desc, reg);
> 993 desc->lli.block_ts_lo = period_len / 4;
994 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
995 desc->lli.ctl_lo = cpu_to_le32(ctllo);
996
997 set_desc_src_master(desc);
998 set_desc_src_master(desc);
999
1000 // Manage transfer list (xfer_list)
1001 if (!first) {
1002 first = desc;
1003 } else {
1004 write_desc_llp(prev, desc->vd.tx.phys | lms);
1005 list_add_tail(&desc->xfer_list,
1006 &first->xfer_list);
1007 }
1008 prev = desc;
1009 if (i == ((buf_len / period_len) - 1))
1010 write_desc_llp(prev, first->vd.tx.phys | lms);
1011
1012 total_len += xfer_len;
1013
1014 set_desc_last(desc);
1015 }
1016 break;
1017 case DMA_DEV_TO_MEM:
1018 reg_width = __ffs(chan->slave_config.src_addr_width);
1019
1020 chan->reg_width = reg_width;
1021 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
1022 offset = DMAC_APB_HALFWORD_WR_CH_EN;
1023 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
1024 reg_value |= 0x1 << chan->id;
1025 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
1026 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
1027 offset = DMAC_APB_BYTE_WR_CH_EN;
1028 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
1029 reg_value |= 0x1 << chan->id;
1030 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
1031 }
1032 reg = chan->slave_config.src_addr;
1033 if (reg_width > DWAXIDMAC_TRANS_WIDTH_32)
1034 reg_width = DWAXIDMAC_TRANS_WIDTH_32;
1035 ctllo = axi_dma_prepare_ctllo(chan) |
1036 reg_width << CH_CTL_L_SRC_WIDTH_POS |
1037 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
1038 // Workaround
1039 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
1040
1041 for (i = 0; i < buf_len / period_len; i++) {
1042 struct axi_dma_desc *desc;
1043 size_t xfer_len;
1044 u32 mem, len;
1045
1046 desc = axi_desc_get(chan);
1047 if (unlikely(!desc))
1048 goto err_desc_get;
1049
1050 xfer_len = len;
1051 block_ts = xfer_len >> reg_width;
1052 if (block_ts > max_block_ts) {
1053 block_ts = max_block_ts;
1054 xfer_len = max_block_ts << reg_width;
1055 }
1056 xfer_len = period_len;
1057 block_ts = period_len;
1058 mem_width = __ffs(data_width | mem | xfer_len);
1059 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
1060 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
1061
1062 ctlhi = axi_dma_prepare_ctlhi(chan);
1063 ctllo |= mem_width << CH_CTL_L_DST_WIDTH_POS;
1064
1065 write_desc_sar(desc, reg);
1066 write_desc_dar(desc, buf_addr + i * period_len);
1067 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
1068 desc->lli.block_ts_lo = period_len / 2;
1069 else if (reg_width >= DWAXIDMAC_TRANS_WIDTH_32)
1070 desc->lli.block_ts_lo = period_len / 4;
1071 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
1072 desc->lli.ctl_lo = cpu_to_le32(ctllo);
1073
1074 set_desc_src_master(desc);
1075 set_desc_src_master(desc);
1076
1077 // Manage transfer list (xfer_list)
1078 if (!first) {
1079 first = desc;
1080 } else {
1081 write_desc_llp(prev, desc->vd.tx.phys | lms);
1082 list_add_tail(&desc->xfer_list,
1083 &first->xfer_list);
1084 }
1085 prev = desc;
1086 if (i == ((buf_len / period_len) - 1))
1087 write_desc_llp(prev, first->vd.tx.phys | lms);
1088
1089 total_len += xfer_len;
1090
1091 // TODO: check if needed
1092 set_desc_last(desc);
1093 }
1094 break;
1095 default:
1096 return NULL;
1097 }
1098
1099 if (unlikely(!first))
1100 return NULL;
1101
1102 return vchan_tx_prep(&chan->vc, &first->vd, flags);
1103
1104 err_desc_get:
1105 if (first)
1106 axi_desc_put(first);
1107
1108 return NULL;
1109 }
1110
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 33593 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-09-04 20:09 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-10 14:12 [intel-linux-intel-lts:5.4/yocto 40/1142] drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: sparse: incorrect type in assignment (different base types) kernel test robot
-- strict thread matches above, loose matches on Subject: below --
2021-09-04 20:09 kernel test robot
2021-08-12 22:24 kernel test robot
2021-06-19 17:42 kernel test robot
2021-05-17 16:38 kernel test robot
2020-11-25 13:03 kernel test robot
2020-11-19 1:16 kernel test robot
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.