From: Matthew Brost <matthew.brost@intel.com> To: John Harrison <john.c.harrison@intel.com> Cc: intel-gfx@lists.freedesktop.org, daniele.ceraolospurio@intel.com, dri-devel@lists.freedesktop.org Subject: Re: [PATCH 17/51] drm/i915/guc: Add several request trace points Date: Mon, 19 Jul 2021 19:10:54 -0700 [thread overview] Message-ID: <20210720021054.GA16001@sdutt-i7> (raw) In-Reply-To: <e8776ea0-84b3-fd8b-fc17-1f634d1a083a@intel.com> On Mon, Jul 19, 2021 at 06:27:06PM -0700, John Harrison wrote: > On 7/16/2021 13:16, Matthew Brost wrote: > > Add trace points for request dependencies and GuC submit. Extended > > existing request trace points to include submit fence value,, guc_id, > Still has misplaced commas. > > Also, Tvrtko has a bunch of comments/questions on the previous version that > need to be addressed. > Replied. Landed on just deleting the contentious, albiet very useful, trace points. Will revisit in the future. Matt > John. > > > and ring tail value. > > > > v2: Fix white space alignment in i915_request_add trace point > > > > Cc: John Harrison <john.c.harrison@intel.com> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > > Reviewed-by: John Harrison <John.C.Harrison@Intel.com> > > --- > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 ++ > > drivers/gpu/drm/i915/i915_request.c | 3 ++ > > drivers/gpu/drm/i915/i915_trace.h | 43 +++++++++++++++++-- > > 3 files changed, 45 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > index a2af7e17dcc2..480fb2184ecf 100644 > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > @@ -417,6 +417,7 @@ static int guc_dequeue_one_context(struct intel_guc *guc) > > guc->stalled_request = last; > > return false; > > } > > + trace_i915_request_guc_submit(last); > > } > > guc->stalled_request = NULL; > > @@ -637,6 +638,8 @@ static int guc_bypass_tasklet_submit(struct intel_guc *guc, > > ret = guc_add_request(guc, rq); > > if (ret == -EBUSY) > > guc->stalled_request = rq; > > + else > > + trace_i915_request_guc_submit(rq); > > return ret; > > } > > diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c > > index 2b2b63cba06c..01aa3d1ee2b1 100644 > > --- a/drivers/gpu/drm/i915/i915_request.c > > +++ b/drivers/gpu/drm/i915/i915_request.c > > @@ -1319,6 +1319,9 @@ __i915_request_await_execution(struct i915_request *to, > > return err; > > } > > + trace_i915_request_dep_to(to); > > + trace_i915_request_dep_from(from); > > + > > /* Couple the dependency tree for PI on this exposed to->fence */ > > if (to->engine->sched_engine->schedule) { > > err = i915_sched_node_add_dependency(&to->sched, > > diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h > > index 6778ad2a14a4..ea41d069bf7d 100644 > > --- a/drivers/gpu/drm/i915/i915_trace.h > > +++ b/drivers/gpu/drm/i915/i915_trace.h > > @@ -794,30 +794,50 @@ DECLARE_EVENT_CLASS(i915_request, > > TP_STRUCT__entry( > > __field(u32, dev) > > __field(u64, ctx) > > + __field(u32, guc_id) > > __field(u16, class) > > __field(u16, instance) > > __field(u32, seqno) > > + __field(u32, tail) > > ), > > TP_fast_assign( > > __entry->dev = rq->engine->i915->drm.primary->index; > > __entry->class = rq->engine->uabi_class; > > __entry->instance = rq->engine->uabi_instance; > > + __entry->guc_id = rq->context->guc_id; > > __entry->ctx = rq->fence.context; > > __entry->seqno = rq->fence.seqno; > > + __entry->tail = rq->tail; > > ), > > - TP_printk("dev=%u, engine=%u:%u, ctx=%llu, seqno=%u", > > + TP_printk("dev=%u, engine=%u:%u, guc_id=%u, ctx=%llu, seqno=%u, tail=%u", > > __entry->dev, __entry->class, __entry->instance, > > - __entry->ctx, __entry->seqno) > > + __entry->guc_id, __entry->ctx, __entry->seqno, > > + __entry->tail) > > ); > > DEFINE_EVENT(i915_request, i915_request_add, > > - TP_PROTO(struct i915_request *rq), > > - TP_ARGS(rq) > > + TP_PROTO(struct i915_request *rq), > > + TP_ARGS(rq) > > ); > > #if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS) > > +DEFINE_EVENT(i915_request, i915_request_dep_to, > > + TP_PROTO(struct i915_request *rq), > > + TP_ARGS(rq) > > +); > > + > > +DEFINE_EVENT(i915_request, i915_request_dep_from, > > + TP_PROTO(struct i915_request *rq), > > + TP_ARGS(rq) > > +); > > + > > +DEFINE_EVENT(i915_request, i915_request_guc_submit, > > + TP_PROTO(struct i915_request *rq), > > + TP_ARGS(rq) > > +); > > + > > DEFINE_EVENT(i915_request, i915_request_submit, > > TP_PROTO(struct i915_request *rq), > > TP_ARGS(rq) > > @@ -887,6 +907,21 @@ TRACE_EVENT(i915_request_out, > > #else > > #if !defined(TRACE_HEADER_MULTI_READ) > > +static inline void > > +trace_i915_request_dep_to(struct i915_request *rq) > > +{ > > +} > > + > > +static inline void > > +trace_i915_request_dep_from(struct i915_request *rq) > > +{ > > +} > > + > > +static inline void > > +trace_i915_request_guc_submit(struct i915_request *rq) > > +{ > > +} > > + > > static inline void > > trace_i915_request_submit(struct i915_request *rq) > > { >
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: John Harrison <john.c.harrison@intel.com> Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 17/51] drm/i915/guc: Add several request trace points Date: Mon, 19 Jul 2021 19:10:54 -0700 [thread overview] Message-ID: <20210720021054.GA16001@sdutt-i7> (raw) In-Reply-To: <e8776ea0-84b3-fd8b-fc17-1f634d1a083a@intel.com> On Mon, Jul 19, 2021 at 06:27:06PM -0700, John Harrison wrote: > On 7/16/2021 13:16, Matthew Brost wrote: > > Add trace points for request dependencies and GuC submit. Extended > > existing request trace points to include submit fence value,, guc_id, > Still has misplaced commas. > > Also, Tvrtko has a bunch of comments/questions on the previous version that > need to be addressed. > Replied. Landed on just deleting the contentious, albiet very useful, trace points. Will revisit in the future. Matt > John. > > > and ring tail value. > > > > v2: Fix white space alignment in i915_request_add trace point > > > > Cc: John Harrison <john.c.harrison@intel.com> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > > Reviewed-by: John Harrison <John.C.Harrison@Intel.com> > > --- > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 ++ > > drivers/gpu/drm/i915/i915_request.c | 3 ++ > > drivers/gpu/drm/i915/i915_trace.h | 43 +++++++++++++++++-- > > 3 files changed, 45 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > index a2af7e17dcc2..480fb2184ecf 100644 > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > @@ -417,6 +417,7 @@ static int guc_dequeue_one_context(struct intel_guc *guc) > > guc->stalled_request = last; > > return false; > > } > > + trace_i915_request_guc_submit(last); > > } > > guc->stalled_request = NULL; > > @@ -637,6 +638,8 @@ static int guc_bypass_tasklet_submit(struct intel_guc *guc, > > ret = guc_add_request(guc, rq); > > if (ret == -EBUSY) > > guc->stalled_request = rq; > > + else > > + trace_i915_request_guc_submit(rq); > > return ret; > > } > > diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c > > index 2b2b63cba06c..01aa3d1ee2b1 100644 > > --- a/drivers/gpu/drm/i915/i915_request.c > > +++ b/drivers/gpu/drm/i915/i915_request.c > > @@ -1319,6 +1319,9 @@ __i915_request_await_execution(struct i915_request *to, > > return err; > > } > > + trace_i915_request_dep_to(to); > > + trace_i915_request_dep_from(from); > > + > > /* Couple the dependency tree for PI on this exposed to->fence */ > > if (to->engine->sched_engine->schedule) { > > err = i915_sched_node_add_dependency(&to->sched, > > diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h > > index 6778ad2a14a4..ea41d069bf7d 100644 > > --- a/drivers/gpu/drm/i915/i915_trace.h > > +++ b/drivers/gpu/drm/i915/i915_trace.h > > @@ -794,30 +794,50 @@ DECLARE_EVENT_CLASS(i915_request, > > TP_STRUCT__entry( > > __field(u32, dev) > > __field(u64, ctx) > > + __field(u32, guc_id) > > __field(u16, class) > > __field(u16, instance) > > __field(u32, seqno) > > + __field(u32, tail) > > ), > > TP_fast_assign( > > __entry->dev = rq->engine->i915->drm.primary->index; > > __entry->class = rq->engine->uabi_class; > > __entry->instance = rq->engine->uabi_instance; > > + __entry->guc_id = rq->context->guc_id; > > __entry->ctx = rq->fence.context; > > __entry->seqno = rq->fence.seqno; > > + __entry->tail = rq->tail; > > ), > > - TP_printk("dev=%u, engine=%u:%u, ctx=%llu, seqno=%u", > > + TP_printk("dev=%u, engine=%u:%u, guc_id=%u, ctx=%llu, seqno=%u, tail=%u", > > __entry->dev, __entry->class, __entry->instance, > > - __entry->ctx, __entry->seqno) > > + __entry->guc_id, __entry->ctx, __entry->seqno, > > + __entry->tail) > > ); > > DEFINE_EVENT(i915_request, i915_request_add, > > - TP_PROTO(struct i915_request *rq), > > - TP_ARGS(rq) > > + TP_PROTO(struct i915_request *rq), > > + TP_ARGS(rq) > > ); > > #if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS) > > +DEFINE_EVENT(i915_request, i915_request_dep_to, > > + TP_PROTO(struct i915_request *rq), > > + TP_ARGS(rq) > > +); > > + > > +DEFINE_EVENT(i915_request, i915_request_dep_from, > > + TP_PROTO(struct i915_request *rq), > > + TP_ARGS(rq) > > +); > > + > > +DEFINE_EVENT(i915_request, i915_request_guc_submit, > > + TP_PROTO(struct i915_request *rq), > > + TP_ARGS(rq) > > +); > > + > > DEFINE_EVENT(i915_request, i915_request_submit, > > TP_PROTO(struct i915_request *rq), > > TP_ARGS(rq) > > @@ -887,6 +907,21 @@ TRACE_EVENT(i915_request_out, > > #else > > #if !defined(TRACE_HEADER_MULTI_READ) > > +static inline void > > +trace_i915_request_dep_to(struct i915_request *rq) > > +{ > > +} > > + > > +static inline void > > +trace_i915_request_dep_from(struct i915_request *rq) > > +{ > > +} > > + > > +static inline void > > +trace_i915_request_guc_submit(struct i915_request *rq) > > +{ > > +} > > + > > static inline void > > trace_i915_request_submit(struct i915_request *rq) > > { > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-20 2:22 UTC|newest] Thread overview: 221+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-16 20:16 [PATCH 00/51] GuC submission support Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 01/51] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 02/51] drm/i915/guc: Remove GuC stage descriptor, add LRC descriptor Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 03/51] drm/i915/guc: Add LRC descriptor context lookup array Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 04/51] drm/i915/guc: Implement GuC submission tasklet Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-19 23:01 ` John Harrison 2021-07-19 23:01 ` [Intel-gfx] " John Harrison 2021-07-19 22:55 ` Matthew Brost 2021-07-19 22:55 ` [Intel-gfx] " Matthew Brost 2021-07-20 0:26 ` John Harrison 2021-07-20 0:26 ` [Intel-gfx] " John Harrison 2021-07-16 20:16 ` [PATCH 05/51] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 06/51] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 0:23 ` John Harrison 2021-07-20 0:23 ` [Intel-gfx] " John Harrison 2021-07-20 2:45 ` Matthew Brost 2021-07-20 2:45 ` [Intel-gfx] " Matthew Brost 2021-07-20 0:51 ` Daniele Ceraolo Spurio 2021-07-20 0:51 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-20 4:04 ` Matthew Brost 2021-07-20 4:04 ` [Intel-gfx] " Matthew Brost 2021-07-21 23:51 ` Daniele Ceraolo Spurio 2021-07-21 23:51 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-22 7:57 ` Michal Wajdeczko 2021-07-22 7:57 ` Michal Wajdeczko 2021-07-22 15:48 ` Matthew Brost 2021-07-22 15:48 ` Matthew Brost 2021-07-16 20:16 ` [PATCH 07/51] drm/i915/guc: Insert fence on context when deregistering Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 08/51] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 09/51] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 10/51] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 11/51] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 12/51] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-19 23:46 ` Daniele Ceraolo Spurio 2021-07-19 23:46 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-20 2:48 ` Matthew Brost 2021-07-20 2:48 ` [Intel-gfx] " Matthew Brost 2021-07-20 2:50 ` Matthew Brost 2021-07-20 2:50 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 13/51] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 0:33 ` John Harrison 2021-07-20 0:33 ` [Intel-gfx] " John Harrison 2021-07-16 20:16 ` [PATCH 14/51] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 15/51] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 1:03 ` John Harrison 2021-07-20 1:03 ` [Intel-gfx] " John Harrison 2021-07-20 1:53 ` Matthew Brost 2021-07-20 1:53 ` [Intel-gfx] " Matthew Brost 2021-07-20 19:49 ` John Harrison 2021-07-20 19:49 ` [Intel-gfx] " John Harrison 2021-07-16 20:16 ` [PATCH 16/51] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 1:13 ` John Harrison 2021-07-20 1:13 ` [Intel-gfx] " John Harrison 2021-07-16 20:16 ` [PATCH 17/51] drm/i915/guc: Add several request trace points Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 1:27 ` John Harrison 2021-07-20 1:27 ` [Intel-gfx] " John Harrison 2021-07-20 2:10 ` Matthew Brost [this message] 2021-07-20 2:10 ` Matthew Brost 2021-07-16 20:16 ` [PATCH 18/51] drm/i915: Add intel_context tracing Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 19/51] drm/i915/guc: GuC virtual engines Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-19 23:33 ` Daniele Ceraolo Spurio 2021-07-19 23:33 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-19 23:27 ` Matthew Brost 2021-07-19 23:27 ` [Intel-gfx] " Matthew Brost 2021-07-19 23:42 ` Daniele Ceraolo Spurio 2021-07-19 23:42 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-19 23:32 ` Matthew Brost 2021-07-19 23:32 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 20/51] drm/i915: Track 'serial' counts for " Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 1:28 ` John Harrison 2021-07-20 1:28 ` [Intel-gfx] " John Harrison 2021-07-20 1:54 ` Matthew Brost 2021-07-20 1:54 ` [Intel-gfx] " Matthew Brost 2021-07-20 16:47 ` Matthew Brost 2021-07-20 16:47 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 21/51] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 22/51] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 23/51] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 19:45 ` John Harrison 2021-07-20 19:45 ` [Intel-gfx] " John Harrison 2021-07-22 12:46 ` Tvrtko Ursulin 2021-07-22 12:46 ` Tvrtko Ursulin 2021-07-26 22:25 ` Matthew Brost 2021-07-26 22:25 ` Matthew Brost 2021-07-16 20:16 ` [PATCH 24/51] drm/i915: Add i915_sched_engine destroy vfunc Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 19:55 ` John Harrison 2021-07-20 19:55 ` [Intel-gfx] " John Harrison 2021-07-20 19:53 ` Matthew Brost 2021-07-20 19:53 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 25/51] drm/i915: Move active request tracking to a vfunc Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 20:05 ` John Harrison 2021-07-20 20:05 ` [Intel-gfx] " John Harrison 2021-07-16 20:16 ` [PATCH 26/51] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 20:19 ` John Harrison 2021-07-20 20:19 ` [Intel-gfx] " John Harrison 2021-07-20 20:59 ` Matthew Brost 2021-07-20 20:59 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 27/51] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 28/51] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 29/51] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 30/51] drm/i915/guc: Handle context reset notification Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-20 20:29 ` John Harrison 2021-07-20 20:29 ` [Intel-gfx] " John Harrison 2021-07-20 20:38 ` Matthew Brost 2021-07-20 20:38 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 31/51] drm/i915/guc: Handle engine reset failure notification Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 32/51] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 33/51] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-22 4:47 ` Matthew Brost 2021-07-22 4:47 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 34/51] drm/i915/guc: Don't complain about reset races Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 35/51] drm/i915/guc: Enable GuC engine reset Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 36/51] drm/i915/guc: Capture error state on context reset Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 37/51] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 38/51] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 39/51] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:04 ` Matthew Brost 2021-07-16 20:04 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 40/51] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 41/51] drm/i915/guc: Add golden context to GuC ADS Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-19 17:24 ` Matthew Brost 2021-07-19 17:24 ` Matthew Brost 2021-07-19 18:25 ` John Harrison 2021-07-19 18:25 ` John Harrison 2021-07-19 18:30 ` Matthew Brost 2021-07-19 18:30 ` Matthew Brost 2021-07-16 20:17 ` [PATCH 42/51] drm/i915/guc: Implement banned contexts for GuC submission Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-20 21:41 ` John Harrison 2021-07-20 21:41 ` [Intel-gfx] " John Harrison 2021-07-16 20:17 ` [PATCH 43/51] drm/i915/guc: Support request cancellation Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-22 19:56 ` Daniele Ceraolo Spurio 2021-07-22 19:56 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-22 20:13 ` Matthew Brost 2021-07-22 20:13 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 44/51] drm/i915/selftest: Better error reporting from hangcheck selftest Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:13 ` Matthew Brost 2021-07-16 20:13 ` Matthew Brost 2021-07-16 20:17 ` [PATCH 45/51] drm/i915/selftest: Fix workarounds selftest for GuC submission Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-20 17:14 ` Matthew Brost 2021-07-20 17:14 ` Matthew Brost 2021-07-16 20:17 ` [PATCH 46/51] drm/i915/selftest: Fix MOCS " Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 23:57 ` Matthew Brost 2021-07-16 23:57 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 47/51] drm/i915/selftest: Increase some timeouts in live_requests Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-20 21:46 ` John Harrison 2021-07-20 21:46 ` [Intel-gfx] " John Harrison 2021-07-22 8:13 ` Tvrtko Ursulin 2021-07-22 8:13 ` Tvrtko Ursulin 2021-07-16 20:17 ` [PATCH 48/51] drm/i915/selftest: Fix hangcheck self test for GuC submission Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 23:43 ` Matthew Brost 2021-07-16 23:43 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 49/51] drm/i915/selftest: Bump selftest timeouts for hangcheck Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 22:23 ` Matthew Brost 2021-07-16 22:23 ` [Intel-gfx] " Matthew Brost 2021-07-22 8:17 ` Tvrtko Ursulin 2021-07-22 8:17 ` Tvrtko Ursulin 2021-07-16 20:17 ` [PATCH 50/51] drm/i915/guc: Implement GuC priority management Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-22 20:26 ` Daniele Ceraolo Spurio 2021-07-22 20:26 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-22 21:38 ` Matthew Brost 2021-07-22 21:38 ` [Intel-gfx] " Matthew Brost 2021-07-22 21:50 ` Daniele Ceraolo Spurio 2021-07-22 21:50 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-22 21:55 ` Matthew Brost 2021-07-22 21:55 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 51/51] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-17 1:10 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev3) Patchwork 2021-07-19 9:06 ` [Intel-gfx] [PATCH 00/51] GuC submission support Tvrtko Ursulin 2021-07-19 9:06 ` Tvrtko Ursulin
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