From: Dmitry Osipenko <digetx@gmail.com> To: "Thierry Reding" <thierry.reding@gmail.com>, "Jonathan Hunter" <jonathanh@nvidia.com>, "Ulf Hansson" <ulf.hansson@linaro.org>, "Viresh Kumar" <vireshk@kernel.org>, "Stephen Boyd" <sboyd@kernel.org>, "Peter De Schrijver" <pdeschrijver@nvidia.com>, "Mikko Perttunen" <mperttunen@nvidia.com>, "Peter Chen" <peter.chen@kernel.org>, "Mark Brown" <broonie@kernel.org>, "Lee Jones" <lee.jones@linaro.org>, "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>, "Nishanth Menon" <nm@ti.com>, "Vignesh Raghavendra" <vigneshr@ti.com>, "Richard Weinberger" <richard@nod.at>, "Miquel Raynal" <miquel.raynal@bootlin.com>, "Lucas Stach" <dev@lynxeye.de>, "Stefan Agner" <stefan@agner.ch>, "Adrian Hunter" <adrian.hunter@intel.com>, "Mauro Carvalho Chehab" <mchehab@kernel.org>, "Rob Herring" <robh+dt@kernel.org>, "Michael Turquette" <mturquette@baylibre.com> Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-staging@lists.linux.dev, linux-spi@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mtd@lists.infradead.org, linux-mmc@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v8 08/34] dt-bindings: host1x: Document OPP and power domain properties Date: Tue, 17 Aug 2021 04:27:28 +0300 [thread overview] Message-ID: <20210817012754.8710-9-digetx@gmail.com> (raw) In-Reply-To: <20210817012754.8710-1-digetx@gmail.com> Document new DVFS OPP table and power domain properties of the Host1x bus and devices sitting on the bus. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../display/tegra/nvidia,tegra20-host1x.txt | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 8a6d3e1ee306..62861a8fb5c6 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -20,6 +20,18 @@ Required properties: - reset-names: Must include the following entries: - host1x +Optional properties: +- operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. + +For each opp entry in 'operating-points-v2' table of host1x and its modules: +- opp-supported-hw: One bitfield indicating: + On Tegra20: SoC process ID mask + On Tegra30+: SoC speedo ID mask + + A bitwise AND is performed against the value and if any bit + matches, the OPP gets enabled. + Each host1x client module having to perform DMA through the Memory Controller should have the interconnect endpoints set to the Memory Client and External Memory respectively. @@ -45,6 +57,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to MPE power domain. - vi: video input @@ -128,6 +142,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to VENC power domain. - epp: encoder pre-processor @@ -147,6 +163,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. - isp: image signal processor @@ -166,6 +184,7 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - power-domains: Phandle to VENC or core power domain. - gr2d: 2D graphics engine @@ -185,6 +204,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. - gr3d: 3D graphics engine @@ -209,6 +230,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandles to 3D or core power domain. - dc: display controller @@ -241,6 +264,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to core power domain. - hdmi: High Definition Multimedia Interface @@ -267,6 +292,7 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - operating-points-v2: See ../bindings/opp/opp.txt for details. - tvo: TV encoder output @@ -277,6 +303,10 @@ of the following host1x client modules: - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. + Optional properties: + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to core power domain. + - dsi: display serial interface Required properties: @@ -305,6 +335,7 @@ of the following host1x client modules: - nvidia,panel: phandle of a display panel - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang up with in order to support up to 8 data lanes + - operating-points-v2: See ../bindings/opp/opp.txt for details. - sor: serial output resource @@ -408,6 +439,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_HOST1X>; resets = <&tegra_car 28>; reset-names = "host1x"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; #address-cells = <1>; #size-cells = <1>; @@ -421,6 +454,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; vi@54080000 { @@ -429,6 +464,7 @@ Example: interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + operating-points-v2 = <&dvfs_opp_table>; clocks = <&tegra_car TEGRA210_CLK_VI>; power-domains = <&pd_venc>; @@ -510,6 +546,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; isp { @@ -528,6 +566,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; gr3d { @@ -536,6 +576,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; dc@54200000 { @@ -547,6 +589,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, <&mc TEGRA20_MC_DISPLAY0B &emc>, @@ -571,6 +615,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, <&mc TEGRA20_MC_DISPLAY0BB &emc>, @@ -596,6 +642,7 @@ Example: resets = <&tegra_car 51>; reset-names = "hdmi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; tvo { @@ -604,6 +651,7 @@ Example: interrupts = <0 76 0x04>; clocks = <&tegra_car TEGRA20_CLK_TVO>; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; dsi { @@ -615,6 +663,7 @@ Example: resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; }; -- 2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com> To: "Thierry Reding" <thierry.reding@gmail.com>, "Jonathan Hunter" <jonathanh@nvidia.com>, "Ulf Hansson" <ulf.hansson@linaro.org>, "Viresh Kumar" <vireshk@kernel.org>, "Stephen Boyd" <sboyd@kernel.org>, "Peter De Schrijver" <pdeschrijver@nvidia.com>, "Mikko Perttunen" <mperttunen@nvidia.com>, "Peter Chen" <peter.chen@kernel.org>, "Mark Brown" <broonie@kernel.org>, "Lee Jones" <lee.jones@linaro.org>, "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>, "Nishanth Menon" <nm@ti.com>, "Vignesh Raghavendra" <vigneshr@ti.com>, "Richard Weinberger" <richard@nod.at>, "Miquel Raynal" <miquel.raynal@bootlin.com>, "Lucas Stach" <dev@lynxeye.de>, "Stefan Agner" <stefan@agner.ch>, "Adrian Hunter" <adrian.hunter@intel.com>, "Mauro Carvalho Chehab" <mchehab@kernel.org>, "Rob Herring" <robh+dt@kernel.org>, "Michael Turquette" <mturquette@baylibre.com> Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-staging@lists.linux.dev, linux-spi@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mtd@lists.infradead.org, linux-mmc@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v8 08/34] dt-bindings: host1x: Document OPP and power domain properties Date: Tue, 17 Aug 2021 04:27:28 +0300 [thread overview] Message-ID: <20210817012754.8710-9-digetx@gmail.com> (raw) In-Reply-To: <20210817012754.8710-1-digetx@gmail.com> Document new DVFS OPP table and power domain properties of the Host1x bus and devices sitting on the bus. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../display/tegra/nvidia,tegra20-host1x.txt | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 8a6d3e1ee306..62861a8fb5c6 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -20,6 +20,18 @@ Required properties: - reset-names: Must include the following entries: - host1x +Optional properties: +- operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. + +For each opp entry in 'operating-points-v2' table of host1x and its modules: +- opp-supported-hw: One bitfield indicating: + On Tegra20: SoC process ID mask + On Tegra30+: SoC speedo ID mask + + A bitwise AND is performed against the value and if any bit + matches, the OPP gets enabled. + Each host1x client module having to perform DMA through the Memory Controller should have the interconnect endpoints set to the Memory Client and External Memory respectively. @@ -45,6 +57,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to MPE power domain. - vi: video input @@ -128,6 +142,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to VENC power domain. - epp: encoder pre-processor @@ -147,6 +163,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. - isp: image signal processor @@ -166,6 +184,7 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - power-domains: Phandle to VENC or core power domain. - gr2d: 2D graphics engine @@ -185,6 +204,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. - gr3d: 3D graphics engine @@ -209,6 +230,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandles to 3D or core power domain. - dc: display controller @@ -241,6 +264,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to core power domain. - hdmi: High Definition Multimedia Interface @@ -267,6 +292,7 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - operating-points-v2: See ../bindings/opp/opp.txt for details. - tvo: TV encoder output @@ -277,6 +303,10 @@ of the following host1x client modules: - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. + Optional properties: + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to core power domain. + - dsi: display serial interface Required properties: @@ -305,6 +335,7 @@ of the following host1x client modules: - nvidia,panel: phandle of a display panel - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang up with in order to support up to 8 data lanes + - operating-points-v2: See ../bindings/opp/opp.txt for details. - sor: serial output resource @@ -408,6 +439,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_HOST1X>; resets = <&tegra_car 28>; reset-names = "host1x"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; #address-cells = <1>; #size-cells = <1>; @@ -421,6 +454,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; vi@54080000 { @@ -429,6 +464,7 @@ Example: interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + operating-points-v2 = <&dvfs_opp_table>; clocks = <&tegra_car TEGRA210_CLK_VI>; power-domains = <&pd_venc>; @@ -510,6 +546,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; isp { @@ -528,6 +566,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; gr3d { @@ -536,6 +576,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; dc@54200000 { @@ -547,6 +589,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, <&mc TEGRA20_MC_DISPLAY0B &emc>, @@ -571,6 +615,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, <&mc TEGRA20_MC_DISPLAY0BB &emc>, @@ -596,6 +642,7 @@ Example: resets = <&tegra_car 51>; reset-names = "hdmi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; tvo { @@ -604,6 +651,7 @@ Example: interrupts = <0 76 0x04>; clocks = <&tegra_car TEGRA20_CLK_TVO>; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; dsi { @@ -615,6 +663,7 @@ Example: resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; }; -- 2.32.0 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2021-08-17 1:30 UTC|newest] Thread overview: 238+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-17 1:27 [PATCH v8 00/34] NVIDIA Tegra power management patches for 5.16 Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 01/34] opp: Add dev_pm_opp_sync() helper Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 7:55 ` Viresh Kumar 2021-08-17 7:55 ` Viresh Kumar 2021-08-17 15:49 ` Dmitry Osipenko 2021-08-17 15:49 ` Dmitry Osipenko 2021-08-18 3:55 ` Viresh Kumar 2021-08-18 3:55 ` Viresh Kumar 2021-08-18 4:12 ` Dmitry Osipenko 2021-08-18 4:12 ` Dmitry Osipenko 2021-08-18 4:29 ` Dmitry Osipenko 2021-08-18 4:29 ` Dmitry Osipenko 2021-08-18 4:30 ` Dmitry Osipenko 2021-08-18 4:30 ` Dmitry Osipenko 2021-08-18 4:34 ` Viresh Kumar 2021-08-18 4:34 ` Viresh Kumar 2021-08-18 4:31 ` Viresh Kumar 2021-08-18 4:31 ` Viresh Kumar 2021-08-18 4:37 ` Dmitry Osipenko 2021-08-18 4:37 ` Dmitry Osipenko 2021-08-18 4:53 ` Viresh Kumar 2021-08-18 4:53 ` Viresh Kumar 2021-08-18 5:21 ` Dmitry Osipenko 2021-08-18 5:21 ` Dmitry Osipenko 2021-08-18 5:58 ` Viresh Kumar 2021-08-18 5:58 ` Viresh Kumar 2021-08-18 6:00 ` Viresh Kumar 2021-08-18 6:00 ` Viresh Kumar 2021-08-18 6:22 ` Dmitry Osipenko 2021-08-18 6:22 ` Dmitry Osipenko 2021-08-18 6:27 ` Viresh Kumar 2021-08-18 6:27 ` Viresh Kumar 2021-08-18 8:29 ` Ulf Hansson 2021-08-18 8:29 ` Ulf Hansson 2021-08-18 9:14 ` Viresh Kumar 2021-08-18 9:14 ` Viresh Kumar 2021-08-18 9:41 ` Ulf Hansson 2021-08-18 9:41 ` Ulf Hansson 2021-08-18 9:42 ` Ulf Hansson 2021-08-18 9:42 ` Ulf Hansson 2021-08-18 9:50 ` Viresh Kumar 2021-08-18 9:50 ` Viresh Kumar 2021-08-18 10:08 ` Ulf Hansson 2021-08-18 10:08 ` Ulf Hansson 2021-08-18 15:43 ` Dmitry Osipenko 2021-08-18 15:43 ` Dmitry Osipenko 2021-08-18 15:46 ` Dmitry Osipenko 2021-08-18 15:46 ` Dmitry Osipenko 2021-08-19 13:07 ` Ulf Hansson 2021-08-19 13:07 ` Ulf Hansson 2021-08-19 19:35 ` Dmitry Osipenko 2021-08-19 19:35 ` Dmitry Osipenko 2021-08-20 5:07 ` Viresh Kumar 2021-08-20 5:07 ` Viresh Kumar 2021-08-20 12:42 ` Ulf Hansson 2021-08-20 12:42 ` Ulf Hansson 2021-08-21 17:34 ` Dmitry Osipenko 2021-08-21 17:34 ` Dmitry Osipenko 2021-08-23 10:46 ` Ulf Hansson 2021-08-23 10:46 ` Ulf Hansson 2021-08-23 15:54 ` Dmitry Osipenko 2021-08-23 15:54 ` Dmitry Osipenko 2021-08-18 15:55 ` Dmitry Osipenko 2021-08-18 15:55 ` Dmitry Osipenko 2021-08-19 6:16 ` Viresh Kumar 2021-08-19 6:16 ` Viresh Kumar 2021-08-19 14:55 ` Ulf Hansson 2021-08-19 14:55 ` Ulf Hansson 2021-08-20 5:18 ` Viresh Kumar 2021-08-20 5:18 ` Viresh Kumar 2021-08-20 12:57 ` Ulf Hansson 2021-08-20 12:57 ` Ulf Hansson 2021-08-23 20:24 ` Dmitry Osipenko 2021-08-23 20:24 ` Dmitry Osipenko 2021-08-24 3:04 ` Viresh Kumar 2021-08-24 3:04 ` Viresh Kumar 2021-08-22 18:35 ` Dmitry Osipenko 2021-08-22 18:35 ` Dmitry Osipenko 2021-08-25 15:41 ` Dmitry Osipenko 2021-08-25 15:41 ` Dmitry Osipenko 2021-08-26 2:54 ` Viresh Kumar 2021-08-26 2:54 ` Viresh Kumar 2021-08-26 2:55 ` Viresh Kumar 2021-08-26 2:55 ` Viresh Kumar 2021-08-17 1:27 ` [PATCH v8 02/34] soc/tegra: pmc: Disable PMC state syncing Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 03/34] soc/tegra: Don't print error message when OPPs not available Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 04/34] soc/tegra: Add devm_tegra_core_dev_init_opp_table_simple() Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 05/34] soc/tegra: Use dev_pm_opp_sync() Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 06/34] dt-bindings: clock: tegra-car: Document new tegra-clocks sub-node Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-18 1:15 ` Rob Herring 2021-08-18 1:15 ` Rob Herring 2021-08-18 1:44 ` Dmitry Osipenko 2021-08-18 1:44 ` Dmitry Osipenko 2021-08-18 13:52 ` Thierry Reding 2021-08-18 13:52 ` Thierry Reding 2021-08-18 15:04 ` Dmitry Osipenko 2021-08-18 15:04 ` Dmitry Osipenko 2021-08-18 13:59 ` Thierry Reding 2021-08-18 13:59 ` Thierry Reding 2021-08-18 15:05 ` Dmitry Osipenko 2021-08-18 15:05 ` Dmitry Osipenko 2021-08-18 16:39 ` Thierry Reding 2021-08-18 16:39 ` Thierry Reding 2021-08-18 16:57 ` Dmitry Osipenko 2021-08-18 16:57 ` Dmitry Osipenko 2021-08-18 17:16 ` Dmitry Osipenko 2021-08-18 17:16 ` Dmitry Osipenko 2021-08-19 16:31 ` Thierry Reding 2021-08-19 16:31 ` Thierry Reding 2021-08-19 22:20 ` Dmitry Osipenko 2021-08-19 22:20 ` Dmitry Osipenko 2021-08-20 2:51 ` Dmitry Osipenko 2021-08-20 2:51 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 07/34] clk: tegra: Support runtime PM and power domain Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-18 14:07 ` Thierry Reding 2021-08-18 14:07 ` Thierry Reding 2021-08-18 15:05 ` Dmitry Osipenko 2021-08-18 15:05 ` Dmitry Osipenko 2021-08-18 16:42 ` Thierry Reding 2021-08-18 16:42 ` Thierry Reding 2021-08-18 17:11 ` Dmitry Osipenko 2021-08-18 17:11 ` Dmitry Osipenko 2021-08-19 16:54 ` Thierry Reding 2021-08-19 16:54 ` Thierry Reding 2021-08-19 22:09 ` Dmitry Osipenko 2021-08-19 22:09 ` Dmitry Osipenko 2021-08-20 11:42 ` Thierry Reding 2021-08-20 11:42 ` Thierry Reding 2021-08-20 13:08 ` Ulf Hansson 2021-08-20 13:08 ` Ulf Hansson 2021-08-21 17:45 ` Dmitry Osipenko 2021-08-21 17:45 ` Dmitry Osipenko 2021-08-23 14:33 ` Thierry Reding 2021-08-23 14:33 ` Thierry Reding 2021-08-23 18:54 ` Dmitry Osipenko 2021-08-23 18:54 ` Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko [this message] 2021-08-17 1:27 ` [PATCH v8 08/34] dt-bindings: host1x: Document OPP and power domain properties Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 09/34] dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-18 1:16 ` Rob Herring 2021-08-18 1:16 ` Rob Herring 2021-08-18 1:37 ` Dmitry Osipenko 2021-08-18 1:37 ` Dmitry Osipenko 2021-08-18 2:04 ` Dmitry Osipenko 2021-08-18 2:04 ` Dmitry Osipenko 2021-08-18 2:07 ` Dmitry Osipenko 2021-08-18 2:07 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 10/34] gpu: host1x: Add host1x_channel_stop() Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 11/34] gpu: host1x: Add runtime PM and OPP support Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 12:04 ` Ulf Hansson 2021-08-17 12:04 ` Ulf Hansson 2021-08-17 14:02 ` Thierry Reding 2021-08-17 14:02 ` Thierry Reding 2021-08-18 8:35 ` Ulf Hansson 2021-08-18 8:35 ` Ulf Hansson 2021-08-18 17:24 ` Dmitry Osipenko 2021-08-18 17:24 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 12/34] drm/tegra: dc: Support OPP and SoC core voltage scaling Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 13/34] drm/tegra: hdmi: Add OPP support Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 14/34] drm/tegra: gr2d: Support power management Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 15/34] drm/tegra: gr3d: " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 16/34] drm/tegra: vic: Support system suspend Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 17/34] usb: chipidea: tegra: Add runtime PM and OPP support Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 18/34] bus: tegra-gmi: " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 19/34] pwm: tegra: " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-19 13:21 ` Thierry Reding 2021-08-19 13:21 ` Thierry Reding 2021-08-19 14:04 ` Ulf Hansson 2021-08-19 14:04 ` Ulf Hansson 2021-08-19 16:17 ` Thierry Reding 2021-08-19 16:17 ` Thierry Reding 2021-08-17 1:27 ` [PATCH v8 20/34] mmc: sdhci-tegra: " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-19 17:03 ` Thierry Reding 2021-08-19 17:03 ` Thierry Reding 2021-08-19 22:37 ` Dmitry Osipenko 2021-08-19 22:37 ` Dmitry Osipenko 2021-08-20 11:35 ` Thierry Reding 2021-08-20 11:35 ` Thierry Reding 2021-08-25 9:45 ` Dmitry Osipenko 2021-08-25 9:45 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 21/34] mtd: rawnand: tegra: " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 8:41 ` Miquel Raynal 2021-08-17 8:41 ` Miquel Raynal 2021-08-17 1:27 ` [PATCH v8 22/34] spi: tegra20-slink: Add " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 12:22 ` Mark Brown 2021-08-17 12:22 ` Mark Brown 2021-08-17 15:53 ` Dmitry Osipenko 2021-08-17 15:53 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 23/34] media: dt: bindings: tegra-vde: Convert to schema Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-18 1:17 ` Rob Herring 2021-08-18 1:17 ` Rob Herring 2021-08-17 1:27 ` [PATCH v8 24/34] media: dt: bindings: tegra-vde: Document OPP and power domain Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-18 1:17 ` Rob Herring 2021-08-18 1:17 ` Rob Herring 2021-08-17 1:27 ` [PATCH v8 25/34] media: staging: tegra-vde: Support generic power domain and OPP Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 26/34] soc/tegra: fuse: Add OPP support Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 27/34] soc/tegra: fuse: Reset hardware Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 28/34] soc/tegra: regulators: Prepare for suspend Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 29/34] soc/tegra: pmc: Enable core domain support for Tegra20 and Tegra30 Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 30/34] ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 31/34] ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 32/34] ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 33/34] ARM: tegra: Add Memory Client resets to Tegra30 " Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko 2021-08-17 1:27 ` [PATCH v8 34/34] ARM: tegra20/30: Disable unused host1x hardware Dmitry Osipenko 2021-08-17 1:27 ` Dmitry Osipenko
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