From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <joel@jms.id.au>, <robh+dt@kernel.org>, <andrew@aj.id.au>,
<linux-aspeed@lists.ozlabs.org>, <openbmc@lists.ozlabs.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: <ryan_chen@aspeedtech.com>
Subject: [PATCH v2 3/5] clk: aspeed: Add eSPI reset bit
Date: Thu, 19 Aug 2021 16:00:38 +0800 [thread overview]
Message-ID: <20210819080040.31242-4-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20210819080040.31242-1-chiawei_wang@aspeedtech.com>
Add bit field definition for the eSPI reset control
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
include/dt-bindings/clock/ast2600-clock.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
index 62b9520a00fd..964934b1caef 100644
--- a/include/dt-bindings/clock/ast2600-clock.h
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -89,6 +89,7 @@
#define ASPEED_CLK_MAC4RCLK 70
/* Only list resets here that are not part of a gate */
+#define ASPEED_RESET_ESPI 57
#define ASPEED_RESET_ADC 55
#define ASPEED_RESET_JTAG_MASTER2 54
#define ASPEED_RESET_I3C_DMA 39
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <joel@jms.id.au>, <robh+dt@kernel.org>, <andrew@aj.id.au>,
<linux-aspeed@lists.ozlabs.org>, <openbmc@lists.ozlabs.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: ryan_chen@aspeedtech.com
Subject: [PATCH v2 3/5] clk: aspeed: Add eSPI reset bit
Date: Thu, 19 Aug 2021 16:00:38 +0800 [thread overview]
Message-ID: <20210819080040.31242-4-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20210819080040.31242-1-chiawei_wang@aspeedtech.com>
Add bit field definition for the eSPI reset control
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
include/dt-bindings/clock/ast2600-clock.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
index 62b9520a00fd..964934b1caef 100644
--- a/include/dt-bindings/clock/ast2600-clock.h
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -89,6 +89,7 @@
#define ASPEED_CLK_MAC4RCLK 70
/* Only list resets here that are not part of a gate */
+#define ASPEED_RESET_ESPI 57
#define ASPEED_RESET_ADC 55
#define ASPEED_RESET_JTAG_MASTER2 54
#define ASPEED_RESET_I3C_DMA 39
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <joel@jms.id.au>, <robh+dt@kernel.org>, <andrew@aj.id.au>,
<linux-aspeed@lists.ozlabs.org>, <openbmc@lists.ozlabs.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: <ryan_chen@aspeedtech.com>
Subject: [PATCH v2 3/5] clk: aspeed: Add eSPI reset bit
Date: Thu, 19 Aug 2021 16:00:38 +0800 [thread overview]
Message-ID: <20210819080040.31242-4-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20210819080040.31242-1-chiawei_wang@aspeedtech.com>
Add bit field definition for the eSPI reset control
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
include/dt-bindings/clock/ast2600-clock.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
index 62b9520a00fd..964934b1caef 100644
--- a/include/dt-bindings/clock/ast2600-clock.h
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -89,6 +89,7 @@
#define ASPEED_CLK_MAC4RCLK 70
/* Only list resets here that are not part of a gate */
+#define ASPEED_RESET_ESPI 57
#define ASPEED_RESET_ADC 55
#define ASPEED_RESET_JTAG_MASTER2 54
#define ASPEED_RESET_I3C_DMA 39
--
2.17.1
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next prev parent reply other threads:[~2021-08-19 8:01 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-19 8:00 [PATCH v2 0/5] arm: aspeed: Add eSPI support Chia-Wei Wang
2021-08-19 8:00 ` Chia-Wei Wang
2021-08-19 8:00 ` Chia-Wei Wang
2021-08-19 8:00 ` [PATCH v2 1/5] dt-bindings: aspeed: Add eSPI controller Chia-Wei Wang
2021-08-19 8:00 ` Chia-Wei Wang
2021-08-19 8:00 ` Chia-Wei Wang
2021-08-19 12:49 ` Rob Herring
2021-08-19 12:49 ` Rob Herring
2021-08-19 12:49 ` Rob Herring
2021-08-20 20:01 ` Rob Herring
2021-08-20 20:01 ` Rob Herring
2021-08-20 20:01 ` Rob Herring
2021-08-23 1:21 ` ChiaWei Wang
2021-08-23 1:21 ` ChiaWei Wang
2021-08-23 1:21 ` ChiaWei Wang
2021-08-19 8:00 ` [PATCH v2 2/5] MAINTAINER: Add ASPEED eSPI driver entry Chia-Wei Wang
2021-08-19 8:00 ` Chia-Wei Wang
2021-08-19 8:00 ` Chia-Wei Wang
2021-08-19 8:00 ` Chia-Wei Wang [this message]
2021-08-19 8:00 ` [PATCH v2 3/5] clk: aspeed: Add eSPI reset bit Chia-Wei Wang
2021-08-19 8:00 ` Chia-Wei Wang
2021-08-19 8:00 ` [PATCH v2 4/5] soc: aspeed: Add eSPI driver Chia-Wei Wang
2021-08-19 8:00 ` Chia-Wei Wang
2021-08-19 8:00 ` Chia-Wei Wang
2021-08-19 17:27 ` kernel test robot
2021-08-19 17:27 ` kernel test robot
2021-08-19 17:27 ` kernel test robot
2021-08-19 17:27 ` kernel test robot
2021-08-19 8:00 ` [PATCH v2 5/5] ARM: dts: aspeed: Add eSPI node Chia-Wei Wang
2021-08-19 8:00 ` Chia-Wei Wang
2021-08-19 8:00 ` Chia-Wei Wang
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