Re: [Intel-gfx] [PATCH V4 6/6] drm/i915/selftest: Remove Renderer class check for l3cc table read

From: Matt Roper <matthew.d.roper@intel.com>
To: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH V4 6/6] drm/i915/selftest: Remove Renderer class check for l3cc table read
Date: Thu, 2 Sep 2021 14:07:45 -0700	[thread overview]
Message-ID: <20210902210745.GR461228@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20210902185635.290538-7-ayaz.siddiqui@intel.com>

On Fri, Sep 03, 2021 at 12:26:35AM +0530, Ayaz A Siddiqui wrote:
> Some platform like XEHPSVD does not have Renderer engines. since
> read_l3cc_table() is guarded by renderer class due to that check
> of L3CC table was not being performed on those platforms.
> 

Yeah, Xe_HP SDV doesn't have an RCS engine, but it does have compute
engines (CCS) that fill the same role.  I have the initial patches to
enable the compute engine ready to send upstream; just waiting on one of
the userspace drivers (either Mesa or OCL) to have their own merge
requests ready so that I can reference that as our userspace consumer.

Maybe we should hold off on this patch for now and change this to

        if (!err && engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)

which will apply to both the render and compute engines at that point?
Or, since these registers are global and not engine-specific, we could
adjust the code to just do this once, with whatever the GT's first
engine happens to be (doesn't matter if it's RCS, CCS, BCS, VCS, or
VECS) so that we're not repeating the same process multiple times
needlessly?

Matt

> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/selftest_mocs.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> index 13d25bf2a94aa..c3a48a06c37ee 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -237,7 +237,7 @@ static int check_mocs_engine(struct live_mocs *arg,
>  	offset = i915_ggtt_offset(vma);
>  	if (!err)
>  		err = read_mocs_table(rq, arg->mocs, &offset);
> -	if (!err && ce->engine->class == RENDER_CLASS)
> +	if (!err)
>  		err = read_l3cc_table(rq, arg->l3cc, &offset);
>  	offset -= i915_ggtt_offset(vma);
>  	GEM_BUG_ON(offset > PAGE_SIZE);
> @@ -250,7 +250,7 @@ static int check_mocs_engine(struct live_mocs *arg,
>  	vaddr = arg->vaddr;
>  	if (!err)
>  		err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
> -	if (!err && ce->engine->class == RENDER_CLASS)
> +	if (!err)
>  		err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
>  	if (err)
>  		return err;
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795