* [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu
@ 2021-09-04 23:55 Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition Philippe Mathieu-Daudé
` (23 more replies)
0 siblings, 24 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Missing review:
- 01 target/avr: Remove pointless use of CONFIG_USER_ONLY definition
- 11 target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder
Hi,
The TCGCPUOps::cpu_exec_interrupt() handler is specific to system
emulation. This series remove it from user-mode.
To do so we have to deal with a x86-hack first, then we restrict
each target handler (one target at a time) and finally we restrict
the prototype, simplifying cpu_handle_interrupt().
As a bonus we can remove the cpu_get_pic_interrupt() stubs from
bsd/linux-user.
Since v1:
- Addressed Richard comments (drop AVR patch, remove assert)
- Added R-b
Philippe Mathieu-Daudé (24):
target/avr: Remove pointless use of CONFIG_USER_ONLY definition
target/i386: Restrict sysemu-only fpu_helper helpers
target/i386: Simplify TARGET_X86_64 #ifdef'ry
target/xtensa: Restrict do_transaction_failed() to sysemu
accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt
target/alpha: Restrict cpu_exec_interrupt() handler to sysemu
target/arm: Restrict cpu_exec_interrupt() handler to sysemu
target/cris: Restrict cpu_exec_interrupt() handler to sysemu
target/hppa: Restrict cpu_exec_interrupt() handler to sysemu
target/i386: Restrict cpu_exec_interrupt() handler to sysemu
target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder
target/m68k: Restrict cpu_exec_interrupt() handler to sysemu
target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu
target/mips: Restrict cpu_exec_interrupt() handler to sysemu
target/nios2: Restrict cpu_exec_interrupt() handler to sysemu
target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu
target/ppc: Restrict cpu_exec_interrupt() handler to sysemu
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
target/sh4: Restrict cpu_exec_interrupt() handler to sysemu
target/sparc: Restrict cpu_exec_interrupt() handler to sysemu
target/rx: Restrict cpu_exec_interrupt() handler to sysemu
target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu
accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu
user: Remove cpu_get_pic_interrupt() stubs
include/hw/core/tcg-cpu-ops.h | 26 ++++++----
target/alpha/cpu.h | 2 +-
target/arm/cpu.h | 3 +-
target/cris/cpu.h | 2 +-
target/hppa/cpu.h | 4 +-
target/i386/cpu.h | 3 ++
target/i386/tcg/helper-tcg.h | 2 +
target/m68k/cpu.h | 2 +
target/microblaze/cpu.h | 2 +
target/mips/tcg/tcg-internal.h | 5 +-
target/openrisc/cpu.h | 5 +-
target/ppc/cpu.h | 4 +-
target/riscv/cpu.h | 2 +-
target/rx/cpu.h | 2 +
target/sh4/cpu.h | 4 +-
target/xtensa/cpu.h | 2 +
accel/tcg/cpu-exec.c | 14 ++++--
bsd-user/main.c | 7 ---
linux-user/main.c | 7 ---
target/alpha/cpu.c | 2 +-
target/alpha/helper.c | 5 +-
target/arm/cpu.c | 7 ++-
target/arm/cpu_tcg.c | 6 +--
target/avr/cpu.c | 3 --
target/cris/cpu.c | 4 +-
target/cris/helper.c | 17 +------
target/hppa/cpu.c | 2 +-
target/hppa/int_helper.c | 7 +--
target/i386/tcg/seg_helper.c | 74 +----------------------------
target/i386/tcg/sysemu/seg_helper.c | 65 +++++++++++++++++++++++++
target/i386/tcg/tcg-cpu.c | 8 ++--
target/m68k/cpu.c | 2 +-
target/m68k/op_helper.c | 16 ++-----
target/microblaze/cpu.c | 2 +-
target/microblaze/helper.c | 13 +----
target/mips/cpu.c | 2 +-
target/mips/tcg/exception.c | 18 -------
target/mips/tcg/sysemu/tlb_helper.c | 18 +++++++
target/mips/tcg/user/tlb_helper.c | 5 --
target/nios2/cpu.c | 5 +-
target/openrisc/cpu.c | 2 +-
target/openrisc/interrupt.c | 2 -
target/ppc/cpu_init.c | 2 +-
target/ppc/excp_helper.c | 21 ++------
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 5 --
target/rx/cpu.c | 2 +-
target/rx/helper.c | 4 ++
target/sh4/cpu.c | 2 +-
target/sh4/helper.c | 9 +---
target/sparc/cpu.c | 4 +-
target/xtensa/cpu.c | 2 +-
target/xtensa/exc_helper.c | 7 +--
target/openrisc/meson.build | 6 ++-
54 files changed, 196 insertions(+), 253 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v2 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-05 8:29 ` Richard Henderson
2021-09-05 14:24 ` Warner Losh
2021-09-04 23:55 ` [PATCH v2 02/24] target/i386: Restrict sysemu-only fpu_helper helpers Philippe Mathieu-Daudé
` (22 subsequent siblings)
23 siblings, 2 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Commit f1c671f96cb ("target/avr: Introduce basic CPU class object")
added to target/avr/cpu.h:
#ifdef CONFIG_USER_ONLY
#error "AVR 8-bit does not support user mode"
#endif
Remove the CONFIG_USER_ONLY definition introduced by mistake in
commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a
pointer in CPUClass").
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/avr/cpu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index ea14175ca55..5d70e34dd54 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -197,10 +197,7 @@ static const struct TCGCPUOps avr_tcg_ops = {
.synchronize_from_tb = avr_cpu_synchronize_from_tb,
.cpu_exec_interrupt = avr_cpu_exec_interrupt,
.tlb_fill = avr_cpu_tlb_fill,
-
-#ifndef CONFIG_USER_ONLY
.do_interrupt = avr_cpu_do_interrupt,
-#endif /* !CONFIG_USER_ONLY */
};
static void avr_cpu_class_init(ObjectClass *oc, void *data)
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 02/24] target/i386: Restrict sysemu-only fpu_helper helpers
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 03/24] target/i386: Simplify TARGET_X86_64 #ifdef'ry Philippe Mathieu-Daudé
` (21 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict some sysemu-only fpu_helper helpers (see commit
83a3d9c7402: "i386: separate fpu_helper sysemu-only parts").
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/i386/cpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 6c50d3ab4f1..c241bc183d2 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1833,11 +1833,14 @@ void x86_cpu_list(void);
int cpu_x86_support_mca_broadcast(CPUX86State *env);
int cpu_get_pic_interrupt(CPUX86State *s);
+
+#ifndef CONFIG_USER_ONLY
/* MSDOS compatibility mode FPU exception support */
void x86_register_ferr_irq(qemu_irq irq);
void fpu_check_raise_ferr_irq(CPUX86State *s);
void cpu_set_ignne(void);
void cpu_clear_ignne(void);
+#endif
/* mpx_helper.c */
void cpu_sync_bndcs_hflags(CPUX86State *env);
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 03/24] target/i386: Simplify TARGET_X86_64 #ifdef'ry
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 02/24] target/i386: Restrict sysemu-only fpu_helper helpers Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 04/24] target/xtensa: Restrict do_transaction_failed() to sysemu Philippe Mathieu-Daudé
` (20 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Merge two TARGET_X86_64 consecutive blocks.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/i386/tcg/seg_helper.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index 3ed20ca31d7..dee7bef68c6 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -929,9 +929,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,
e2);
env->eip = offset;
}
-#endif
-#ifdef TARGET_X86_64
void helper_sysret(CPUX86State *env, int dflag)
{
int cpl, selector;
@@ -984,7 +982,7 @@ void helper_sysret(CPUX86State *env, int dflag)
DESC_W_MASK | DESC_A_MASK);
}
}
-#endif
+#endif /* TARGET_X86_64 */
/* real mode interrupt */
static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 04/24] target/xtensa: Restrict do_transaction_failed() to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 03/24] target/i386: Simplify TARGET_X86_64 #ifdef'ry Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 05/24] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt Philippe Mathieu-Daudé
` (19 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
The do_transaction_failed() is restricted to system emulation since
commit cbc183d2d9f ("cpu: move cc->transaction_failed to tcg_ops").
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/xtensa/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 2345cb59c79..1e0cb1535ca 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -568,10 +568,12 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
bool probe, uintptr_t retaddr);
void xtensa_cpu_do_interrupt(CPUState *cpu);
bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
+#ifndef CONFIG_USER_ONLY
void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
+#endif /* !CONFIG_USER_ONLY */
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void xtensa_count_regs(const XtensaConfig *config,
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 05/24] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 04/24] target/xtensa: Restrict do_transaction_failed() to sysemu Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 06/24] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu Philippe Mathieu-Daudé
` (18 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
do_interrupt() is sysemu specific. However due to some X86
specific hack, it is also used in user-mode emulation, which
is why it couldn't be restricted to CONFIG_SOFTMMU (see the
comment around added in commit 78271684719: "cpu: tcg_ops:
move to tcg-cpu-ops.h, keep a pointer in CPUClass").
Keep the hack but rename the handler as fake_user_interrupt()
and restrict do_interrupt() to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/tcg-cpu-ops.h | 22 ++++++++++++++--------
accel/tcg/cpu-exec.c | 4 ++--
target/i386/tcg/tcg-cpu.c | 6 ++++--
3 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index eab27d0c030..6c7ab9600ba 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -37,14 +37,6 @@ struct TCGCPUOps {
void (*cpu_exec_exit)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
- /**
- * @do_interrupt: Callback for interrupt handling.
- *
- * note that this is in general SOFTMMU only, but it actually isn't
- * because of an x86 hack (accel/tcg/cpu-exec.c), so we cannot put it
- * in the SOFTMMU section in general.
- */
- void (*do_interrupt)(CPUState *cpu);
/**
* @tlb_fill: Handle a softmmu tlb miss or user-only address fault
*
@@ -61,6 +53,20 @@ struct TCGCPUOps {
void (*debug_excp_handler)(CPUState *cpu);
#ifdef NEED_CPU_H
+#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386)
+ /**
+ * @fake_user_interrupt: Callback for 'fake exception' handling.
+ *
+ * Simulate 'fake exception' which will be handled outside the
+ * cpu execution loop (hack for x86 user mode).
+ */
+ void (*fake_user_interrupt)(CPUState *cpu);
+#else
+ /**
+ * @do_interrupt: Callback for interrupt handling.
+ */
+ void (*do_interrupt)(CPUState *cpu);
+#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
#ifdef CONFIG_SOFTMMU
/**
* @do_transaction_failed: Callback for handling failed memory transactions
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index e5c0ccd1a2a..2838177e7f0 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -651,8 +651,8 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
loop */
#if defined(TARGET_I386)
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops->do_interrupt(cpu);
-#endif
+ cc->tcg_ops->fake_user_interrupt(cpu);
+#endif /* TARGET_I386 */
*ret = cpu->exception_index;
cpu->exception_index = -1;
return true;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 93a79a57415..04c35486a2f 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -73,9 +73,11 @@ static const struct TCGCPUOps x86_tcg_ops = {
.cpu_exec_enter = x86_cpu_exec_enter,
.cpu_exec_exit = x86_cpu_exec_exit,
.cpu_exec_interrupt = x86_cpu_exec_interrupt,
- .do_interrupt = x86_cpu_do_interrupt,
.tlb_fill = x86_cpu_tlb_fill,
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ .fake_user_interrupt = x86_cpu_do_interrupt,
+#else
+ .do_interrupt = x86_cpu_do_interrupt,
.debug_excp_handler = breakpoint_handler,
.debug_check_breakpoint = x86_debug_check_breakpoint,
#endif /* !CONFIG_USER_ONLY */
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 06/24] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 05/24] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 07/24] target/arm: " Philippe Mathieu-Daudé
` (17 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/alpha/cpu.h | 2 +-
target/alpha/cpu.c | 2 +-
target/alpha/helper.c | 5 ++---
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 82df108967b..4e993bd15bd 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -274,10 +274,10 @@ struct AlphaCPU {
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_alpha_cpu;
-#endif
void alpha_cpu_do_interrupt(CPUState *cpu);
bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);
+#endif /* !CONFIG_USER_ONLY */
void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);
hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 4871ad0c0a6..93e16a2ffb4 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -218,10 +218,10 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
static const struct TCGCPUOps alpha_tcg_ops = {
.initialize = alpha_translate_init,
- .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
.tlb_fill = alpha_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
.do_interrupt = alpha_cpu_do_interrupt,
.do_transaction_failed = alpha_cpu_do_transaction_failed,
.do_unaligned_access = alpha_cpu_do_unaligned_access,
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 4f56fe4d231..81550d9e2ff 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -293,7 +293,6 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
prot, mmu_idx, TARGET_PAGE_SIZE);
return true;
}
-#endif /* USER_ONLY */
void alpha_cpu_do_interrupt(CPUState *cs)
{
@@ -348,7 +347,6 @@ void alpha_cpu_do_interrupt(CPUState *cs)
cs->exception_index = -1;
-#if !defined(CONFIG_USER_ONLY)
switch (i) {
case EXCP_RESET:
i = 0x0000;
@@ -404,7 +402,6 @@ void alpha_cpu_do_interrupt(CPUState *cs)
/* Switch to PALmode. */
env->flags |= ENV_FLAG_PAL_MODE;
-#endif /* !USER_ONLY */
}
bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
@@ -451,6 +448,8 @@ bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return false;
}
+#endif /* !CONFIG_USER_ONLY */
+
void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
static const char linux_reg_names[31][4] = {
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 07/24] target/arm: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 06/24] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 08/24] target/cris: " Philippe Mathieu-Daudé
` (16 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/cpu.h | 3 +--
target/arm/cpu.c | 7 +++++--
target/arm/cpu_tcg.c | 6 +++---
3 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 6a987f65e41..cfd755cff99 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1040,11 +1040,10 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_arm_cpu;
-#endif
void arm_cpu_do_interrupt(CPUState *cpu);
void arm_v7m_cpu_do_interrupt(CPUState *cpu);
-bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
+#endif /* !CONFIG_USER_ONLY */
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d631c4683c4..ba0741b20e4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -440,6 +440,8 @@ static void arm_cpu_reset(DeviceState *dev)
arm_rebuild_hflags(env);
}
+#ifndef CONFIG_USER_ONLY
+
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
unsigned int target_el,
unsigned int cur_el, bool secure,
@@ -556,7 +558,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
return unmasked || pstate_unmasked;
}
-bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
CPUARMState *env = cs->env_ptr;
@@ -608,6 +610,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
cc->tcg_ops->do_interrupt(cs);
return true;
}
+#endif /* !CONFIG_USER_ONLY */
void arm_cpu_update_virq(ARMCPU *cpu)
{
@@ -2010,11 +2013,11 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
static const struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
- .cpu_exec_interrupt = arm_cpu_exec_interrupt,
.tlb_fill = arm_cpu_tlb_fill,
.debug_excp_handler = arm_debug_excp_handler,
#if !defined(CONFIG_USER_ONLY)
+ .cpu_exec_interrupt = arm_cpu_exec_interrupt,
.do_interrupt = arm_cpu_do_interrupt,
.do_transaction_failed = arm_cpu_do_transaction_failed,
.do_unaligned_access = arm_cpu_do_unaligned_access,
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 33cc75af57d..0d5adccf1a7 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -22,7 +22,7 @@
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-#ifdef CONFIG_TCG
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -46,7 +46,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return ret;
}
-#endif /* CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
static void arm926_initfn(Object *obj)
{
@@ -898,11 +898,11 @@ static void pxa270c5_initfn(Object *obj)
static const struct TCGCPUOps arm_v7m_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
- .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
.tlb_fill = arm_cpu_tlb_fill,
.debug_excp_handler = arm_debug_excp_handler,
#if !defined(CONFIG_USER_ONLY)
+ .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
.do_interrupt = arm_v7m_cpu_do_interrupt,
.do_transaction_failed = arm_cpu_do_transaction_failed,
.do_unaligned_access = arm_cpu_do_unaligned_access,
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 08/24] target/cris: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 07/24] target/arm: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 09/24] target/hppa: " Philippe Mathieu-Daudé
` (15 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/cris/cpu.h | 2 +-
target/cris/cpu.c | 4 ++--
target/cris/helper.c | 17 ++---------------
3 files changed, 5 insertions(+), 18 deletions(-)
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index d3b64929096..be021899ae8 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -185,11 +185,11 @@ struct CRISCPU {
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_cris_cpu;
-#endif
void cris_cpu_do_interrupt(CPUState *cpu);
void crisv10_cpu_do_interrupt(CPUState *cpu);
bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
+#endif
void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags);
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 70932b1f8c7..c2e7483f5bd 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -205,20 +205,20 @@ static const struct SysemuCPUOps cris_sysemu_ops = {
static const struct TCGCPUOps crisv10_tcg_ops = {
.initialize = cris_initialize_crisv10_tcg,
- .cpu_exec_interrupt = cris_cpu_exec_interrupt,
.tlb_fill = cris_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = cris_cpu_exec_interrupt,
.do_interrupt = crisv10_cpu_do_interrupt,
#endif /* !CONFIG_USER_ONLY */
};
static const struct TCGCPUOps crisv32_tcg_ops = {
.initialize = cris_initialize_tcg,
- .cpu_exec_interrupt = cris_cpu_exec_interrupt,
.tlb_fill = cris_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = cris_cpu_exec_interrupt,
.do_interrupt = cris_cpu_do_interrupt,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/cris/helper.c b/target/cris/helper.c
index 911867f3b48..36926faf323 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -41,20 +41,6 @@
#if defined(CONFIG_USER_ONLY)
-void cris_cpu_do_interrupt(CPUState *cs)
-{
- CRISCPU *cpu = CRIS_CPU(cs);
- CPUCRISState *env = &cpu->env;
-
- cs->exception_index = -1;
- env->pregs[PR_ERP] = env->pc;
-}
-
-void crisv10_cpu_do_interrupt(CPUState *cs)
-{
- cris_cpu_do_interrupt(cs);
-}
-
bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
@@ -287,7 +273,6 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
return phy;
}
-#endif
bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
@@ -319,3 +304,5 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return ret;
}
+
+#endif /* !CONFIG_USER_ONLY */
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 09/24] target/hppa: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 08/24] target/cris: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 10/24] target/i386: " Philippe Mathieu-Daudé
` (14 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/hppa/cpu.h | 4 ++--
target/hppa/cpu.c | 2 +-
target/hppa/int_helper.c | 7 ++-----
3 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 748270bfa31..7854675b903 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -325,13 +325,13 @@ int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc);
hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void hppa_cpu_do_interrupt(CPUState *cpu);
-bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
#ifndef CONFIG_USER_ONLY
+void hppa_cpu_do_interrupt(CPUState *cpu);
+bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
int type, hwaddr *pphys, int *pprot);
extern const MemoryRegionOps hppa_io_eir_ops;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 2eace4ee124..e8edd189bfc 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -144,10 +144,10 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
static const struct TCGCPUOps hppa_tcg_ops = {
.initialize = hppa_translate_init,
.synchronize_from_tb = hppa_cpu_synchronize_from_tb,
- .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
.tlb_fill = hppa_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
.do_interrupt = hppa_cpu_do_interrupt,
.do_unaligned_access = hppa_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c
index 349495d3610..13073ae2bda 100644
--- a/target/hppa/int_helper.c
+++ b/target/hppa/int_helper.c
@@ -88,7 +88,6 @@ void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val)
eval_interrupt(env_archcpu(env));
qemu_mutex_unlock_iothread();
}
-#endif /* !CONFIG_USER_ONLY */
void hppa_cpu_do_interrupt(CPUState *cs)
{
@@ -100,7 +99,6 @@ void hppa_cpu_do_interrupt(CPUState *cs)
uint64_t iasq_f = env->iasq_f;
uint64_t iasq_b = env->iasq_b;
-#ifndef CONFIG_USER_ONLY
target_ureg old_psw;
/* As documented in pa2.0 -- interruption handling. */
@@ -187,7 +185,6 @@ void hppa_cpu_do_interrupt(CPUState *cs)
env->iaoq_b = env->iaoq_f + 4;
env->iasq_f = 0;
env->iasq_b = 0;
-#endif
if (qemu_loglevel_mask(CPU_LOG_INT)) {
static const char * const names[] = {
@@ -248,7 +245,6 @@ void hppa_cpu_do_interrupt(CPUState *cs)
bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
-#ifndef CONFIG_USER_ONLY
HPPACPU *cpu = HPPA_CPU(cs);
CPUHPPAState *env = &cpu->env;
@@ -258,6 +254,7 @@ bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
hppa_cpu_do_interrupt(cs);
return true;
}
-#endif
return false;
}
+
+#endif /* !CONFIG_USER_ONLY */
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 10/24] target/i386: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 09/24] target/hppa: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder Philippe Mathieu-Daudé
` (13 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/i386/tcg/helper-tcg.h | 2 ++
target/i386/tcg/seg_helper.c | 10 ++--------
target/i386/tcg/tcg-cpu.c | 2 +-
3 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
index 2510cc244e9..60ca09e95eb 100644
--- a/target/i386/tcg/helper-tcg.h
+++ b/target/i386/tcg/helper-tcg.h
@@ -38,7 +38,9 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS);
* @cpu: vCPU the interrupt is to be handled by.
*/
void x86_cpu_do_interrupt(CPUState *cpu);
+#ifndef CONFIG_USER_ONLY
bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
+#endif
/* helper.c */
bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index dee7bef68c6..13c6e6ee62e 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -1110,6 +1110,7 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw);
}
+#ifndef CONFIG_USER_ONLY
bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
X86CPU *cpu = X86_CPU(cs);
@@ -1125,23 +1126,17 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
* This is required to make icount-driven execution deterministic.
*/
switch (interrupt_request) {
-#if !defined(CONFIG_USER_ONLY)
case CPU_INTERRUPT_POLL:
cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
apic_poll_irq(cpu->apic_state);
break;
-#endif
case CPU_INTERRUPT_SIPI:
do_cpu_sipi(cpu);
break;
case CPU_INTERRUPT_SMI:
cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0);
cs->interrupt_request &= ~CPU_INTERRUPT_SMI;
-#ifdef CONFIG_USER_ONLY
- cpu_abort(CPU(cpu), "SMI interrupt: cannot enter SMM in user-mode");
-#else
do_smm_enter(cpu);
-#endif /* CONFIG_USER_ONLY */
break;
case CPU_INTERRUPT_NMI:
cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0);
@@ -1162,7 +1157,6 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
"Servicing hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
break;
-#if !defined(CONFIG_USER_ONLY)
case CPU_INTERRUPT_VIRQ:
/* FIXME: this should respect TPR */
cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0);
@@ -1173,12 +1167,12 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
do_interrupt_x86_hardirq(env, intno, 1);
cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
break;
-#endif
}
/* Ensure that no TB jump will be modified as the program flow was changed. */
return true;
}
+#endif /* CONFIG_USER_ONLY */
void helper_lldt(CPUX86State *env, int selector)
{
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 04c35486a2f..3ecfae34cb5 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -72,12 +72,12 @@ static const struct TCGCPUOps x86_tcg_ops = {
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
.cpu_exec_enter = x86_cpu_exec_enter,
.cpu_exec_exit = x86_cpu_exec_exit,
- .cpu_exec_interrupt = x86_cpu_exec_interrupt,
.tlb_fill = x86_cpu_tlb_fill,
#ifdef CONFIG_USER_ONLY
.fake_user_interrupt = x86_cpu_do_interrupt,
#else
.do_interrupt = x86_cpu_do_interrupt,
+ .cpu_exec_interrupt = x86_cpu_exec_interrupt,
.debug_excp_handler = breakpoint_handler,
.debug_check_breakpoint = x86_debug_check_breakpoint,
#endif /* !CONFIG_USER_ONLY */
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 10/24] target/i386: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-05 8:35 ` Richard Henderson
2021-09-05 14:26 ` Warner Losh
2021-09-04 23:55 ` [PATCH v2 12/24] target/m68k: Restrict cpu_exec_interrupt() handler to sysemu Philippe Mathieu-Daudé
` (12 subsequent siblings)
23 siblings, 2 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Following the logic of commit 30493a030ff ("i386: split seg_helper
into user-only and sysemu parts"), move x86_cpu_exec_interrupt()
under sysemu/seg_helper.c.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
I prefer to not squash this into the previous patch because the
ifdef'ry removal (in previous patch) is not trivial IMO.
---
target/i386/tcg/seg_helper.c | 64 ----------------------------
target/i386/tcg/sysemu/seg_helper.c | 65 +++++++++++++++++++++++++++++
2 files changed, 65 insertions(+), 64 deletions(-)
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index 13c6e6ee62e..baa905a0cd6 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -1110,70 +1110,6 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw);
}
-#ifndef CONFIG_USER_ONLY
-bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
- int intno;
-
- interrupt_request = x86_cpu_pending_interrupt(cs, interrupt_request);
- if (!interrupt_request) {
- return false;
- }
-
- /* Don't process multiple interrupt requests in a single call.
- * This is required to make icount-driven execution deterministic.
- */
- switch (interrupt_request) {
- case CPU_INTERRUPT_POLL:
- cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
- apic_poll_irq(cpu->apic_state);
- break;
- case CPU_INTERRUPT_SIPI:
- do_cpu_sipi(cpu);
- break;
- case CPU_INTERRUPT_SMI:
- cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0);
- cs->interrupt_request &= ~CPU_INTERRUPT_SMI;
- do_smm_enter(cpu);
- break;
- case CPU_INTERRUPT_NMI:
- cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0);
- cs->interrupt_request &= ~CPU_INTERRUPT_NMI;
- env->hflags2 |= HF2_NMI_MASK;
- do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
- break;
- case CPU_INTERRUPT_MCE:
- cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
- do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
- break;
- case CPU_INTERRUPT_HARD:
- cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0);
- cs->interrupt_request &= ~(CPU_INTERRUPT_HARD |
- CPU_INTERRUPT_VIRQ);
- intno = cpu_get_pic_interrupt(env);
- qemu_log_mask(CPU_LOG_TB_IN_ASM,
- "Servicing hardware INT=0x%02x\n", intno);
- do_interrupt_x86_hardirq(env, intno, 1);
- break;
- case CPU_INTERRUPT_VIRQ:
- /* FIXME: this should respect TPR */
- cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0);
- intno = x86_ldl_phys(cs, env->vm_vmcb
- + offsetof(struct vmcb, control.int_vector));
- qemu_log_mask(CPU_LOG_TB_IN_ASM,
- "Servicing virtual hardware INT=0x%02x\n", intno);
- do_interrupt_x86_hardirq(env, intno, 1);
- cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
- break;
- }
-
- /* Ensure that no TB jump will be modified as the program flow was changed. */
- return true;
-}
-#endif /* CONFIG_USER_ONLY */
-
void helper_lldt(CPUX86State *env, int selector)
{
SegmentCache *dt;
diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/seg_helper.c
index 82c0856c417..b425b930f9d 100644
--- a/target/i386/tcg/sysemu/seg_helper.c
+++ b/target/i386/tcg/sysemu/seg_helper.c
@@ -125,6 +125,71 @@ void x86_cpu_do_interrupt(CPUState *cs)
}
}
+bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+ int intno;
+
+ interrupt_request = x86_cpu_pending_interrupt(cs, interrupt_request);
+ if (!interrupt_request) {
+ return false;
+ }
+
+ /*
+ * Don't process multiple interrupt requests in a single call.
+ * This is required to make icount-driven execution deterministic.
+ */
+ switch (interrupt_request) {
+ case CPU_INTERRUPT_POLL:
+ cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
+ apic_poll_irq(cpu->apic_state);
+ break;
+ case CPU_INTERRUPT_SIPI:
+ do_cpu_sipi(cpu);
+ break;
+ case CPU_INTERRUPT_SMI:
+ cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0);
+ cs->interrupt_request &= ~CPU_INTERRUPT_SMI;
+ do_smm_enter(cpu);
+ break;
+ case CPU_INTERRUPT_NMI:
+ cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0);
+ cs->interrupt_request &= ~CPU_INTERRUPT_NMI;
+ env->hflags2 |= HF2_NMI_MASK;
+ do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
+ break;
+ case CPU_INTERRUPT_MCE:
+ cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
+ do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
+ break;
+ case CPU_INTERRUPT_HARD:
+ cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0);
+ cs->interrupt_request &= ~(CPU_INTERRUPT_HARD |
+ CPU_INTERRUPT_VIRQ);
+ intno = cpu_get_pic_interrupt(env);
+ qemu_log_mask(CPU_LOG_TB_IN_ASM,
+ "Servicing hardware INT=0x%02x\n", intno);
+ do_interrupt_x86_hardirq(env, intno, 1);
+ break;
+ case CPU_INTERRUPT_VIRQ:
+ /* FIXME: this should respect TPR */
+ cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0);
+ intno = x86_ldl_phys(cs, env->vm_vmcb
+ + offsetof(struct vmcb, control.int_vector));
+ qemu_log_mask(CPU_LOG_TB_IN_ASM,
+ "Servicing virtual hardware INT=0x%02x\n", intno);
+ do_interrupt_x86_hardirq(env, intno, 1);
+ cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
+ break;
+ }
+
+ /*
+ * Ensure that no TB jump will be modified as the program flow was changed.
+ */
+ return true;
+}
+
/* check if Port I/O is allowed in TSS */
void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size)
{
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 12/24] target/m68k: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 13/24] target/microblaze: " Philippe Mathieu-Daudé
` (11 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/m68k/cpu.h | 2 ++
target/m68k/cpu.c | 2 +-
target/m68k/op_helper.c | 16 +++-------------
3 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 997d588911c..550eb028b6e 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -166,8 +166,10 @@ struct M68kCPU {
};
+#ifndef CONFIG_USER_ONLY
void m68k_cpu_do_interrupt(CPUState *cpu);
bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
+#endif /* !CONFIG_USER_ONLY */
void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 72de6e97262..66d22d11895 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -515,10 +515,10 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
static const struct TCGCPUOps m68k_tcg_ops = {
.initialize = m68k_tcg_init,
- .cpu_exec_interrupt = m68k_cpu_exec_interrupt,
.tlb_fill = m68k_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = m68k_cpu_exec_interrupt,
.do_interrupt = m68k_cpu_do_interrupt,
.do_transaction_failed = m68k_cpu_transaction_failed,
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index d006d1cb3ea..5d624838ae6 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -24,18 +24,7 @@
#include "semihosting/semihost.h"
#include "tcg/tcg.h"
-#if defined(CONFIG_USER_ONLY)
-
-void m68k_cpu_do_interrupt(CPUState *cs)
-{
- cs->exception_index = -1;
-}
-
-static inline void do_interrupt_m68k_hardirq(CPUM68KState *env)
-{
-}
-
-#else
+#if !defined(CONFIG_USER_ONLY)
static void cf_rte(CPUM68KState *env)
{
@@ -516,7 +505,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
cpu_loop_exit(cs);
}
}
-#endif
bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
@@ -538,6 +526,8 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return false;
}
+#endif /* !CONFIG_USER_ONLY */
+
static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
{
CPUState *cs = env_cpu(env);
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 13/24] target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 12/24] target/m68k: Restrict cpu_exec_interrupt() handler to sysemu Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 14/24] target/mips: " Philippe Mathieu-Daudé
` (10 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/microblaze/cpu.h | 2 ++
target/microblaze/cpu.c | 2 +-
target/microblaze/helper.c | 13 ++-----------
3 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e4bba8a7551..40401c33b72 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -355,8 +355,10 @@ struct MicroBlazeCPU {
};
+#ifndef CONFIG_USER_ONLY
void mb_cpu_do_interrupt(CPUState *cs);
bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
+#endif /* !CONFIG_USER_ONLY */
void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 72d8f2a0daa..15db277925f 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -365,10 +365,10 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
static const struct TCGCPUOps mb_tcg_ops = {
.initialize = mb_tcg_init,
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
- .cpu_exec_interrupt = mb_cpu_exec_interrupt,
.tlb_fill = mb_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = mb_cpu_exec_interrupt,
.do_interrupt = mb_cpu_do_interrupt,
.do_transaction_failed = mb_cpu_transaction_failed,
.do_unaligned_access = mb_cpu_do_unaligned_access,
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 20dbd673136..dd2aecd1d58 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -26,16 +26,6 @@
#if defined(CONFIG_USER_ONLY)
-void mb_cpu_do_interrupt(CPUState *cs)
-{
- MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
- CPUMBState *env = &cpu->env;
-
- cs->exception_index = -1;
- env->res_addr = RES_ADDR_NONE;
- env->regs[14] = env->pc;
-}
-
bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
@@ -271,7 +261,6 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
return paddr;
}
-#endif
bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
@@ -289,6 +278,8 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return false;
}
+#endif /* !CONFIG_USER_ONLY */
+
void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 14/24] target/mips: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 13/24] target/microblaze: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 15/24] target/nios2: " Philippe Mathieu-Daudé
` (9 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/tcg-internal.h | 5 +++--
target/mips/cpu.c | 2 +-
target/mips/tcg/exception.c | 18 ------------------
target/mips/tcg/sysemu/tlb_helper.c | 18 ++++++++++++++++++
target/mips/tcg/user/tlb_helper.c | 5 -----
5 files changed, 22 insertions(+), 26 deletions(-)
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index 81b14eb219e..c7a77ddccdd 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -18,8 +18,6 @@
void mips_tcg_init(void);
void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
-void mips_cpu_do_interrupt(CPUState *cpu);
-bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
@@ -41,6 +39,9 @@ static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
#if !defined(CONFIG_USER_ONLY)
+void mips_cpu_do_interrupt(CPUState *cpu);
+bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
+
void mmu_init(CPUMIPSState *env, const mips_def_t *def);
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index d426918291a..00e0c55d0e4 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -539,10 +539,10 @@ static const struct SysemuCPUOps mips_sysemu_ops = {
static const struct TCGCPUOps mips_tcg_ops = {
.initialize = mips_tcg_init,
.synchronize_from_tb = mips_cpu_synchronize_from_tb,
- .cpu_exec_interrupt = mips_cpu_exec_interrupt,
.tlb_fill = mips_cpu_tlb_fill,
#if !defined(CONFIG_USER_ONLY)
+ .cpu_exec_interrupt = mips_cpu_exec_interrupt,
.do_interrupt = mips_cpu_do_interrupt,
.do_transaction_failed = mips_cpu_do_transaction_failed,
.do_unaligned_access = mips_cpu_do_unaligned_access,
diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c
index 4fb8b00711d..7b3026b105b 100644
--- a/target/mips/tcg/exception.c
+++ b/target/mips/tcg/exception.c
@@ -86,24 +86,6 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
}
-bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
- if (interrupt_request & CPU_INTERRUPT_HARD) {
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
-
- if (cpu_mips_hw_interrupts_enabled(env) &&
- cpu_mips_hw_interrupts_pending(env)) {
- /* Raise it */
- cs->exception_index = EXCP_EXT_INTERRUPT;
- env->error_code = 0;
- mips_cpu_do_interrupt(cs);
- return true;
- }
- }
- return false;
-}
-
static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_RESET] = "reset",
[EXCP_SRESET] = "soft reset",
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index a150a014ec1..73254d19298 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -1339,6 +1339,24 @@ void mips_cpu_do_interrupt(CPUState *cs)
cs->exception_index = EXCP_NONE;
}
+bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ if (interrupt_request & CPU_INTERRUPT_HARD) {
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
+ if (cpu_mips_hw_interrupts_enabled(env) &&
+ cpu_mips_hw_interrupts_pending(env)) {
+ /* Raise it */
+ cs->exception_index = EXCP_EXT_INTERRUPT;
+ env->error_code = 0;
+ mips_cpu_do_interrupt(cs);
+ return true;
+ }
+ }
+ return false;
+}
+
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
{
CPUState *cs = env_cpu(env);
diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_helper.c
index b835144b820..210c6d529ef 100644
--- a/target/mips/tcg/user/tlb_helper.c
+++ b/target/mips/tcg/user/tlb_helper.c
@@ -57,8 +57,3 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
raise_mmu_exception(env, address, access_type);
do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
}
-
-void mips_cpu_do_interrupt(CPUState *cs)
-{
- cs->exception_index = EXCP_NONE;
-}
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 15/24] target/nios2: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 14/24] target/mips: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 16/24] target/openrisc: " Philippe Mathieu-Daudé
` (8 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/nios2/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 5e37defef80..947bb09bc1e 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -127,6 +127,7 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
ncc->parent_realize(dev, errp);
}
+#ifndef CONFIG_USER_ONLY
static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
@@ -140,7 +141,7 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return false;
}
-
+#endif /* !CONFIG_USER_ONLY */
static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
@@ -219,10 +220,10 @@ static const struct SysemuCPUOps nios2_sysemu_ops = {
static const struct TCGCPUOps nios2_tcg_ops = {
.initialize = nios2_tcg_init,
- .cpu_exec_interrupt = nios2_cpu_exec_interrupt,
.tlb_fill = nios2_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = nios2_cpu_exec_interrupt,
.do_interrupt = nios2_cpu_do_interrupt,
.do_unaligned_access = nios2_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 16/24] target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 15/24] target/nios2: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 17/24] target/ppc: " Philippe Mathieu-Daudé
` (7 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/openrisc/cpu.h | 5 +++--
target/openrisc/cpu.c | 2 +-
target/openrisc/interrupt.c | 2 --
target/openrisc/meson.build | 6 ++++--
4 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 82cbaeb4f84..be6df81a810 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -312,8 +312,6 @@ struct OpenRISCCPU {
void cpu_openrisc_list(void);
-void openrisc_cpu_do_interrupt(CPUState *cpu);
-bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -331,6 +329,9 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *info);
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_openrisc_cpu;
+void openrisc_cpu_do_interrupt(CPUState *cpu);
+bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
+
/* hw/openrisc_pic.c */
void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index bd34e429ecb..27cb04152f9 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -186,10 +186,10 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
static const struct TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
- .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
.tlb_fill = openrisc_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
.do_interrupt = openrisc_cpu_do_interrupt,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 3eab771dcda..19223e3f25b 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -28,7 +28,6 @@
void openrisc_cpu_do_interrupt(CPUState *cs)
{
-#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
int exception = cs->exception_index;
@@ -96,7 +95,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
} else {
cpu_abort(cs, "Unhandled exception 0x%x\n", exception);
}
-#endif
cs->exception_index = -1;
}
diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build
index 9774a583065..e445dec4a00 100644
--- a/target/openrisc/meson.build
+++ b/target/openrisc/meson.build
@@ -9,7 +9,6 @@
'exception_helper.c',
'fpu_helper.c',
'gdbstub.c',
- 'interrupt.c',
'interrupt_helper.c',
'mmu.c',
'sys_helper.c',
@@ -17,7 +16,10 @@
))
openrisc_softmmu_ss = ss.source_set()
-openrisc_softmmu_ss.add(files('machine.c'))
+openrisc_softmmu_ss.add(files(
+ 'interrupt.c',
+ 'machine.c',
+))
target_arch += {'openrisc': openrisc_ss}
target_softmmu_arch += {'openrisc': openrisc_softmmu_ss}
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 17/24] target/ppc: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 16/24] target/openrisc: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 18/24] target/riscv: " Philippe Mathieu-Daudé
` (6 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: David Gibson, Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/ppc/cpu.h | 4 ++--
target/ppc/cpu_init.c | 2 +-
target/ppc/excp_helper.c | 21 +++------------------
3 files changed, 6 insertions(+), 21 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 500205229c0..362e7c4c5c7 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1254,8 +1254,6 @@ DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
#endif /* CONFIG_USER_ONLY */
-void ppc_cpu_do_interrupt(CPUState *cpu);
-bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -1271,6 +1269,8 @@ int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque);
#ifndef CONFIG_USER_ONLY
+void ppc_cpu_do_interrupt(CPUState *cpu);
+bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
void ppc_cpu_do_system_reset(CPUState *cs);
void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
extern const VMStateDescription vmstate_ppc_cpu;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ad7abc6041a..6aad01d1d3a 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9014,10 +9014,10 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
static const struct TCGCPUOps ppc_tcg_ops = {
.initialize = ppc_translate_init,
- .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
.tlb_fill = ppc_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
.do_interrupt = ppc_cpu_do_interrupt,
.cpu_exec_enter = ppc_cpu_exec_enter,
.cpu_exec_exit = ppc_cpu_exec_exit,
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 7b6ac16eef7..d7e32ee107e 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -40,24 +40,8 @@
/*****************************************************************************/
/* Exception processing */
-#if defined(CONFIG_USER_ONLY)
-void ppc_cpu_do_interrupt(CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+#if !defined(CONFIG_USER_ONLY)
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
-}
-
-static void ppc_hw_interrupt(CPUPPCState *env)
-{
- CPUState *cs = env_cpu(env);
-
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
-}
-#else /* defined(CONFIG_USER_ONLY) */
static inline void dump_syscall(CPUPPCState *env)
{
qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64
@@ -1113,7 +1097,6 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector)
powerpc_set_excp_state(cpu, vector, msr);
}
-#endif /* !CONFIG_USER_ONLY */
bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
@@ -1130,6 +1113,8 @@ bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return false;
}
+#endif /* !CONFIG_USER_ONLY */
+
#if defined(DEBUG_OP)
static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
{
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 18/24] target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 17/24] target/ppc: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-05 15:59 ` Bin Meng
2021-09-04 23:55 ` [PATCH v2 19/24] target/sh4: " Philippe Mathieu-Daudé
` (5 subsequent siblings)
23 siblings, 1 reply; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 5 -----
3 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bf1c899c00b..e735e53e26c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -334,7 +334,6 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
@@ -362,6 +361,7 @@ void riscv_cpu_list(void);
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
+bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1a2b03d579c..13575c14085 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -644,10 +644,10 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
static const struct TCGCPUOps riscv_tcg_ops = {
.initialize = riscv_translate_init,
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
- .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
.tlb_fill = riscv_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
.do_interrupt = riscv_cpu_do_interrupt,
.do_transaction_failed = riscv_cpu_do_transaction_failed,
.do_unaligned_access = riscv_cpu_do_unaligned_access,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 968cb8046f4..701858d670c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -75,11 +75,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
return RISCV_EXCP_NONE; /* indicates no pending interrupt */
}
}
-#endif
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
-#if !defined(CONFIG_USER_ONLY)
if (interrupt_request & CPU_INTERRUPT_HARD) {
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
@@ -90,12 +88,9 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return true;
}
}
-#endif
return false;
}
-#if !defined(CONFIG_USER_ONLY)
-
/* Return true is floating point support is currently enabled */
bool riscv_cpu_fp_enabled(CPURISCVState *env)
{
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 19/24] target/sh4: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 18/24] target/riscv: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 20/24] target/sparc: " Philippe Mathieu-Daudé
` (4 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/sh4/cpu.h | 4 ++--
target/sh4/cpu.c | 2 +-
target/sh4/helper.c | 9 ++-------
3 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 01c43440822..017a7702140 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -204,8 +204,6 @@ struct SuperHCPU {
};
-void superh_cpu_do_interrupt(CPUState *cpu);
-bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -223,6 +221,8 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
void sh4_cpu_list(void);
#if !defined(CONFIG_USER_ONLY)
+void superh_cpu_do_interrupt(CPUState *cpu);
+bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
void cpu_sh4_invalidate_tlb(CPUSH4State *s);
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
hwaddr addr);
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 83269229421..2047742d03c 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -236,10 +236,10 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
static const struct TCGCPUOps superh_tcg_ops = {
.initialize = sh4_translate_init,
.synchronize_from_tb = superh_cpu_synchronize_from_tb,
- .cpu_exec_interrupt = superh_cpu_exec_interrupt,
.tlb_fill = superh_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = superh_cpu_exec_interrupt,
.do_interrupt = superh_cpu_do_interrupt,
.do_unaligned_access = superh_cpu_do_unaligned_access,
.io_recompile_replay_branch = superh_io_recompile_replay_branch,
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 2d622081e85..53cb9c3b631 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -45,11 +45,6 @@
#if defined(CONFIG_USER_ONLY)
-void superh_cpu_do_interrupt(CPUState *cs)
-{
- cs->exception_index = -1;
-}
-
int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr)
{
/* For user mode, only U0 area is cacheable. */
@@ -784,8 +779,6 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
return 0;
}
-#endif
-
bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
@@ -803,6 +796,8 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return false;
}
+#endif /* !CONFIG_USER_ONLY */
+
bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 20/24] target/sparc: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 19/24] target/sh4: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 21/24] target/rx: " Philippe Mathieu-Daudé
` (3 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/sparc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index da6b30ec747..5a8a4ce7506 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -77,6 +77,7 @@ static void sparc_cpu_reset(DeviceState *dev)
env->cache_control = 0;
}
+#ifndef CONFIG_USER_ONLY
static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
@@ -96,6 +97,7 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return false;
}
+#endif /* !CONFIG_USER_ONLY */
static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
{
@@ -863,10 +865,10 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
static const struct TCGCPUOps sparc_tcg_ops = {
.initialize = sparc_tcg_init,
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
- .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
.tlb_fill = sparc_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
.do_interrupt = sparc_cpu_do_interrupt,
.do_transaction_failed = sparc_cpu_do_transaction_failed,
.do_unaligned_access = sparc_cpu_do_unaligned_access,
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 21/24] target/rx: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (19 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 20/24] target/sparc: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 22/24] target/xtensa: " Philippe Mathieu-Daudé
` (2 subsequent siblings)
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/rx/cpu.h | 2 ++
target/rx/cpu.c | 2 +-
target/rx/helper.c | 4 ++++
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 0b4b998c7be..faa3606f52f 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -124,8 +124,10 @@ typedef RXCPU ArchCPU;
#define CPU_RESOLVING_TYPE TYPE_RX_CPU
const char *rx_crname(uint8_t cr);
+#ifndef CONFIG_USER_ONLY
void rx_cpu_do_interrupt(CPUState *cpu);
bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
+#endif /* !CONFIG_USER_ONLY */
void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 96cc96e514f..25a4aa2976d 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -186,10 +186,10 @@ static const struct SysemuCPUOps rx_sysemu_ops = {
static const struct TCGCPUOps rx_tcg_ops = {
.initialize = rx_translate_init,
.synchronize_from_tb = rx_cpu_synchronize_from_tb,
- .cpu_exec_interrupt = rx_cpu_exec_interrupt,
.tlb_fill = rx_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = rx_cpu_exec_interrupt,
.do_interrupt = rx_cpu_do_interrupt,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/rx/helper.c b/target/rx/helper.c
index db6b07e3890..f34945e7e2c 100644
--- a/target/rx/helper.c
+++ b/target/rx/helper.c
@@ -40,6 +40,8 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte)
env->psw_c = FIELD_EX32(psw, PSW, C);
}
+#ifndef CONFIG_USER_ONLY
+
#define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR)
void rx_cpu_do_interrupt(CPUState *cs)
{
@@ -142,6 +144,8 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return false;
}
+#endif /* !CONFIG_USER_ONLY */
+
hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
return addr;
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 22/24] target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (20 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 21/24] target/rx: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 24/24] user: Remove cpu_get_pic_interrupt() stubs Philippe Mathieu-Daudé
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/xtensa/cpu.h | 4 ++--
target/xtensa/cpu.c | 2 +-
target/xtensa/exc_helper.c | 7 ++-----
3 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 1e0cb1535ca..cbb720e7cca 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -566,14 +566,14 @@ struct XtensaCPU {
bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+#ifndef CONFIG_USER_ONLY
void xtensa_cpu_do_interrupt(CPUState *cpu);
bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
-#ifndef CONFIG_USER_ONLY
void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
-#endif /* !CONFIG_USER_ONLY */
+#endif
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void xtensa_count_regs(const XtensaConfig *config,
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 58ec3a08622..c1cbd03595e 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -192,11 +192,11 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
static const struct TCGCPUOps xtensa_tcg_ops = {
.initialize = xtensa_translate_init,
- .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
.tlb_fill = xtensa_cpu_tlb_fill,
.debug_excp_handler = xtensa_breakpoint_handler,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
.do_interrupt = xtensa_cpu_do_interrupt,
.do_transaction_failed = xtensa_cpu_do_transaction_failed,
.do_unaligned_access = xtensa_cpu_do_unaligned_access,
diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c
index 10e75ab070d..9bc7f50d355 100644
--- a/target/xtensa/exc_helper.c
+++ b/target/xtensa/exc_helper.c
@@ -255,11 +255,6 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
}
check_interrupts(env);
}
-#else
-void xtensa_cpu_do_interrupt(CPUState *cs)
-{
-}
-#endif
bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
@@ -270,3 +265,5 @@ bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return false;
}
+
+#endif /* !CONFIG_USER_ONLY */
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (21 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 22/24] target/xtensa: " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 24/24] user: Remove cpu_get_pic_interrupt() stubs Philippe Mathieu-Daudé
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
All targets call TCGCPUOps::cpu_exec_interrupt() from sysemu code.
Move its declaration to restrict it to system emulation.
Extend the code guarded.
Restrict the static inlined need_replay_interrupt() method to
avoid a "defined but not used" warning.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/tcg-cpu-ops.h | 4 ++--
accel/tcg/cpu-exec.c | 10 +++++++---
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 6c7ab9600ba..55123cb4d22 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -35,8 +35,6 @@ struct TCGCPUOps {
void (*cpu_exec_enter)(CPUState *cpu);
/** @cpu_exec_exit: Callback for cpu_exec cleanup */
void (*cpu_exec_exit)(CPUState *cpu);
- /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
- bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
/**
* @tlb_fill: Handle a softmmu tlb miss or user-only address fault
*
@@ -68,6 +66,8 @@ struct TCGCPUOps {
void (*do_interrupt)(CPUState *cpu);
#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
#ifdef CONFIG_SOFTMMU
+ /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
+ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
/**
* @do_transaction_failed: Callback for handling failed memory transactions
* (ie bus faults or external aborts; not MMU faults)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 2838177e7f0..75dbc1e4e33 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -685,6 +685,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
return false;
}
+#ifndef CONFIG_USER_ONLY
/*
* CPU_INTERRUPT_POLL is a virtual event which gets converted into a
* "real" interrupt event later. It does not need to be recorded for
@@ -698,12 +699,11 @@ static inline bool need_replay_interrupt(int interrupt_request)
return true;
#endif
}
+#endif /* !CONFIG_USER_ONLY */
static inline bool cpu_handle_interrupt(CPUState *cpu,
TranslationBlock **last_tb)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
/* Clear the interrupt flag now since we're processing
* cpu->interrupt_request and cpu->exit_request.
* Ensure zeroing happens before reading cpu->exit_request or
@@ -725,6 +725,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
qemu_mutex_unlock_iothread();
return true;
}
+#if !defined(CONFIG_USER_ONLY)
if (replay_mode == REPLAY_MODE_PLAY && !replay_has_interrupt()) {
/* Do nothing */
} else if (interrupt_request & CPU_INTERRUPT_HALT) {
@@ -753,12 +754,14 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
qemu_mutex_unlock_iothread();
return true;
}
-#endif
+#endif /* !TARGET_I386 */
/* The target hook has 3 exit conditions:
False when the interrupt isn't processed,
True when it is, and we should restart on a new TB,
and via longjmp via cpu_loop_exit. */
else {
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
if (cc->tcg_ops->cpu_exec_interrupt &&
cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) {
if (need_replay_interrupt(interrupt_request)) {
@@ -777,6 +780,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
* reload the 'interrupt_request' value */
interrupt_request = cpu->interrupt_request;
}
+#endif /* !CONFIG_USER_ONLY */
if (interrupt_request & CPU_INTERRUPT_EXITTB) {
cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
/* ensure that no TB jump will be modified as
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 24/24] user: Remove cpu_get_pic_interrupt() stubs
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
` (22 preceding siblings ...)
2021-09-04 23:55 ` [PATCH v2 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() " Philippe Mathieu-Daudé
@ 2021-09-04 23:55 ` Philippe Mathieu-Daudé
23 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-04 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Laurent Vivier, Warner Losh,
Philippe Mathieu-Daudé
cpu_get_pic_interrupt() is now unreachable from user-mode,
delete the unnecessary stubs.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/i386/cpu.h | 2 +-
bsd-user/main.c | 7 -------
linux-user/main.c | 7 -------
3 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index c241bc183d2..c7cc65e92d5 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1832,9 +1832,9 @@ int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void x86_cpu_list(void);
int cpu_x86_support_mca_broadcast(CPUX86State *env);
+#ifndef CONFIG_USER_ONLY
int cpu_get_pic_interrupt(CPUX86State *s);
-#ifndef CONFIG_USER_ONLY
/* MSDOS compatibility mode FPU exception support */
void x86_register_ferr_irq(qemu_irq irq);
void fpu_check_raise_ferr_irq(CPUX86State *s);
diff --git a/bsd-user/main.c b/bsd-user/main.c
index fe66204b6b7..e358c38c353 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -66,13 +66,6 @@ void gemu_log(const char *fmt, ...)
va_end(ap);
}
-#if defined(TARGET_I386)
-int cpu_get_pic_interrupt(CPUX86State *env)
-{
- return -1;
-}
-#endif
-
void fork_start(void)
{
}
diff --git a/linux-user/main.c b/linux-user/main.c
index a6094563b6b..45bde4598d5 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -120,13 +120,6 @@ const char *qemu_uname_release;
by remapping the process stack directly at the right place */
unsigned long guest_stack_size = 8 * 1024 * 1024UL;
-#if defined(TARGET_I386)
-int cpu_get_pic_interrupt(CPUX86State *env)
-{
- return -1;
-}
-#endif
-
/***********************************************************/
/* Helper routines for implementing atomic operations. */
--
2.31.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v2 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition
2021-09-04 23:55 ` [PATCH v2 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition Philippe Mathieu-Daudé
@ 2021-09-05 8:29 ` Richard Henderson
2021-09-05 14:24 ` Warner Losh
1 sibling, 0 replies; 30+ messages in thread
From: Richard Henderson @ 2021-09-05 8:29 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Laurent Vivier, Warner Losh
On 9/5/21 1:55 AM, Philippe Mathieu-Daudé wrote:
> Commit f1c671f96cb ("target/avr: Introduce basic CPU class object")
> added to target/avr/cpu.h:
>
> #ifdef CONFIG_USER_ONLY
> #error "AVR 8-bit does not support user mode"
> #endif
>
> Remove the CONFIG_USER_ONLY definition introduced by mistake in
> commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a
> pointer in CPUClass").
>
> Reported-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/avr/cpu.c | 3 ---
> 1 file changed, 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder
2021-09-04 23:55 ` [PATCH v2 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder Philippe Mathieu-Daudé
@ 2021-09-05 8:35 ` Richard Henderson
2021-09-05 14:26 ` Warner Losh
1 sibling, 0 replies; 30+ messages in thread
From: Richard Henderson @ 2021-09-05 8:35 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Laurent Vivier, Warner Losh
On 9/5/21 1:55 AM, Philippe Mathieu-Daudé wrote:
> Following the logic of commit 30493a030ff ("i386: split seg_helper
> into user-only and sysemu parts"), move x86_cpu_exec_interrupt()
> under sysemu/seg_helper.c.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> I prefer to not squash this into the previous patch because the
> ifdef'ry removal (in previous patch) is not trivial IMO.
> ---
> target/i386/tcg/seg_helper.c | 64 ----------------------------
> target/i386/tcg/sysemu/seg_helper.c | 65 +++++++++++++++++++++++++++++
> 2 files changed, 65 insertions(+), 64 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition
2021-09-04 23:55 ` [PATCH v2 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition Philippe Mathieu-Daudé
2021-09-05 8:29 ` Richard Henderson
@ 2021-09-05 14:24 ` Warner Losh
1 sibling, 0 replies; 30+ messages in thread
From: Warner Losh @ 2021-09-05 14:24 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Richard Henderson, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 1275 bytes --]
On Sat, Sep 4, 2021 at 5:55 PM Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Commit f1c671f96cb ("target/avr: Introduce basic CPU class object")
> added to target/avr/cpu.h:
>
> #ifdef CONFIG_USER_ONLY
> #error "AVR 8-bit does not support user mode"
> #endif
>
> Remove the CONFIG_USER_ONLY definition introduced by mistake in
> commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a
> pointer in CPUClass").
>
> Reported-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/avr/cpu.c | 3 ---
> 1 file changed, 3 deletions(-)
>
Reviewed-By: Warner Losh <imp@bsdimp.com>
> diff --git a/target/avr/cpu.c b/target/avr/cpu.c
> index ea14175ca55..5d70e34dd54 100644
> --- a/target/avr/cpu.c
> +++ b/target/avr/cpu.c
> @@ -197,10 +197,7 @@ static const struct TCGCPUOps avr_tcg_ops = {
> .synchronize_from_tb = avr_cpu_synchronize_from_tb,
> .cpu_exec_interrupt = avr_cpu_exec_interrupt,
> .tlb_fill = avr_cpu_tlb_fill,
> -
> -#ifndef CONFIG_USER_ONLY
> .do_interrupt = avr_cpu_do_interrupt,
> -#endif /* !CONFIG_USER_ONLY */
> };
>
> static void avr_cpu_class_init(ObjectClass *oc, void *data)
> --
> 2.31.1
>
>
[-- Attachment #2: Type: text/html, Size: 2053 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder
2021-09-04 23:55 ` [PATCH v2 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder Philippe Mathieu-Daudé
2021-09-05 8:35 ` Richard Henderson
@ 2021-09-05 14:26 ` Warner Losh
1 sibling, 0 replies; 30+ messages in thread
From: Warner Losh @ 2021-09-05 14:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Richard Henderson, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 6780 bytes --]
On Sat, Sep 4, 2021 at 5:56 PM Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Following the logic of commit 30493a030ff ("i386: split seg_helper
> into user-only and sysemu parts"), move x86_cpu_exec_interrupt()
> under sysemu/seg_helper.c.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> I prefer to not squash this into the previous patch because the
> ifdef'ry removal (in previous patch) is not trivial IMO.
> ---
> target/i386/tcg/seg_helper.c | 64 ----------------------------
> target/i386/tcg/sysemu/seg_helper.c | 65 +++++++++++++++++++++++++++++
> 2 files changed, 65 insertions(+), 64 deletions(-)
>
Reviewed-By: Warner Losh <imp@bsdimp.com>
> diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
> index 13c6e6ee62e..baa905a0cd6 100644
> --- a/target/i386/tcg/seg_helper.c
> +++ b/target/i386/tcg/seg_helper.c
> @@ -1110,70 +1110,6 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int
> intno, int is_hw)
> do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw);
> }
>
> -#ifndef CONFIG_USER_ONLY
> -bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> -{
> - X86CPU *cpu = X86_CPU(cs);
> - CPUX86State *env = &cpu->env;
> - int intno;
> -
> - interrupt_request = x86_cpu_pending_interrupt(cs, interrupt_request);
> - if (!interrupt_request) {
> - return false;
> - }
> -
> - /* Don't process multiple interrupt requests in a single call.
> - * This is required to make icount-driven execution deterministic.
> - */
> - switch (interrupt_request) {
> - case CPU_INTERRUPT_POLL:
> - cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
> - apic_poll_irq(cpu->apic_state);
> - break;
> - case CPU_INTERRUPT_SIPI:
> - do_cpu_sipi(cpu);
> - break;
> - case CPU_INTERRUPT_SMI:
> - cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0);
> - cs->interrupt_request &= ~CPU_INTERRUPT_SMI;
> - do_smm_enter(cpu);
> - break;
> - case CPU_INTERRUPT_NMI:
> - cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0);
> - cs->interrupt_request &= ~CPU_INTERRUPT_NMI;
> - env->hflags2 |= HF2_NMI_MASK;
> - do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
> - break;
> - case CPU_INTERRUPT_MCE:
> - cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
> - do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
> - break;
> - case CPU_INTERRUPT_HARD:
> - cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0);
> - cs->interrupt_request &= ~(CPU_INTERRUPT_HARD |
> - CPU_INTERRUPT_VIRQ);
> - intno = cpu_get_pic_interrupt(env);
> - qemu_log_mask(CPU_LOG_TB_IN_ASM,
> - "Servicing hardware INT=0x%02x\n", intno);
> - do_interrupt_x86_hardirq(env, intno, 1);
> - break;
> - case CPU_INTERRUPT_VIRQ:
> - /* FIXME: this should respect TPR */
> - cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0);
> - intno = x86_ldl_phys(cs, env->vm_vmcb
> - + offsetof(struct vmcb, control.int_vector));
> - qemu_log_mask(CPU_LOG_TB_IN_ASM,
> - "Servicing virtual hardware INT=0x%02x\n", intno);
> - do_interrupt_x86_hardirq(env, intno, 1);
> - cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
> - break;
> - }
> -
> - /* Ensure that no TB jump will be modified as the program flow was
> changed. */
> - return true;
> -}
> -#endif /* CONFIG_USER_ONLY */
> -
> void helper_lldt(CPUX86State *env, int selector)
> {
> SegmentCache *dt;
> diff --git a/target/i386/tcg/sysemu/seg_helper.c
> b/target/i386/tcg/sysemu/seg_helper.c
> index 82c0856c417..b425b930f9d 100644
> --- a/target/i386/tcg/sysemu/seg_helper.c
> +++ b/target/i386/tcg/sysemu/seg_helper.c
> @@ -125,6 +125,71 @@ void x86_cpu_do_interrupt(CPUState *cs)
> }
> }
>
> +bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> +{
> + X86CPU *cpu = X86_CPU(cs);
> + CPUX86State *env = &cpu->env;
> + int intno;
> +
> + interrupt_request = x86_cpu_pending_interrupt(cs, interrupt_request);
> + if (!interrupt_request) {
> + return false;
> + }
> +
> + /*
> + * Don't process multiple interrupt requests in a single call.
> + * This is required to make icount-driven execution deterministic.
> + */
> + switch (interrupt_request) {
> + case CPU_INTERRUPT_POLL:
> + cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
> + apic_poll_irq(cpu->apic_state);
> + break;
> + case CPU_INTERRUPT_SIPI:
> + do_cpu_sipi(cpu);
> + break;
> + case CPU_INTERRUPT_SMI:
> + cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0);
> + cs->interrupt_request &= ~CPU_INTERRUPT_SMI;
> + do_smm_enter(cpu);
> + break;
> + case CPU_INTERRUPT_NMI:
> + cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0);
> + cs->interrupt_request &= ~CPU_INTERRUPT_NMI;
> + env->hflags2 |= HF2_NMI_MASK;
> + do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
> + break;
> + case CPU_INTERRUPT_MCE:
> + cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
> + do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
> + break;
> + case CPU_INTERRUPT_HARD:
> + cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0);
> + cs->interrupt_request &= ~(CPU_INTERRUPT_HARD |
> + CPU_INTERRUPT_VIRQ);
> + intno = cpu_get_pic_interrupt(env);
> + qemu_log_mask(CPU_LOG_TB_IN_ASM,
> + "Servicing hardware INT=0x%02x\n", intno);
> + do_interrupt_x86_hardirq(env, intno, 1);
> + break;
> + case CPU_INTERRUPT_VIRQ:
> + /* FIXME: this should respect TPR */
> + cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0);
> + intno = x86_ldl_phys(cs, env->vm_vmcb
> + + offsetof(struct vmcb, control.int_vector));
> + qemu_log_mask(CPU_LOG_TB_IN_ASM,
> + "Servicing virtual hardware INT=0x%02x\n", intno);
> + do_interrupt_x86_hardirq(env, intno, 1);
> + cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
> + break;
> + }
> +
> + /*
> + * Ensure that no TB jump will be modified as the program flow was
> changed.
> + */
> + return true;
> +}
> +
> /* check if Port I/O is allowed in TSS */
> void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size)
> {
> --
> 2.31.1
>
>
[-- Attachment #2: Type: text/html, Size: 8341 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 18/24] target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
2021-09-04 23:55 ` [PATCH v2 18/24] target/riscv: " Philippe Mathieu-Daudé
@ 2021-09-05 15:59 ` Bin Meng
0 siblings, 0 replies; 30+ messages in thread
From: Bin Meng @ 2021-09-05 15:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Richard Henderson, qemu-devel@nongnu.org Developers, Warner Losh,
Laurent Vivier
On Sun, Sep 5, 2021 at 8:06 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Restrict cpu_exec_interrupt() and its callees to sysemu.
>
> Reviewed-by: Warner Losh <imp@bsdimp.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/riscv/cpu.h | 2 +-
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu_helper.c | 5 -----
> 3 files changed, 2 insertions(+), 7 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2021-09-05 16:03 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-04 23:55 [PATCH v2 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition Philippe Mathieu-Daudé
2021-09-05 8:29 ` Richard Henderson
2021-09-05 14:24 ` Warner Losh
2021-09-04 23:55 ` [PATCH v2 02/24] target/i386: Restrict sysemu-only fpu_helper helpers Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 03/24] target/i386: Simplify TARGET_X86_64 #ifdef'ry Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 04/24] target/xtensa: Restrict do_transaction_failed() to sysemu Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 05/24] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 06/24] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 07/24] target/arm: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 08/24] target/cris: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 09/24] target/hppa: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 10/24] target/i386: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder Philippe Mathieu-Daudé
2021-09-05 8:35 ` Richard Henderson
2021-09-05 14:26 ` Warner Losh
2021-09-04 23:55 ` [PATCH v2 12/24] target/m68k: Restrict cpu_exec_interrupt() handler to sysemu Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 13/24] target/microblaze: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 14/24] target/mips: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 15/24] target/nios2: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 16/24] target/openrisc: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 17/24] target/ppc: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 18/24] target/riscv: " Philippe Mathieu-Daudé
2021-09-05 15:59 ` Bin Meng
2021-09-04 23:55 ` [PATCH v2 19/24] target/sh4: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 20/24] target/sparc: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 21/24] target/rx: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 22/24] target/xtensa: " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() " Philippe Mathieu-Daudé
2021-09-04 23:55 ` [PATCH v2 24/24] user: Remove cpu_get_pic_interrupt() stubs Philippe Mathieu-Daudé
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