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From: Agustin Gutierrez <agustin.gutierrez@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <Harry.Wentland@amd.com>, <Sunpeng.Li@amd.com>,
	<Bhawanpreet.Lakha@amd.com>, <Rodrigo.Siqueira@amd.com>,
	<Aurabindo.Pillai@amd.com>, <qingqing.zhuo@amd.com>,
	<mikita.lipski@amd.com>,  <roman.li@amd.com>,
	<Anson.Jacob@amd.com>, <wayne.lin@amd.com>, <stylon.wang@amd.com>,
	<solomon.chiu@amd.com>, <pavle.kotarac@amd.com>,
	<agustin.gutierrez@amd.com>, Jake Wang <haonan.wang2@amd.com>,
	Nikola Cornij <Nikola.Cornij@amd.com>
Subject: [PATCH 14/27] drm/amd/display: Disable dsc root clock when not being used
Date: Fri, 15 Oct 2021 14:43:19 -0400	[thread overview]
Message-ID: <20211015184332.221091-15-agustin.gutierrez@amd.com> (raw)
In-Reply-To: <20211015184332.221091-1-agustin.gutierrez@amd.com>

From: Jake Wang <haonan.wang2@amd.com>

[Why & How]
Disable root clock for dsc when not being used.

Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 16 ++++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 72 +++++++++++++++++++
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h | 18 ++++-
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c    | 17 +++++
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |  9 +++
 5 files changed, 129 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index ede65100a050..f6f2d48a70c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -169,7 +169,17 @@
 	type DTBCLK_DTO_DIV[MAX_PIPES];\
 	type DCCG_AUDIO_DTO_SEL;\
 	type DCCG_AUDIO_DTO0_SOURCE_SEL;\
-	type DENTIST_DISPCLK_CHG_MODE;
+	type DENTIST_DISPCLK_CHG_MODE;\
+	type DSCCLK0_DTO_PHASE;\
+	type DSCCLK0_DTO_MODULO;\
+	type DSCCLK1_DTO_PHASE;\
+	type DSCCLK1_DTO_MODULO;\
+	type DSCCLK2_DTO_PHASE;\
+	type DSCCLK2_DTO_MODULO;\
+	type DSCCLK0_DTO_ENABLE;\
+	type DSCCLK1_DTO_ENABLE;\
+	type DSCCLK2_DTO_ENABLE;
+
 
 struct dccg_shift {
 	DCCG_REG_FIELD_LIST(uint8_t)
@@ -205,6 +215,10 @@ struct dccg_registers {
 	uint32_t SYMCLK32_SE_CNTL;
 	uint32_t SYMCLK32_LE_CNTL;
 	uint32_t DENTIST_DISPCLK_CNTL;
+	uint32_t DSCCLK_DTO_CTRL;
+	uint32_t DSCCLK0_DTO_PARAM;
+	uint32_t DSCCLK1_DTO_PARAM;
+	uint32_t DSCCLK2_DTO_PARAM;
 };
 
 struct dcn_dccg {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 152adb597d48..3a325e4afe2f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -247,6 +247,76 @@ void dccg31_disable_symclk32_le(
 	}
 }
 
+static void dccg31_disable_dscclk(struct dccg *dccg, int inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
+		return;
+	//DTO must be enabled to generate a 0 Hz clock output
+	switch (inst) {
+	case 0:
+		REG_UPDATE(DSCCLK_DTO_CTRL,
+				DSCCLK0_DTO_ENABLE, 1);
+		REG_UPDATE_2(DSCCLK0_DTO_PARAM,
+				DSCCLK0_DTO_PHASE, 0,
+				DSCCLK0_DTO_MODULO, 1);
+		break;
+	case 1:
+		REG_UPDATE(DSCCLK_DTO_CTRL,
+				DSCCLK1_DTO_ENABLE, 1);
+		REG_UPDATE_2(DSCCLK1_DTO_PARAM,
+				DSCCLK1_DTO_PHASE, 0,
+				DSCCLK1_DTO_MODULO, 1);
+		break;
+	case 2:
+		REG_UPDATE(DSCCLK_DTO_CTRL,
+				DSCCLK2_DTO_ENABLE, 1);
+		REG_UPDATE_2(DSCCLK2_DTO_PARAM,
+				DSCCLK2_DTO_PHASE, 0,
+				DSCCLK2_DTO_MODULO, 1);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+}
+
+static void dccg31_enable_dscclk(struct dccg *dccg, int inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
+		return;
+	//Disable DTO
+	switch (inst) {
+	case 0:
+		REG_UPDATE_2(DSCCLK0_DTO_PARAM,
+				DSCCLK0_DTO_PHASE, 0,
+				DSCCLK0_DTO_MODULO, 0);
+		REG_UPDATE(DSCCLK_DTO_CTRL,
+				DSCCLK0_DTO_ENABLE, 0);
+		break;
+	case 1:
+		REG_UPDATE_2(DSCCLK1_DTO_PARAM,
+				DSCCLK1_DTO_PHASE, 0,
+				DSCCLK1_DTO_MODULO, 0);
+		REG_UPDATE(DSCCLK_DTO_CTRL,
+				DSCCLK1_DTO_ENABLE, 0);
+		break;
+	case 2:
+		REG_UPDATE_2(DSCCLK2_DTO_PARAM,
+				DSCCLK2_DTO_PHASE, 0,
+				DSCCLK2_DTO_MODULO, 0);
+		REG_UPDATE(DSCCLK_DTO_CTRL,
+				DSCCLK2_DTO_ENABLE, 0);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+}
+
 void dccg31_set_physymclk(
 		struct dccg *dccg,
 		int phy_inst,
@@ -469,6 +539,8 @@ static const struct dccg_funcs dccg31_funcs = {
 	.set_dtbclk_dto = dccg31_set_dtbclk_dto,
 	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
 	.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,
+	.disable_dsc = dccg31_disable_dscclk,
+	.enable_dsc = dccg31_enable_dscclk,
 };
 
 struct dccg *dccg31_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index 1e5aabcb7799..61b457ab790d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -61,7 +61,11 @@
 	SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\
 	SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\
 	SR(DCCG_AUDIO_DTO_SOURCE),\
-	SR(DENTIST_DISPCLK_CNTL)
+	SR(DENTIST_DISPCLK_CNTL),\
+	SR(DSCCLK0_DTO_PARAM),\
+	SR(DSCCLK1_DTO_PARAM),\
+	SR(DSCCLK2_DTO_PARAM),\
+	SR(DSCCLK_DTO_CTRL)
 
 
 #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \
@@ -119,7 +123,17 @@
 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\
 	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
 	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
-	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh)
+	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh), \
+	DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\
+	DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\
+	DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\
+	DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\
+	DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\
+	DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\
+	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\
+	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\
+	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh)
+
 
 
 struct dccg *dccg31_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 52947c03be31..fee385e37c9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -270,6 +270,12 @@ void dcn31_dsc_pg_control(
 	if (hws->ctx->dc->debug.disable_dsc_power_gate)
 		return;
 
+	if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&
+		hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&
+		power_on)
+		hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(
+			hws->ctx->dc->res_pool->dccg, dsc_inst);
+
 	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 	if (org_ip_request_cntl == 0)
 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
@@ -306,6 +312,17 @@ void dcn31_dsc_pg_control(
 
 	if (org_ip_request_cntl == 0)
 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
+
+	if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {
+		if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)
+			hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
+				hws->ctx->dc->res_pool->dccg, dsc_inst);
+
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+		dc_z10_save_init(hws->ctx->dc);
+#endif
+	}
+
 }
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 09237d5819f4..c940fdfda144 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -123,6 +123,15 @@ struct dccg_funcs {
 	void (*set_dispclk_change_mode)(
 			struct dccg *dccg,
 			enum dentist_dispclk_change_mode change_mode);
+
+	void (*disable_dsc)(
+		struct dccg *dccg,
+		int inst);
+
+	void (*enable_dsc)(
+		struct dccg *dccg,
+		int inst);
+
 };
 
 #endif //__DAL_DCCG_H__
-- 
2.25.1


  parent reply	other threads:[~2021-10-15 18:44 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-15 18:43 [PATCH 00/27] DC Patchset for October 15 Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 01/27] drm/amd/display: Disable dpp root clock when not being used Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 02/27] drm/amd/display: Clear encoder assignment for copied streams Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 03/27] drm/amd/display: Do not skip link training on DP quick hot plug Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 04/27] drm/amd/display: add DP2.0 debug option to set MST_EN for SST stream Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 05/27] drm/amd/display: Clean Up VPG Low Mem Power Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 06/27] drm/amd/display: do not compare integers of different widths Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 07/27] drm/amd/display: correct apg audio channel enable golden value Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 08/27] drm/amd/display: Validate plane rects before use Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 09/27] drm/amd/display: Removed power down on boot from DCN31 Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 10/27] drm/amd/display: Limit display scaling to up to true 4k for DCN 3.1 Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 11/27] drm/amd/display: Fix DP2 SE and LE SYMCLK selection for B0 PHY Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 12/27] drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1 Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 13/27] drm/amd/display: Add missing PSR state Agustin Gutierrez
2021-10-15 18:43 ` Agustin Gutierrez [this message]
2021-10-15 18:43 ` [PATCH 15/27] drm/amd/display: Require immediate flip support for DCN3.1 planes Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 16/27] drm/amd/display: increase Z9 latency to workaround underflow in Z9 Agustin Gutierrez
2021-10-15 23:53   ` Mike Lothian
2021-10-18 17:14     ` Kazlauskas, Nicholas
2021-10-18 22:57       ` Paul Menzel
2021-10-15 18:43 ` [PATCH 17/27] drm/amd/display: Increase watermark latencies for DCN3.1 Agustin Gutierrez
2021-10-18 22:56   ` Paul Menzel
2021-10-15 18:43 ` [PATCH 18/27] drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 19/27] drm/amd/display: Removed z10 save after dsc disable Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 20/27] drm/amd/display: Moved dccg init to after bios golden init Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 21/27] drm/amd/display: Disable hdmistream and hdmichar clocks Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 22/27] drm/amd/display: Change initializer to single brace Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 23/27] drm/amd/display: 3.2.157 Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 24/27] drm/amd/display: Add bios parser support for latest firmware_info Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 25/27] drm/amd/display: [FW Promotion] Release 0.0.88 Agustin Gutierrez
2021-10-15 18:43 ` [PATCH 26/27] Revert "drm/amd/display: Fix error in dmesg at boot" Agustin Gutierrez
2021-10-18 23:23   ` Paul Menzel
2021-10-15 18:43 ` [PATCH 27/27] Revert "drm/amd/display: Add helper for blanking all dp displays" Agustin Gutierrez
2021-10-18 23:25   ` Paul Menzel
2021-10-18 17:01 ` [PATCH 00/27] DC Patchset for October 15 Wheeler, Daniel

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