From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Luis Pires" <luis.pires@eldorado.org.br>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH 16/33] target/mips: Convert MSA 2RF instruction format to decodetree
Date: Sat, 23 Oct 2021 23:47:46 +0200 [thread overview]
Message-ID: <20211023214803.522078-17-f4bug@amsat.org> (raw)
In-Reply-To: <20211023214803.522078-1-f4bug@amsat.org>
Convert 2-register floating-point operations to decodetree.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 19 ++++++
target/mips/tcg/msa_translate.c | 109 ++++++++------------------------
2 files changed, 46 insertions(+), 82 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 5fe6923ace5..2997bfa24e3 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -13,6 +13,7 @@
&r rs rt rd sa
+&msa_r df wd ws wt
&msa_bz df wt sa
&msa_ldst df wd ws sa
@@ -20,6 +21,7 @@
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_ldst
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_ldst
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldst ws=0
@@ -74,6 +76,23 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ FCLASS 011110 110010000 . ..... ..... 011110 @2rf
+ FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
+ FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf
+ FSQRT 011110 110010011 . ..... ..... 011110 @2rf
+ FRSQRT 011110 110010100 . ..... ..... 011110 @2rf
+ FRCP 011110 110010101 . ..... ..... 011110 @2rf
+ FRINT 011110 110010110 . ..... ..... 011110 @2rf
+ FLOG2 011110 110010111 . ..... ..... 011110 @2rf
+ FEXUPL 011110 110011000 . ..... ..... 011110 @2rf
+ FEXUPR 011110 110011001 . ..... ..... 011110 @2rf
+ FFQL 011110 110011010 . ..... ..... 011110 @2rf
+ FFQR 011110 110011011 . ..... ..... 011110 @2rf
+ FTINT_S 011110 110011100 . ..... ..... 011110 @2rf
+ FTINT_U 011110 110011101 . ..... ..... 011110 @2rf
+ FFINT_S 011110 110011110 . ..... ..... 011110 @2rf
+ FFINT_U 011110 110011111 . ..... ..... 011110 @2rf
+
LD 011110 .......... ..... ..... 1000 .. @ldst
ST 011110 .......... ..... ..... 1001 .. @ldst
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 52af99636a4..c6a77381c0e 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -41,7 +41,7 @@ enum {
};
enum {
- /* VEC/2R/2RF instruction */
+ /* VEC/2R instruction */
OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC,
OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC,
OPC_NOR_V = (0x02 << 21) | OPC_MSA_VEC,
@@ -51,7 +51,6 @@ enum {
OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC,
OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
- OPC_MSA_2RF = (0x19 << 21) | OPC_MSA_VEC,
/* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
@@ -59,24 +58,6 @@ enum {
OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
- /* 2RF instruction df(bit 16) = _w, _d */
- OPC_FCLASS_df = (0x00 << 17) | OPC_MSA_2RF,
- OPC_FTRUNC_S_df = (0x01 << 17) | OPC_MSA_2RF,
- OPC_FTRUNC_U_df = (0x02 << 17) | OPC_MSA_2RF,
- OPC_FSQRT_df = (0x03 << 17) | OPC_MSA_2RF,
- OPC_FRSQRT_df = (0x04 << 17) | OPC_MSA_2RF,
- OPC_FRCP_df = (0x05 << 17) | OPC_MSA_2RF,
- OPC_FRINT_df = (0x06 << 17) | OPC_MSA_2RF,
- OPC_FLOG2_df = (0x07 << 17) | OPC_MSA_2RF,
- OPC_FEXUPL_df = (0x08 << 17) | OPC_MSA_2RF,
- OPC_FEXUPR_df = (0x09 << 17) | OPC_MSA_2RF,
- OPC_FFQL_df = (0x0A << 17) | OPC_MSA_2RF,
- OPC_FFQR_df = (0x0B << 17) | OPC_MSA_2RF,
- OPC_FTINT_S_df = (0x0C << 17) | OPC_MSA_2RF,
- OPC_FTINT_U_df = (0x0D << 17) | OPC_MSA_2RF,
- OPC_FFINT_S_df = (0x0E << 17) | OPC_MSA_2RF,
- OPC_FFINT_U_df = (0x0F << 17) | OPC_MSA_2RF,
-
/* 3R instruction df(bits 22..21) = _b, _h, _w, d */
OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -1932,73 +1913,40 @@ static void gen_msa_2r(DisasContext *ctx)
tcg_temp_free_i32(tws);
}
-static void gen_msa_2rf(DisasContext *ctx)
+static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
+ void (*gen_msa_2rf)(TCGv_ptr, TCGv_i32,
+ TCGv_i32, TCGv_i32))
{
-#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
- (op & (0xf << 17)))
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- uint8_t df = (ctx->opcode >> 16) & 0x1;
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
+ TCGv_i32 twd = tcg_const_i32(a->wd);
+ TCGv_i32 tws = tcg_const_i32(a->ws);
/* adjust df value for floating-point instruction */
- TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
+ TCGv_i32 tdf = tcg_constant_i32(DF_WORD + a->df);
- switch (MASK_MSA_2RF(ctx->opcode)) {
- case OPC_FCLASS_df:
- gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTRUNC_S_df:
- gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTRUNC_U_df:
- gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FSQRT_df:
- gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FRSQRT_df:
- gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FRCP_df:
- gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FRINT_df:
- gen_helper_msa_frint_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FLOG2_df:
- gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FEXUPL_df:
- gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FEXUPR_df:
- gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFQL_df:
- gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFQR_df:
- gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTINT_S_df:
- gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTINT_U_df:
- gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFINT_S_df:
- gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFINT_U_df:
- gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws);
- break;
- }
+ gen_msa_2rf(cpu_env, tdf, twd, tws);
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
+
+ return true;
}
+TRANS_MSA(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df);
+TRANS_MSA(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df);
+TRANS_MSA(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df);
+TRANS_MSA(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df);
+TRANS_MSA(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df);
+TRANS_MSA(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df);
+TRANS_MSA(FRINT, trans_msa_2rf, gen_helper_msa_frint_df);
+TRANS_MSA(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df);
+TRANS_MSA(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df);
+TRANS_MSA(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df);
+TRANS_MSA(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df);
+TRANS_MSA(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df);
+TRANS_MSA(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df);
+TRANS_MSA(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df);
+TRANS_MSA(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df);
+TRANS_MSA(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df);
+
static void gen_msa_vec_v(DisasContext *ctx)
{
#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
@@ -2057,9 +2005,6 @@ static void gen_msa_vec(DisasContext *ctx)
case OPC_MSA_2R:
gen_msa_2r(ctx);
break;
- case OPC_MSA_2RF:
- gen_msa_2rf(ctx);
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
--
2.31.1
next prev parent reply other threads:[~2021-10-23 22:02 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path Philippe Mathieu-Daudé
2021-10-23 23:24 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 02/33] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 10:38 ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 05/33] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-24 1:02 ` Richard Henderson
2021-10-24 12:48 ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-24 1:03 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-24 1:05 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-24 1:53 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers Philippe Mathieu-Daudé
2021-10-24 1:58 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 10/33] target/mips: Extract df_extract() helper Philippe Mathieu-Daudé
2021-10-24 2:26 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24 2:10 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 12/33] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-24 2:45 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 13/33] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-24 3:40 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 14/33] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-24 3:45 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 15/33] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-24 4:53 ` Richard Henderson
2021-10-24 11:18 ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` Philippe Mathieu-Daudé [this message]
2021-10-24 5:01 ` [PATCH 16/33] target/mips: Convert MSA 2RF " Richard Henderson
2021-10-23 21:47 ` [PATCH 17/33] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-24 5:04 ` Richard Henderson
2021-10-24 16:44 ` Philippe Mathieu-Daudé
2021-10-24 17:26 ` Richard Henderson
2021-10-25 16:43 ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 18/33] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-24 5:14 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 19/33] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-24 5:17 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-24 17:37 ` Richard Henderson
2021-10-24 17:42 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-24 17:42 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-24 17:51 ` Richard Henderson
2021-10-24 17:52 ` Richard Henderson
2021-10-24 18:57 ` Philippe Mathieu-Daudé
2021-10-24 20:27 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-24 17:55 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-24 18:09 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-24 18:12 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24 20:52 ` Richard Henderson
2021-10-27 17:27 ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 27/33] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-24 21:01 ` Richard Henderson
2021-10-27 17:40 ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-24 21:02 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-24 21:09 ` Richard Henderson
2021-10-23 21:48 ` [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes " Philippe Mathieu-Daudé
2021-10-24 21:15 ` Richard Henderson
2021-10-23 21:48 ` [PATCH 31/33] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-24 21:16 ` Richard Henderson
2021-10-23 21:48 ` [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-24 21:17 ` Richard Henderson
2021-10-23 21:48 ` [PATCH 33/33] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-24 21:18 ` Richard Henderson
2021-10-24 18:26 ` [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Jiaxun Yang
2021-10-24 19:01 ` Philippe Mathieu-Daudé
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