From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Luis Pires" <luis.pires@eldorado.org.br>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH 19/33] target/mips: Convert MSA VEC instruction format to decodetree
Date: Sat, 23 Oct 2021 23:47:49 +0200 [thread overview]
Message-ID: <20211023214803.522078-20-f4bug@amsat.org> (raw)
In-Reply-To: <20211023214803.522078-1-f4bug@amsat.org>
Convert 3-register instructions with implicit data formats
to decodetree.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 8 ++++
target/mips/tcg/msa_translate.c | 82 +++++++--------------------------
2 files changed, 24 insertions(+), 66 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 88757f547eb..72447041fef 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -21,6 +21,7 @@
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_ldst
@@ -77,6 +78,13 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ AND_V 011110 00000 ..... ..... ..... 011110 @vec
+ OR_V 011110 00001 ..... ..... ..... 011110 @vec
+ NOR_V 011110 00010 ..... ..... ..... 011110 @vec
+ XOR_V 011110 00011 ..... ..... ..... 011110 @vec
+ BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec
+ BMZ_V 011110 00101 ..... ..... ..... 011110 @vec
+ BSEL_V 011110 00110 ..... ..... ..... 011110 @vec
FILL 011110 11000000 .. ..... ..... 011110 @2r
PCNT 011110 11000001 .. ..... ..... 011110 @2r
NLOC 011110 11000010 .. ..... ..... 011110 @2r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index f54e9d173ac..461a427c9df 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -37,19 +37,9 @@ enum {
OPC_MSA_3RF_1A = 0x1A | OPC_MSA,
OPC_MSA_3RF_1B = 0x1B | OPC_MSA,
OPC_MSA_3RF_1C = 0x1C | OPC_MSA,
- OPC_MSA_VEC = 0x1E | OPC_MSA,
};
enum {
- /* VEC/2R instruction */
- OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC,
- OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC,
- OPC_NOR_V = (0x02 << 21) | OPC_MSA_VEC,
- OPC_XOR_V = (0x03 << 21) | OPC_MSA_VEC,
- OPC_BMNZ_V = (0x04 << 21) | OPC_MSA_VEC,
- OPC_BMZ_V = (0x05 << 21) | OPC_MSA_VEC,
- OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC,
-
/* 3R instruction df(bits 22..21) = _b, _h, _w, d */
OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -1925,67 +1915,30 @@ TRANS_MSA(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df);
TRANS_MSA(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df);
TRANS_MSA(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df);
-static void gen_msa_vec_v(DisasContext *ctx)
+static bool trans_msa_vec(DisasContext *ctx, arg_msa_r *a,
+ void (*gen_msa_vec)(TCGv_ptr, TCGv_i32,
+ TCGv_i32, TCGv_i32))
{
-#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
+ TCGv_i32 twd = tcg_const_i32(a->wd);
+ TCGv_i32 tws = tcg_const_i32(a->ws);
+ TCGv_i32 twt = tcg_const_i32(a->wt);
- switch (MASK_MSA_VEC(ctx->opcode)) {
- case OPC_AND_V:
- gen_helper_msa_and_v(cpu_env, twd, tws, twt);
- break;
- case OPC_OR_V:
- gen_helper_msa_or_v(cpu_env, twd, tws, twt);
- break;
- case OPC_NOR_V:
- gen_helper_msa_nor_v(cpu_env, twd, tws, twt);
- break;
- case OPC_XOR_V:
- gen_helper_msa_xor_v(cpu_env, twd, tws, twt);
- break;
- case OPC_BMNZ_V:
- gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt);
- break;
- case OPC_BMZ_V:
- gen_helper_msa_bmz_v(cpu_env, twd, tws, twt);
- break;
- case OPC_BSEL_V:
- gen_helper_msa_bsel_v(cpu_env, twd, tws, twt);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
+ gen_msa_vec(cpu_env, twd, tws, twt);
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
tcg_temp_free_i32(twt);
+
+ return true;
}
-static void gen_msa_vec(DisasContext *ctx)
-{
- switch (MASK_MSA_VEC(ctx->opcode)) {
- case OPC_AND_V:
- case OPC_OR_V:
- case OPC_NOR_V:
- case OPC_XOR_V:
- case OPC_BMNZ_V:
- case OPC_BMZ_V:
- case OPC_BSEL_V:
- gen_msa_vec_v(ctx);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-}
+TRANS_MSA(AND_V, trans_msa_vec, gen_helper_msa_and_v);
+TRANS_MSA(OR_V, trans_msa_vec, gen_helper_msa_or_v);
+TRANS_MSA(NOR_V, trans_msa_vec, gen_helper_msa_nor_v);
+TRANS_MSA(XOR_V, trans_msa_vec, gen_helper_msa_xor_v);
+TRANS_MSA(BMNZ_V, trans_msa_vec, gen_helper_msa_bmnz_v);
+TRANS_MSA(BMZ_V, trans_msa_vec, gen_helper_msa_bmz_v);
+TRANS_MSA(BSEL_V, trans_msa_vec, gen_helper_msa_bsel_v);
static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
{
@@ -2015,9 +1968,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
case OPC_MSA_3RF_1C:
gen_msa_3rf(ctx);
break;
- case OPC_MSA_VEC:
- gen_msa_vec(ctx);
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
--
2.31.1
next prev parent reply other threads:[~2021-10-23 21:54 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path Philippe Mathieu-Daudé
2021-10-23 23:24 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 02/33] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 10:38 ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 05/33] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-24 1:02 ` Richard Henderson
2021-10-24 12:48 ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-24 1:03 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-24 1:05 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-24 1:53 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers Philippe Mathieu-Daudé
2021-10-24 1:58 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 10/33] target/mips: Extract df_extract() helper Philippe Mathieu-Daudé
2021-10-24 2:26 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24 2:10 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 12/33] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-24 2:45 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 13/33] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-24 3:40 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 14/33] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-24 3:45 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 15/33] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-24 4:53 ` Richard Henderson
2021-10-24 11:18 ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 16/33] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-24 5:01 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 17/33] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-24 5:04 ` Richard Henderson
2021-10-24 16:44 ` Philippe Mathieu-Daudé
2021-10-24 17:26 ` Richard Henderson
2021-10-25 16:43 ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 18/33] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-24 5:14 ` Richard Henderson
2021-10-23 21:47 ` Philippe Mathieu-Daudé [this message]
2021-10-24 5:17 ` [PATCH 19/33] target/mips: Convert MSA VEC " Richard Henderson
2021-10-23 21:47 ` [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-24 17:37 ` Richard Henderson
2021-10-24 17:42 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-24 17:42 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-24 17:51 ` Richard Henderson
2021-10-24 17:52 ` Richard Henderson
2021-10-24 18:57 ` Philippe Mathieu-Daudé
2021-10-24 20:27 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-24 17:55 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-24 18:09 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-24 18:12 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24 20:52 ` Richard Henderson
2021-10-27 17:27 ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 27/33] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-24 21:01 ` Richard Henderson
2021-10-27 17:40 ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-24 21:02 ` Richard Henderson
2021-10-23 21:47 ` [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-24 21:09 ` Richard Henderson
2021-10-23 21:48 ` [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes " Philippe Mathieu-Daudé
2021-10-24 21:15 ` Richard Henderson
2021-10-23 21:48 ` [PATCH 31/33] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-24 21:16 ` Richard Henderson
2021-10-23 21:48 ` [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-24 21:17 ` Richard Henderson
2021-10-23 21:48 ` [PATCH 33/33] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-24 21:18 ` Richard Henderson
2021-10-24 18:26 ` [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Jiaxun Yang
2021-10-24 19:01 ` Philippe Mathieu-Daudé
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