[PATCH 00/13] Support UXL filed in xstatus.

[LIU Zhiwei <zhiwei_liu@c-sky.com>]

In this patch set, we process the pc reigsters writes,
gdb reads and writes, and address calculation under
different UXLEN settings.

LIU Zhiwei (13):
  target/riscv: Sign extend pc for different ol
  target/riscv: Extend pc for runtime pc write
  target/riscv: Ignore the pc bits above XLEN
  target/riscv: Use gdb xml according to max mxlen
  target/riscv: Calculate address according to ol
  target/riscv: Adjust vsetvl according to ol
  target/riscv: Ajdust vector atomic check with ol
  target/riscv: Fix check range for first fault only
  target/riscv: Adjust vector address with ol
  target/riscv: Adjust scalar reg in vector with ol
  target/riscv: Switch context in exception return
  target/riscv: Don't save pc when exception return
  target/riscv: Enable uxl field write

 target/riscv/cpu.c                            | 20 ++++-
 target/riscv/cpu.h                            |  4 +
 target/riscv/cpu_helper.c                     |  4 +-
 target/riscv/csr.c                            |  6 +-
 target/riscv/gdbstub.c                        | 73 ++++++++++++-----
 target/riscv/helper.h                         |  7 +-
 target/riscv/insn_trans/trans_privileged.c.inc|  9 +--
 target/riscv/insn_trans/trans_rvd.c.inc       | 20 ++---
 target/riscv/insn_trans/trans_rvf.c.inc       | 21 ++---
 target/riscv/insn_trans/trans_rvi.c.inc       | 23 +++---
 target/riscv/insn_trans/trans_rvv.c.inc       | 19 +++--
 target/riscv/internals.h                      |  1 +
 target/riscv/op_helper.c                      | 30 ++++++-
 target/riscv/translate.c                      | 23 +++++-
 target/riscv/vector_helper.c                  | 81 +++++++++++++------
 15 files changed, 233 insertions(+), 108 deletions(-)

-- 
2.25.1