From: kernel test robot <lkp@intel.com>
To: Qin Jian <qinjian@cqplus1.com>, robh+dt@kernel.org
Cc: kbuild-all@lists.01.org, mturquette@baylibre.com,
sboyd@kernel.org, maz@kernel.org, p.zabel@pengutronix.de,
linux@armlinux.org.uk, broonie@kernel.org, arnd@arndb.de,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v4 06/10] clk: Add Sunplus SP7021 clock driver
Date: Fri, 5 Nov 2021 12:02:57 +0800 [thread overview]
Message-ID: <202111051242.IdXNWfVt-lkp@intel.com> (raw)
In-Reply-To: <2373006c300bfde8b0a1470f81d252d3766ae1c3.1635993377.git.qinjian@cqplus1.com>
[-- Attachment #1: Type: text/plain, Size: 5350 bytes --]
Hi Qin,
I love your patch! Yet something to improve:
[auto build test ERROR on pza/reset/next]
[also build test ERROR on robh/for-next clk/clk-next tip/irq/core linus/master v5.15 next-20211104]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211104-115746
base: https://git.pengutronix.de/git/pza/linux reset/next
config: arc-allyesconfig (attached as .config)
compiler: arceb-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/604141a9aad536dff720a6337561171d72d63d74
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211104-115746
git checkout 604141a9aad536dff720a6337561171d72d63d74
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=arc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/clk/clk-sp7021.c: In function 'plltv_fractional_div':
>> drivers/clk/clk-sp7021.c:292:13: error: variable 'diff_min_sign' set but not used [-Werror=unused-but-set-variable]
292 | u32 diff_min_sign = 0;
| ^~~~~~~~~~~~~
drivers/clk/clk-sp7021.c: At top level:
drivers/clk/clk-sp7021.c:625:13: error: no previous prototype for 'clk_register_sp_pll' [-Werror=missing-prototypes]
625 | struct clk *clk_register_sp_pll(const char *name, const char *parent,
| ^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +/diff_min_sign +292 drivers/clk/clk-sp7021.c
286
287 static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq)
288 {
289 u32 m, r;
290 u32 nint, nfra;
291 u32 diff_min_quotient = 210000000, diff_min_remainder = 0;
> 292 u32 diff_min_sign = 0;
293 unsigned long fvco, nf, f, fout = 0;
294 int sdm, ph;
295
296 /* check freq */
297 if (freq < F_MIN) {
298 pr_warn("%s: %s freq:%lu < F_MIN:%lu, round up\n",
299 __func__, clk_hw_get_name(&clk->hw), freq, F_MIN);
300 freq = F_MIN;
301 } else if (freq > F_MAX) {
302 pr_warn("%s: %s freq:%lu > F_MAX:%lu, round down\n",
303 __func__, clk_hw_get_name(&clk->hw), freq, F_MAX);
304 freq = F_MAX;
305 }
306
307 /* DIVR 0~3 */
308 for (r = 0; r <= 3; r++) {
309 fvco = freq << r;
310 if (fvco <= FVCO_MAX)
311 break;
312 }
313 f = F_27M >> r;
314
315 /* PH_SEL 1/0 */
316 for (ph = 1; ph >= 0; ph--) {
317 const u32 *pp = pt[ph];
318 u32 ms = 1;
319
320 /* SDM_MOD 0/1 */
321 for (sdm = 0; sdm <= 1; sdm++) {
322 u32 mod = mods[sdm];
323
324 /* DIVM 1~32 */
325 for (m = ms; m <= 32; m++) {
326 u32 diff_freq;
327 u32 diff_freq_quotient = 0, diff_freq_remainder = 0;
328 u32 diff_freq_sign = 0; /* 0:Positive number, 1:Negative number */
329
330 nf = fvco * m;
331 nint = nf / pp[3];
332
333 if (nint < pp[1])
334 continue;
335 if (nint > pp[1])
336 break;
337
338 nfra = (((nf % pp[3]) * mod * pp[4]) + (F_27M / 2)) / F_27M;
339 if (nfra)
340 diff_freq = (f * (nint + pp[2]) / pp[0]) -
341 (f * (mod - nfra) / mod / pp[4]);
342 else
343 diff_freq = (f * (nint) / pp[0]);
344
345 diff_freq_quotient = diff_freq / m;
346 diff_freq_remainder = ((diff_freq % m) * 1000) / m;
347
348 if (freq > diff_freq_quotient) {
349 diff_freq_quotient = freq - diff_freq_quotient - 1;
350 diff_freq_remainder = 1000 - diff_freq_remainder;
351 diff_freq_sign = 1;
352 } else {
353 diff_freq_quotient = diff_freq_quotient - freq;
354 diff_freq_sign = 0;
355 }
356
357 if ((diff_min_quotient > diff_freq_quotient) ||
358 ((diff_min_quotient == diff_freq_quotient) &&
359 (diff_min_remainder > diff_freq_remainder))) {
360
361 /* found a closer freq, save parameters */
362 clk->p[SEL_FRA] = 1;
363 clk->p[SDM_MOD] = sdm;
364 clk->p[PH_SEL] = ph;
365 clk->p[NFRA] = nfra;
366 clk->p[DIVR] = r;
367 clk->p[DIVM] = m;
368
369 fout = diff_freq / m;
370 diff_min_quotient = diff_freq_quotient;
371 diff_min_remainder = diff_freq_remainder;
372 diff_min_sign = diff_freq_sign;
373 }
374 }
375 }
376 }
377
378 if (!fout) {
379 pr_err("%s: %s freq:%lu not found a valid setting\n",
380 __func__, clk_hw_get_name(&clk->hw), freq);
381 return -EINVAL;
382 }
383
384 return fout;
385 }
386
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 69191 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: kernel test robot <lkp@intel.com>
To: Qin Jian <qinjian@cqplus1.com>, robh+dt@kernel.org
Cc: kbuild-all@lists.01.org, mturquette@baylibre.com,
sboyd@kernel.org, maz@kernel.org, p.zabel@pengutronix.de,
linux@armlinux.org.uk, broonie@kernel.org, arnd@arndb.de,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v4 06/10] clk: Add Sunplus SP7021 clock driver
Date: Fri, 5 Nov 2021 12:02:57 +0800 [thread overview]
Message-ID: <202111051242.IdXNWfVt-lkp@intel.com> (raw)
In-Reply-To: <2373006c300bfde8b0a1470f81d252d3766ae1c3.1635993377.git.qinjian@cqplus1.com>
[-- Attachment #1: Type: text/plain, Size: 5350 bytes --]
Hi Qin,
I love your patch! Yet something to improve:
[auto build test ERROR on pza/reset/next]
[also build test ERROR on robh/for-next clk/clk-next tip/irq/core linus/master v5.15 next-20211104]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211104-115746
base: https://git.pengutronix.de/git/pza/linux reset/next
config: arc-allyesconfig (attached as .config)
compiler: arceb-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/604141a9aad536dff720a6337561171d72d63d74
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211104-115746
git checkout 604141a9aad536dff720a6337561171d72d63d74
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=arc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/clk/clk-sp7021.c: In function 'plltv_fractional_div':
>> drivers/clk/clk-sp7021.c:292:13: error: variable 'diff_min_sign' set but not used [-Werror=unused-but-set-variable]
292 | u32 diff_min_sign = 0;
| ^~~~~~~~~~~~~
drivers/clk/clk-sp7021.c: At top level:
drivers/clk/clk-sp7021.c:625:13: error: no previous prototype for 'clk_register_sp_pll' [-Werror=missing-prototypes]
625 | struct clk *clk_register_sp_pll(const char *name, const char *parent,
| ^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +/diff_min_sign +292 drivers/clk/clk-sp7021.c
286
287 static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq)
288 {
289 u32 m, r;
290 u32 nint, nfra;
291 u32 diff_min_quotient = 210000000, diff_min_remainder = 0;
> 292 u32 diff_min_sign = 0;
293 unsigned long fvco, nf, f, fout = 0;
294 int sdm, ph;
295
296 /* check freq */
297 if (freq < F_MIN) {
298 pr_warn("%s: %s freq:%lu < F_MIN:%lu, round up\n",
299 __func__, clk_hw_get_name(&clk->hw), freq, F_MIN);
300 freq = F_MIN;
301 } else if (freq > F_MAX) {
302 pr_warn("%s: %s freq:%lu > F_MAX:%lu, round down\n",
303 __func__, clk_hw_get_name(&clk->hw), freq, F_MAX);
304 freq = F_MAX;
305 }
306
307 /* DIVR 0~3 */
308 for (r = 0; r <= 3; r++) {
309 fvco = freq << r;
310 if (fvco <= FVCO_MAX)
311 break;
312 }
313 f = F_27M >> r;
314
315 /* PH_SEL 1/0 */
316 for (ph = 1; ph >= 0; ph--) {
317 const u32 *pp = pt[ph];
318 u32 ms = 1;
319
320 /* SDM_MOD 0/1 */
321 for (sdm = 0; sdm <= 1; sdm++) {
322 u32 mod = mods[sdm];
323
324 /* DIVM 1~32 */
325 for (m = ms; m <= 32; m++) {
326 u32 diff_freq;
327 u32 diff_freq_quotient = 0, diff_freq_remainder = 0;
328 u32 diff_freq_sign = 0; /* 0:Positive number, 1:Negative number */
329
330 nf = fvco * m;
331 nint = nf / pp[3];
332
333 if (nint < pp[1])
334 continue;
335 if (nint > pp[1])
336 break;
337
338 nfra = (((nf % pp[3]) * mod * pp[4]) + (F_27M / 2)) / F_27M;
339 if (nfra)
340 diff_freq = (f * (nint + pp[2]) / pp[0]) -
341 (f * (mod - nfra) / mod / pp[4]);
342 else
343 diff_freq = (f * (nint) / pp[0]);
344
345 diff_freq_quotient = diff_freq / m;
346 diff_freq_remainder = ((diff_freq % m) * 1000) / m;
347
348 if (freq > diff_freq_quotient) {
349 diff_freq_quotient = freq - diff_freq_quotient - 1;
350 diff_freq_remainder = 1000 - diff_freq_remainder;
351 diff_freq_sign = 1;
352 } else {
353 diff_freq_quotient = diff_freq_quotient - freq;
354 diff_freq_sign = 0;
355 }
356
357 if ((diff_min_quotient > diff_freq_quotient) ||
358 ((diff_min_quotient == diff_freq_quotient) &&
359 (diff_min_remainder > diff_freq_remainder))) {
360
361 /* found a closer freq, save parameters */
362 clk->p[SEL_FRA] = 1;
363 clk->p[SDM_MOD] = sdm;
364 clk->p[PH_SEL] = ph;
365 clk->p[NFRA] = nfra;
366 clk->p[DIVR] = r;
367 clk->p[DIVM] = m;
368
369 fout = diff_freq / m;
370 diff_min_quotient = diff_freq_quotient;
371 diff_min_remainder = diff_freq_remainder;
372 diff_min_sign = diff_freq_sign;
373 }
374 }
375 }
376 }
377
378 if (!fout) {
379 pr_err("%s: %s freq:%lu not found a valid setting\n",
380 __func__, clk_hw_get_name(&clk->hw), freq);
381 return -EINVAL;
382 }
383
384 return fout;
385 }
386
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 69191 bytes --]
[-- Attachment #3: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH v4 06/10] clk: Add Sunplus SP7021 clock driver
Date: Fri, 05 Nov 2021 12:02:57 +0800 [thread overview]
Message-ID: <202111051242.IdXNWfVt-lkp@intel.com> (raw)
In-Reply-To: <2373006c300bfde8b0a1470f81d252d3766ae1c3.1635993377.git.qinjian@cqplus1.com>
[-- Attachment #1: Type: text/plain, Size: 5499 bytes --]
Hi Qin,
I love your patch! Yet something to improve:
[auto build test ERROR on pza/reset/next]
[also build test ERROR on robh/for-next clk/clk-next tip/irq/core linus/master v5.15 next-20211104]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211104-115746
base: https://git.pengutronix.de/git/pza/linux reset/next
config: arc-allyesconfig (attached as .config)
compiler: arceb-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/604141a9aad536dff720a6337561171d72d63d74
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qin-Jian/dt-bindings-vendor-prefixes-Add-Sunplus/20211104-115746
git checkout 604141a9aad536dff720a6337561171d72d63d74
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=arc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/clk/clk-sp7021.c: In function 'plltv_fractional_div':
>> drivers/clk/clk-sp7021.c:292:13: error: variable 'diff_min_sign' set but not used [-Werror=unused-but-set-variable]
292 | u32 diff_min_sign = 0;
| ^~~~~~~~~~~~~
drivers/clk/clk-sp7021.c: At top level:
drivers/clk/clk-sp7021.c:625:13: error: no previous prototype for 'clk_register_sp_pll' [-Werror=missing-prototypes]
625 | struct clk *clk_register_sp_pll(const char *name, const char *parent,
| ^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +/diff_min_sign +292 drivers/clk/clk-sp7021.c
286
287 static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq)
288 {
289 u32 m, r;
290 u32 nint, nfra;
291 u32 diff_min_quotient = 210000000, diff_min_remainder = 0;
> 292 u32 diff_min_sign = 0;
293 unsigned long fvco, nf, f, fout = 0;
294 int sdm, ph;
295
296 /* check freq */
297 if (freq < F_MIN) {
298 pr_warn("%s: %s freq:%lu < F_MIN:%lu, round up\n",
299 __func__, clk_hw_get_name(&clk->hw), freq, F_MIN);
300 freq = F_MIN;
301 } else if (freq > F_MAX) {
302 pr_warn("%s: %s freq:%lu > F_MAX:%lu, round down\n",
303 __func__, clk_hw_get_name(&clk->hw), freq, F_MAX);
304 freq = F_MAX;
305 }
306
307 /* DIVR 0~3 */
308 for (r = 0; r <= 3; r++) {
309 fvco = freq << r;
310 if (fvco <= FVCO_MAX)
311 break;
312 }
313 f = F_27M >> r;
314
315 /* PH_SEL 1/0 */
316 for (ph = 1; ph >= 0; ph--) {
317 const u32 *pp = pt[ph];
318 u32 ms = 1;
319
320 /* SDM_MOD 0/1 */
321 for (sdm = 0; sdm <= 1; sdm++) {
322 u32 mod = mods[sdm];
323
324 /* DIVM 1~32 */
325 for (m = ms; m <= 32; m++) {
326 u32 diff_freq;
327 u32 diff_freq_quotient = 0, diff_freq_remainder = 0;
328 u32 diff_freq_sign = 0; /* 0:Positive number, 1:Negative number */
329
330 nf = fvco * m;
331 nint = nf / pp[3];
332
333 if (nint < pp[1])
334 continue;
335 if (nint > pp[1])
336 break;
337
338 nfra = (((nf % pp[3]) * mod * pp[4]) + (F_27M / 2)) / F_27M;
339 if (nfra)
340 diff_freq = (f * (nint + pp[2]) / pp[0]) -
341 (f * (mod - nfra) / mod / pp[4]);
342 else
343 diff_freq = (f * (nint) / pp[0]);
344
345 diff_freq_quotient = diff_freq / m;
346 diff_freq_remainder = ((diff_freq % m) * 1000) / m;
347
348 if (freq > diff_freq_quotient) {
349 diff_freq_quotient = freq - diff_freq_quotient - 1;
350 diff_freq_remainder = 1000 - diff_freq_remainder;
351 diff_freq_sign = 1;
352 } else {
353 diff_freq_quotient = diff_freq_quotient - freq;
354 diff_freq_sign = 0;
355 }
356
357 if ((diff_min_quotient > diff_freq_quotient) ||
358 ((diff_min_quotient == diff_freq_quotient) &&
359 (diff_min_remainder > diff_freq_remainder))) {
360
361 /* found a closer freq, save parameters */
362 clk->p[SEL_FRA] = 1;
363 clk->p[SDM_MOD] = sdm;
364 clk->p[PH_SEL] = ph;
365 clk->p[NFRA] = nfra;
366 clk->p[DIVR] = r;
367 clk->p[DIVM] = m;
368
369 fout = diff_freq / m;
370 diff_min_quotient = diff_freq_quotient;
371 diff_min_remainder = diff_freq_remainder;
372 diff_min_sign = diff_freq_sign;
373 }
374 }
375 }
376 }
377
378 if (!fout) {
379 pr_err("%s: %s freq:%lu not found a valid setting\n",
380 __func__, clk_hw_get_name(&clk->hw), freq);
381 return -EINVAL;
382 }
383
384 return fout;
385 }
386
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 69191 bytes --]
next prev parent reply other threads:[~2021-11-05 4:03 UTC|newest]
Thread overview: 124+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-29 8:44 [PATCH v2 0/8] Add Sunplus SP7021 SoC Support Qin Jian
2021-10-29 8:44 ` Qin Jian
2021-10-29 8:44 ` [PATCH v2 1/8] dt-bindings: vendor-prefixes: Add Sunplus Qin Jian
2021-10-29 8:44 ` Qin Jian
2021-10-29 8:44 ` [PATCH v2 2/8] dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards Qin Jian
2021-10-29 8:44 ` Qin Jian
2021-10-29 8:44 ` [PATCH v2 3/8] dt-bindings: reset: Add bindings for SP7021 reset driver Qin Jian
2021-10-29 8:44 ` Qin Jian
2021-10-29 8:44 ` [PATCH v2 4/8] reset: Add Sunplus " Qin Jian
2021-10-29 8:44 ` Qin Jian
2021-10-30 4:18 ` kernel test robot
2021-10-30 4:18 ` kernel test robot
2021-10-30 4:18 ` kernel test robot
2021-10-29 8:44 ` [PATCH v2 5/8] dt-bindings: clock: Add bindings for SP7021 clock driver Qin Jian
2021-10-29 8:44 ` Qin Jian
2021-10-29 8:44 ` [PATCH v2 6/8] clk: Add Sunplus " Qin Jian
2021-10-29 8:44 ` Qin Jian
2021-10-29 8:44 ` [PATCH v2 7/8] dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller Qin Jian
2021-10-29 8:44 ` Qin Jian
2021-10-29 8:44 ` [PATCH v2 8/8] irqchip: Add support for Sunplus " Qin Jian
2021-10-29 8:44 ` Qin Jian
2021-10-29 15:25 ` Marc Zyngier
2021-10-29 15:25 ` Marc Zyngier
2021-11-01 5:01 ` [PATCH v3 0/8] Add Sunplus SP7021 SoC Support Qin Jian
2021-11-01 5:01 ` Qin Jian
2021-11-01 5:01 ` [PATCH v3 1/8] dt-bindings: vendor-prefixes: Add Sunplus Qin Jian
2021-11-01 5:01 ` Qin Jian
2021-11-02 17:44 ` Rob Herring
2021-11-02 17:44 ` Rob Herring
2021-11-01 5:01 ` [PATCH v3 2/8] dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards Qin Jian
2021-11-01 5:01 ` Qin Jian
2021-11-01 19:58 ` Rob Herring
2021-11-01 19:58 ` Rob Herring
2021-11-01 5:01 ` [PATCH v3 3/8] dt-bindings: reset: Add bindings for SP7021 reset driver Qin Jian
2021-11-01 5:01 ` Qin Jian
2021-11-02 11:51 ` Philipp Zabel
2021-11-02 11:51 ` Philipp Zabel
2021-11-03 1:20 ` 答复: " qinjian[覃健]
2021-11-03 1:20 ` qinjian[覃健]
2021-11-01 5:01 ` [PATCH v3 4/8] reset: Add Sunplus " Qin Jian
2021-11-01 5:01 ` Qin Jian
2021-11-02 12:22 ` Philipp Zabel
2021-11-02 12:22 ` Philipp Zabel
2021-11-03 2:42 ` 答复: " qinjian[覃健]
2021-11-03 2:42 ` qinjian[覃健]
2021-11-01 5:01 ` [PATCH v3 5/8] dt-bindings: clock: Add bindings for SP7021 clock driver Qin Jian
2021-11-01 5:01 ` Qin Jian
2021-11-01 19:59 ` Rob Herring
2021-11-01 19:59 ` Rob Herring
2021-11-01 5:01 ` [PATCH v3 6/8] clk: Add Sunplus " Qin Jian
2021-11-01 5:01 ` Qin Jian
2021-11-01 10:16 ` kernel test robot
2021-11-01 10:16 ` kernel test robot
2021-11-01 10:16 ` kernel test robot
2021-11-01 5:01 ` [PATCH v3 7/8] dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller Qin Jian
2021-11-01 5:01 ` Qin Jian
2021-11-02 17:45 ` Rob Herring
2021-11-02 17:45 ` Rob Herring
2021-11-01 5:01 ` [PATCH v3 8/8] irqchip: Add Sunplus SP7021 interrupt controller driver Qin Jian
2021-11-01 5:01 ` Qin Jian
2021-11-01 8:27 ` kernel test robot
2021-11-01 8:27 ` kernel test robot
2021-11-01 8:27 ` kernel test robot
2021-11-01 10:26 ` kernel test robot
2021-11-01 10:26 ` kernel test robot
2021-11-01 10:26 ` kernel test robot
2021-10-30 15:30 ` [PATCH v2 8/8] irqchip: Add support for Sunplus SP7021 interrupt controller kernel test robot
2021-10-30 15:30 ` kernel test robot
2021-10-30 15:30 ` kernel test robot
2021-10-30 19:29 ` kernel test robot
2021-10-30 19:29 ` kernel test robot
2021-11-04 2:56 ` [PATCH v4 00/10] Add Sunplus SP7021 SoC Support Qin Jian
2021-11-04 2:56 ` Qin Jian
2021-11-04 2:56 ` [PATCH v4 01/10] dt-bindings: vendor-prefixes: Add Sunplus Qin Jian
2021-11-04 2:56 ` Qin Jian
2021-11-08 17:45 ` Rob Herring
2021-11-08 17:45 ` Rob Herring
2021-11-04 2:56 ` [PATCH v4 02/10] dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards Qin Jian
2021-11-04 2:56 ` Qin Jian
2021-11-08 17:46 ` Rob Herring
2021-11-08 17:46 ` Rob Herring
2021-11-04 2:57 ` [PATCH v4 03/10] dt-bindings: reset: Add bindings for SP7021 reset driver Qin Jian
2021-11-04 2:57 ` Qin Jian
2021-11-12 21:56 ` Rob Herring
2021-11-12 21:56 ` Rob Herring
2021-11-04 2:57 ` [PATCH v4 04/10] reset: Add Sunplus " Qin Jian
2021-11-04 2:57 ` Qin Jian
2021-11-04 2:57 ` [PATCH v4 05/10] dt-bindings: clock: Add bindings for SP7021 clock driver Qin Jian
2021-11-04 2:57 ` Qin Jian
2021-11-08 17:46 ` Rob Herring
2021-11-08 17:46 ` Rob Herring
2021-11-04 2:57 ` [PATCH v4 06/10] clk: Add Sunplus " Qin Jian
2021-11-04 2:57 ` Qin Jian
2021-11-04 5:09 ` Randy Dunlap
2021-11-04 5:09 ` Randy Dunlap
2021-11-04 11:32 ` kernel test robot
2021-11-04 11:32 ` kernel test robot
2021-11-04 11:32 ` kernel test robot
2021-11-05 4:02 ` kernel test robot [this message]
2021-11-05 4:02 ` kernel test robot
2021-11-05 4:02 ` kernel test robot
2021-11-04 2:57 ` [PATCH v4 07/10] dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller Qin Jian
2021-11-04 2:57 ` Qin Jian
2021-11-08 17:46 ` Rob Herring
2021-11-08 17:46 ` Rob Herring
2021-11-04 2:57 ` [PATCH v4 08/10] irqchip: Add Sunplus SP7021 interrupt controller driver Qin Jian
2021-11-04 2:57 ` Qin Jian
2021-11-04 5:09 ` Randy Dunlap
2021-11-04 5:09 ` Randy Dunlap
2021-11-04 2:57 ` [PATCH v4 09/10] ARM: sunplus: Add initial support for Sunplus SP7021 SoC Qin Jian
2021-11-04 2:57 ` Qin Jian
2021-11-04 5:09 ` Randy Dunlap
2021-11-04 5:09 ` Randy Dunlap
2021-11-04 5:09 ` Randy Dunlap
2021-11-04 5:09 ` Randy Dunlap
2021-11-04 15:23 ` kernel test robot
2021-11-04 15:23 ` kernel test robot
2021-11-04 15:23 ` kernel test robot
2021-11-04 2:57 ` [PATCH v4 10/10] ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig Qin Jian
2021-11-04 2:57 ` Qin Jian
2021-11-04 8:22 ` [PATCH v4 00/10] Add Sunplus SP7021 SoC Support Marc Zyngier
2021-11-04 8:22 ` Marc Zyngier
2021-11-04 8:35 ` 答复: " qinjian[覃健]
2021-11-04 8:35 ` qinjian[覃健]
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