* [PATCH v1] drm/amd/pm: add GFXCLK/SCLK clocks level print support for APUs
@ 2021-11-11 9:34 Perry Yuan
2021-11-12 15:33 ` Alex Deucher
0 siblings, 1 reply; 2+ messages in thread
From: Perry Yuan @ 2021-11-11 9:34 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Ray.Huang
Cc: Xinmei.Huang, Perry Yuan, Mario.Limonciello
add support that allow the userspace tool like RGP to get the GFX clock
value at runtime, the fix follow the old way to show the min/current/max
clocks level for compatible consideration.
=== Test ===
$ cat /sys/class/drm/card0/device/pp_dpm_sclk
0: 200Mhz *
1: 1100Mhz
2: 1600Mhz
then run stress test on one APU system.
$ cat /sys/class/drm/card0/device/pp_dpm_sclk
0: 200Mhz
1: 1040Mhz *
2: 1600Mhz
The current GFXCLK value is updated at runtime.
BugLink: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5260
Reviewed-by: Huang Ray <Ray.Huang@amd.com>
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
---
.../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 22 +++++++++++++--
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 26 ++++++++++++++++++
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 27 +++++++++++++++++++
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h | 1 +
4 files changed, 74 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index 3d4c65bc29dc..6e8343907c32 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -308,6 +308,7 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
{
int ret = 0, size = 0;
uint32_t cur_value = 0;
+ int i;
smu_cmn_get_sysfs_buf(&buf, &size);
@@ -333,8 +334,6 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
size += sysfs_emit_at(buf, size, "VDDC: %7umV %10umV\n",
CYAN_SKILLFISH_VDDC_MIN, CYAN_SKILLFISH_VDDC_MAX);
break;
- case SMU_GFXCLK:
- case SMU_SCLK:
case SMU_FCLK:
case SMU_MCLK:
case SMU_SOCCLK:
@@ -345,6 +344,25 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
return ret;
size += sysfs_emit_at(buf, size, "0: %uMhz *\n", cur_value);
break;
+ case SMU_SCLK:
+ case SMU_GFXCLK:
+ ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value);
+ if (ret)
+ return ret;
+ if (cur_value == CYAN_SKILLFISH_SCLK_MAX)
+ i = 2;
+ else if (cur_value == CYAN_SKILLFISH_SCLK_MIN)
+ i = 0;
+ else
+ i = 1;
+ size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", CYAN_SKILLFISH_SCLK_MIN,
+ i == 0 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
+ i == 1 ? cur_value : CYAN_SKILLFISH_SCLK_DEFAULT,
+ i == 1 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", CYAN_SKILLFISH_SCLK_MAX,
+ i == 2 ? "*" : "");
+ break;
default:
dev_warn(smu->adev->dev, "Unsupported clock type\n");
return ret;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index f6ef0ce6e9e2..6852e4b45589 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -683,6 +683,7 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
bool cur_value_match_level = false;
+ uint32_t min, max;
memset(&metrics, 0, sizeof(metrics));
@@ -743,6 +744,13 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
if (ret)
return ret;
break;
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
+ if (ret) {
+ return ret;
+ }
+ break;
default:
break;
}
@@ -768,6 +776,24 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
if (!cur_value_match_level)
size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
break;
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
+ max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
+ if (cur_value == max)
+ i = 2;
+ else if (cur_value == min)
+ i = 0;
+ else
+ i = 1;
+ size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
+ i == 0 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
+ i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
+ i == 1 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
+ i == 2 ? "*" : "");
+ break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index a403657151ba..cb5326d98f3e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -781,6 +781,11 @@ static int yellow_carp_get_current_clk_freq(struct smu_context *smu,
case SMU_FCLK:
return smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GetFclkFrequency, 0, value);
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ return smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_GetGfxclkFrequency, 0, value);
+ break;
default:
return -EINVAL;
}
@@ -1051,6 +1056,7 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu,
{
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
+ uint32_t min, max;
smu_cmn_get_sysfs_buf(&buf, &size);
@@ -1089,6 +1095,27 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu,
cur_value == value ? "*" : "");
}
break;
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
+ if (ret)
+ goto print_clk_out;
+ min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
+ max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
+ if (cur_value == max)
+ i = 2;
+ else if (cur_value == min)
+ i = 0;
+ else
+ i = 1;
+ size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
+ i == 0 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
+ i == 1 ? cur_value : YELLOW_CARP_UMD_PSTATE_GFXCLK,
+ i == 1 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
+ i == 2 ? "*" : "");
+ break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
index b3ad8352c68a..a9205a8ea3ad 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
@@ -24,5 +24,6 @@
#define __YELLOW_CARP_PPT_H__
extern void yellow_carp_set_ppt_funcs(struct smu_context *smu);
+#define YELLOW_CARP_UMD_PSTATE_GFXCLK 1100
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v1] drm/amd/pm: add GFXCLK/SCLK clocks level print support for APUs
2021-11-11 9:34 [PATCH v1] drm/amd/pm: add GFXCLK/SCLK clocks level print support for APUs Perry Yuan
@ 2021-11-12 15:33 ` Alex Deucher
0 siblings, 0 replies; 2+ messages in thread
From: Alex Deucher @ 2021-11-12 15:33 UTC (permalink / raw)
To: Perry Yuan
Cc: Deucher, Alexander, Xinmei.Huang, Huang Rui, Limonciello, Mario,
amd-gfx list
On Thu, Nov 11, 2021 at 4:35 AM Perry Yuan <Perry.Yuan@amd.com> wrote:
>
> add support that allow the userspace tool like RGP to get the GFX clock
> value at runtime, the fix follow the old way to show the min/current/max
> clocks level for compatible consideration.
>
> === Test ===
> $ cat /sys/class/drm/card0/device/pp_dpm_sclk
> 0: 200Mhz *
> 1: 1100Mhz
> 2: 1600Mhz
>
> then run stress test on one APU system.
> $ cat /sys/class/drm/card0/device/pp_dpm_sclk
> 0: 200Mhz
> 1: 1040Mhz *
> 2: 1600Mhz
>
> The current GFXCLK value is updated at runtime.
>
> BugLink: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5260
> Reviewed-by: Huang Ray <Ray.Huang@amd.com>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
Might be cleaner to split this into 3 patches, one for each asic. Either way:
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Alex
> ---
> .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 22 +++++++++++++--
> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 26 ++++++++++++++++++
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 27 +++++++++++++++++++
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h | 1 +
> 4 files changed, 74 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> index 3d4c65bc29dc..6e8343907c32 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> @@ -308,6 +308,7 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
> {
> int ret = 0, size = 0;
> uint32_t cur_value = 0;
> + int i;
>
> smu_cmn_get_sysfs_buf(&buf, &size);
>
> @@ -333,8 +334,6 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
> size += sysfs_emit_at(buf, size, "VDDC: %7umV %10umV\n",
> CYAN_SKILLFISH_VDDC_MIN, CYAN_SKILLFISH_VDDC_MAX);
> break;
> - case SMU_GFXCLK:
> - case SMU_SCLK:
> case SMU_FCLK:
> case SMU_MCLK:
> case SMU_SOCCLK:
> @@ -345,6 +344,25 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
> return ret;
> size += sysfs_emit_at(buf, size, "0: %uMhz *\n", cur_value);
> break;
> + case SMU_SCLK:
> + case SMU_GFXCLK:
> + ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value);
> + if (ret)
> + return ret;
> + if (cur_value == CYAN_SKILLFISH_SCLK_MAX)
> + i = 2;
> + else if (cur_value == CYAN_SKILLFISH_SCLK_MIN)
> + i = 0;
> + else
> + i = 1;
> + size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", CYAN_SKILLFISH_SCLK_MIN,
> + i == 0 ? "*" : "");
> + size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
> + i == 1 ? cur_value : CYAN_SKILLFISH_SCLK_DEFAULT,
> + i == 1 ? "*" : "");
> + size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", CYAN_SKILLFISH_SCLK_MAX,
> + i == 2 ? "*" : "");
> + break;
> default:
> dev_warn(smu->adev->dev, "Unsupported clock type\n");
> return ret;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index f6ef0ce6e9e2..6852e4b45589 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -683,6 +683,7 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
> int i, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> bool cur_value_match_level = false;
> + uint32_t min, max;
>
> memset(&metrics, 0, sizeof(metrics));
>
> @@ -743,6 +744,13 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
> if (ret)
> return ret;
> break;
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
> + if (ret) {
> + return ret;
> + }
> + break;
> default:
> break;
> }
> @@ -768,6 +776,24 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
> if (!cur_value_match_level)
> size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
> break;
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
> + max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
> + if (cur_value == max)
> + i = 2;
> + else if (cur_value == min)
> + i = 0;
> + else
> + i = 1;
> + size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
> + i == 0 ? "*" : "");
> + size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
> + i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
> + i == 1 ? "*" : "");
> + size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
> + i == 2 ? "*" : "");
> + break;
> default:
> break;
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index a403657151ba..cb5326d98f3e 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -781,6 +781,11 @@ static int yellow_carp_get_current_clk_freq(struct smu_context *smu,
> case SMU_FCLK:
> return smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_GetFclkFrequency, 0, value);
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + return smu_cmn_send_smc_msg_with_param(smu,
> + SMU_MSG_GetGfxclkFrequency, 0, value);
> + break;
> default:
> return -EINVAL;
> }
> @@ -1051,6 +1056,7 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu,
> {
> int i, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> + uint32_t min, max;
>
> smu_cmn_get_sysfs_buf(&buf, &size);
>
> @@ -1089,6 +1095,27 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu,
> cur_value == value ? "*" : "");
> }
> break;
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
> + if (ret)
> + goto print_clk_out;
> + min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
> + max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
> + if (cur_value == max)
> + i = 2;
> + else if (cur_value == min)
> + i = 0;
> + else
> + i = 1;
> + size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
> + i == 0 ? "*" : "");
> + size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
> + i == 1 ? cur_value : YELLOW_CARP_UMD_PSTATE_GFXCLK,
> + i == 1 ? "*" : "");
> + size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
> + i == 2 ? "*" : "");
> + break;
> default:
> break;
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
> index b3ad8352c68a..a9205a8ea3ad 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
> @@ -24,5 +24,6 @@
> #define __YELLOW_CARP_PPT_H__
>
> extern void yellow_carp_set_ppt_funcs(struct smu_context *smu);
> +#define YELLOW_CARP_UMD_PSTATE_GFXCLK 1100
>
> #endif
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2021-11-11 9:34 [PATCH v1] drm/amd/pm: add GFXCLK/SCLK clocks level print support for APUs Perry Yuan
2021-11-12 15:33 ` Alex Deucher
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