From: Dan Carpenter <dan.carpenter@oracle.com>
To: kbuild@lists.01.org, Ben Widawsky <ben.widawsky@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Cc: lkp@intel.com, kbuild-all@lists.01.org,
Ben Widawsky <ben.widawsky@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH 14/23] cxl: Introduce topology host registration
Date: Mon, 29 Nov 2021 14:42:23 +0300 [thread overview]
Message-ID: <202111260523.BAvGTRJR-lkp@intel.com> (raw)
In-Reply-To: <20211120000250.1663391-15-ben.widawsky@intel.com>
Hi Ben,
url: https://github.com/0day-ci/linux/commits/Ben-Widawsky/Add-drivers-for-CXL-ports-and-mem-devices/20211120-080513
base: 53989fad1286e652ea3655ae3367ba698da8d2ff
config: x86_64-randconfig-m001-20211118 (https://download.01.org/0day-ci/archive/20211126/202111260523.BAvGTRJR-lkp@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/cxl/acpi.c:399 cxl_acpi_probe() error: uninitialized symbol 'root_port'.
vim +/root_port +399 drivers/cxl/acpi.c
4812be97c015bd Dan Williams 2021-06-09 383 static int cxl_acpi_probe(struct platform_device *pdev)
4812be97c015bd Dan Williams 2021-06-09 384 {
3b94ce7b7bc1b4 Dan Williams 2021-06-09 385 int rc;
4812be97c015bd Dan Williams 2021-06-09 386 struct cxl_port *root_port;
4812be97c015bd Dan Williams 2021-06-09 387 struct device *host = &pdev->dev;
7d4b5ca2e2cb5d Dan Williams 2021-06-09 388 struct acpi_device *adev = ACPI_COMPANION(host);
f4ce1f766f1ebf Dan Williams 2021-10-29 389 struct cxl_cfmws_context ctx;
4812be97c015bd Dan Williams 2021-06-09 390
6b4661f8037e4f Ben Widawsky 2021-11-19 391 rc = cxl_register_topology_host(host);
6b4661f8037e4f Ben Widawsky 2021-11-19 392 if (rc)
6b4661f8037e4f Ben Widawsky 2021-11-19 393 return rc;
6b4661f8037e4f Ben Widawsky 2021-11-19 394
6b4661f8037e4f Ben Widawsky 2021-11-19 395 rc = devm_add_action_or_reset(host, clear_topology_host, host);
6b4661f8037e4f Ben Widawsky 2021-11-19 396 if (rc)
6b4661f8037e4f Ben Widawsky 2021-11-19 397 return rc;
6b4661f8037e4f Ben Widawsky 2021-11-19 398
6b4661f8037e4f Ben Widawsky 2021-11-19 @399 root_port = devm_cxl_add_port(host, CXL_RESOURCE_NONE, root_port);
^^^^^^^^^^
Uninitialized.
4812be97c015bd Dan Williams 2021-06-09 400 if (IS_ERR(root_port))
4812be97c015bd Dan Williams 2021-06-09 401 return PTR_ERR(root_port);
4812be97c015bd Dan Williams 2021-06-09 402 dev_dbg(host, "add: %s\n", dev_name(&root_port->dev));
4812be97c015bd Dan Williams 2021-06-09 403
3b94ce7b7bc1b4 Dan Williams 2021-06-09 404 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
7d4b5ca2e2cb5d Dan Williams 2021-06-09 405 add_host_bridge_dport);
f4ce1f766f1ebf Dan Williams 2021-10-29 406 if (rc < 0)
f4ce1f766f1ebf Dan Williams 2021-10-29 407 return rc;
3b94ce7b7bc1b4 Dan Williams 2021-06-09 408
f4ce1f766f1ebf Dan Williams 2021-10-29 409 ctx = (struct cxl_cfmws_context) {
f4ce1f766f1ebf Dan Williams 2021-10-29 410 .dev = host,
f4ce1f766f1ebf Dan Williams 2021-10-29 411 .root_port = root_port,
f4ce1f766f1ebf Dan Williams 2021-10-29 412 };
f4ce1f766f1ebf Dan Williams 2021-10-29 413 acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
3e23d17ce1980c Alison Schofield 2021-06-17 414
3b94ce7b7bc1b4 Dan Williams 2021-06-09 415 /*
3b94ce7b7bc1b4 Dan Williams 2021-06-09 416 * Root level scanned with host-bridge as dports, now scan host-bridges
3b94ce7b7bc1b4 Dan Williams 2021-06-09 417 * for their role as CXL uports to their CXL-capable PCIe Root Ports.
3b94ce7b7bc1b4 Dan Williams 2021-06-09 418 */
8fdcb1704f61a8 Dan Williams 2021-06-15 419 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
3b94ce7b7bc1b4 Dan Williams 2021-06-09 420 add_host_bridge_uport);
f4ce1f766f1ebf Dan Williams 2021-10-29 421 if (rc < 0)
f4ce1f766f1ebf Dan Williams 2021-10-29 422 return rc;
8fdcb1704f61a8 Dan Williams 2021-06-15 423
8fdcb1704f61a8 Dan Williams 2021-06-15 424 if (IS_ENABLED(CONFIG_CXL_PMEM))
8fdcb1704f61a8 Dan Williams 2021-06-15 425 rc = device_for_each_child(&root_port->dev, root_port,
8fdcb1704f61a8 Dan Williams 2021-06-15 426 add_root_nvdimm_bridge);
8fdcb1704f61a8 Dan Williams 2021-06-15 427 if (rc < 0)
8fdcb1704f61a8 Dan Williams 2021-06-15 428 return rc;
f4ce1f766f1ebf Dan Williams 2021-10-29 429
8fdcb1704f61a8 Dan Williams 2021-06-15 430 return 0;
4812be97c015bd Dan Williams 2021-06-09 431 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
WARNING: multiple messages have this Message-ID (diff)
From: kernel test robot <lkp@intel.com>
To: kbuild@lists.01.org
Subject: Re: [PATCH 14/23] cxl: Introduce topology host registration
Date: Fri, 26 Nov 2021 05:53:06 +0800 [thread overview]
Message-ID: <202111260523.BAvGTRJR-lkp@intel.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 5316 bytes --]
CC: kbuild-all(a)lists.01.org
In-Reply-To: <20211120000250.1663391-15-ben.widawsky@intel.com>
References: <20211120000250.1663391-15-ben.widawsky@intel.com>
TO: Ben Widawsky <ben.widawsky@intel.com>
TO: linux-cxl(a)vger.kernel.org
TO: linux-pci(a)vger.kernel.org
CC: Ben Widawsky <ben.widawsky@intel.com>
CC: Alison Schofield <alison.schofield@intel.com>
CC: Dan Williams <dan.j.williams@intel.com>
CC: Ira Weiny <ira.weiny@intel.com>
CC: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
CC: Vishal Verma <vishal.l.verma@intel.com>
Hi Ben,
I love your patch! Perhaps something to improve:
[auto build test WARNING on 53989fad1286e652ea3655ae3367ba698da8d2ff]
url: https://github.com/0day-ci/linux/commits/Ben-Widawsky/Add-drivers-for-CXL-ports-and-mem-devices/20211120-080513
base: 53989fad1286e652ea3655ae3367ba698da8d2ff
:::::: branch date: 6 days ago
:::::: commit date: 6 days ago
config: x86_64-randconfig-m001-20211118 (https://download.01.org/0day-ci/archive/20211126/202111260523.BAvGTRJR-lkp(a)intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/cxl/acpi.c:399 cxl_acpi_probe() error: uninitialized symbol 'root_port'.
vim +/root_port +399 drivers/cxl/acpi.c
6b4661f8037e4f Ben Widawsky 2021-11-19 382
4812be97c015bd Dan Williams 2021-06-09 383 static int cxl_acpi_probe(struct platform_device *pdev)
4812be97c015bd Dan Williams 2021-06-09 384 {
3b94ce7b7bc1b4 Dan Williams 2021-06-09 385 int rc;
4812be97c015bd Dan Williams 2021-06-09 386 struct cxl_port *root_port;
4812be97c015bd Dan Williams 2021-06-09 387 struct device *host = &pdev->dev;
7d4b5ca2e2cb5d Dan Williams 2021-06-09 388 struct acpi_device *adev = ACPI_COMPANION(host);
f4ce1f766f1ebf Dan Williams 2021-10-29 389 struct cxl_cfmws_context ctx;
4812be97c015bd Dan Williams 2021-06-09 390
6b4661f8037e4f Ben Widawsky 2021-11-19 391 rc = cxl_register_topology_host(host);
6b4661f8037e4f Ben Widawsky 2021-11-19 392 if (rc)
6b4661f8037e4f Ben Widawsky 2021-11-19 393 return rc;
6b4661f8037e4f Ben Widawsky 2021-11-19 394
6b4661f8037e4f Ben Widawsky 2021-11-19 395 rc = devm_add_action_or_reset(host, clear_topology_host, host);
6b4661f8037e4f Ben Widawsky 2021-11-19 396 if (rc)
6b4661f8037e4f Ben Widawsky 2021-11-19 397 return rc;
6b4661f8037e4f Ben Widawsky 2021-11-19 398
6b4661f8037e4f Ben Widawsky 2021-11-19 @399 root_port = devm_cxl_add_port(host, CXL_RESOURCE_NONE, root_port);
4812be97c015bd Dan Williams 2021-06-09 400 if (IS_ERR(root_port))
4812be97c015bd Dan Williams 2021-06-09 401 return PTR_ERR(root_port);
4812be97c015bd Dan Williams 2021-06-09 402 dev_dbg(host, "add: %s\n", dev_name(&root_port->dev));
4812be97c015bd Dan Williams 2021-06-09 403
3b94ce7b7bc1b4 Dan Williams 2021-06-09 404 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
7d4b5ca2e2cb5d Dan Williams 2021-06-09 405 add_host_bridge_dport);
f4ce1f766f1ebf Dan Williams 2021-10-29 406 if (rc < 0)
f4ce1f766f1ebf Dan Williams 2021-10-29 407 return rc;
3b94ce7b7bc1b4 Dan Williams 2021-06-09 408
f4ce1f766f1ebf Dan Williams 2021-10-29 409 ctx = (struct cxl_cfmws_context) {
f4ce1f766f1ebf Dan Williams 2021-10-29 410 .dev = host,
f4ce1f766f1ebf Dan Williams 2021-10-29 411 .root_port = root_port,
f4ce1f766f1ebf Dan Williams 2021-10-29 412 };
f4ce1f766f1ebf Dan Williams 2021-10-29 413 acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
3e23d17ce1980c Alison Schofield 2021-06-17 414
3b94ce7b7bc1b4 Dan Williams 2021-06-09 415 /*
3b94ce7b7bc1b4 Dan Williams 2021-06-09 416 * Root level scanned with host-bridge as dports, now scan host-bridges
3b94ce7b7bc1b4 Dan Williams 2021-06-09 417 * for their role as CXL uports to their CXL-capable PCIe Root Ports.
3b94ce7b7bc1b4 Dan Williams 2021-06-09 418 */
8fdcb1704f61a8 Dan Williams 2021-06-15 419 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
3b94ce7b7bc1b4 Dan Williams 2021-06-09 420 add_host_bridge_uport);
f4ce1f766f1ebf Dan Williams 2021-10-29 421 if (rc < 0)
f4ce1f766f1ebf Dan Williams 2021-10-29 422 return rc;
8fdcb1704f61a8 Dan Williams 2021-06-15 423
8fdcb1704f61a8 Dan Williams 2021-06-15 424 if (IS_ENABLED(CONFIG_CXL_PMEM))
8fdcb1704f61a8 Dan Williams 2021-06-15 425 rc = device_for_each_child(&root_port->dev, root_port,
8fdcb1704f61a8 Dan Williams 2021-06-15 426 add_root_nvdimm_bridge);
8fdcb1704f61a8 Dan Williams 2021-06-15 427 if (rc < 0)
8fdcb1704f61a8 Dan Williams 2021-06-15 428 return rc;
f4ce1f766f1ebf Dan Williams 2021-10-29 429
8fdcb1704f61a8 Dan Williams 2021-06-15 430 return 0;
4812be97c015bd Dan Williams 2021-06-09 431 }
4812be97c015bd Dan Williams 2021-06-09 432
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
WARNING: multiple messages have this Message-ID (diff)
From: Dan Carpenter <dan.carpenter@oracle.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH 14/23] cxl: Introduce topology host registration
Date: Mon, 29 Nov 2021 14:42:23 +0300 [thread overview]
Message-ID: <202111260523.BAvGTRJR-lkp@intel.com> (raw)
In-Reply-To: <20211120000250.1663391-15-ben.widawsky@intel.com>
[-- Attachment #1: Type: text/plain, Size: 4624 bytes --]
Hi Ben,
url: https://github.com/0day-ci/linux/commits/Ben-Widawsky/Add-drivers-for-CXL-ports-and-mem-devices/20211120-080513
base: 53989fad1286e652ea3655ae3367ba698da8d2ff
config: x86_64-randconfig-m001-20211118 (https://download.01.org/0day-ci/archive/20211126/202111260523.BAvGTRJR-lkp(a)intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/cxl/acpi.c:399 cxl_acpi_probe() error: uninitialized symbol 'root_port'.
vim +/root_port +399 drivers/cxl/acpi.c
4812be97c015bd Dan Williams 2021-06-09 383 static int cxl_acpi_probe(struct platform_device *pdev)
4812be97c015bd Dan Williams 2021-06-09 384 {
3b94ce7b7bc1b4 Dan Williams 2021-06-09 385 int rc;
4812be97c015bd Dan Williams 2021-06-09 386 struct cxl_port *root_port;
4812be97c015bd Dan Williams 2021-06-09 387 struct device *host = &pdev->dev;
7d4b5ca2e2cb5d Dan Williams 2021-06-09 388 struct acpi_device *adev = ACPI_COMPANION(host);
f4ce1f766f1ebf Dan Williams 2021-10-29 389 struct cxl_cfmws_context ctx;
4812be97c015bd Dan Williams 2021-06-09 390
6b4661f8037e4f Ben Widawsky 2021-11-19 391 rc = cxl_register_topology_host(host);
6b4661f8037e4f Ben Widawsky 2021-11-19 392 if (rc)
6b4661f8037e4f Ben Widawsky 2021-11-19 393 return rc;
6b4661f8037e4f Ben Widawsky 2021-11-19 394
6b4661f8037e4f Ben Widawsky 2021-11-19 395 rc = devm_add_action_or_reset(host, clear_topology_host, host);
6b4661f8037e4f Ben Widawsky 2021-11-19 396 if (rc)
6b4661f8037e4f Ben Widawsky 2021-11-19 397 return rc;
6b4661f8037e4f Ben Widawsky 2021-11-19 398
6b4661f8037e4f Ben Widawsky 2021-11-19 @399 root_port = devm_cxl_add_port(host, CXL_RESOURCE_NONE, root_port);
^^^^^^^^^^
Uninitialized.
4812be97c015bd Dan Williams 2021-06-09 400 if (IS_ERR(root_port))
4812be97c015bd Dan Williams 2021-06-09 401 return PTR_ERR(root_port);
4812be97c015bd Dan Williams 2021-06-09 402 dev_dbg(host, "add: %s\n", dev_name(&root_port->dev));
4812be97c015bd Dan Williams 2021-06-09 403
3b94ce7b7bc1b4 Dan Williams 2021-06-09 404 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
7d4b5ca2e2cb5d Dan Williams 2021-06-09 405 add_host_bridge_dport);
f4ce1f766f1ebf Dan Williams 2021-10-29 406 if (rc < 0)
f4ce1f766f1ebf Dan Williams 2021-10-29 407 return rc;
3b94ce7b7bc1b4 Dan Williams 2021-06-09 408
f4ce1f766f1ebf Dan Williams 2021-10-29 409 ctx = (struct cxl_cfmws_context) {
f4ce1f766f1ebf Dan Williams 2021-10-29 410 .dev = host,
f4ce1f766f1ebf Dan Williams 2021-10-29 411 .root_port = root_port,
f4ce1f766f1ebf Dan Williams 2021-10-29 412 };
f4ce1f766f1ebf Dan Williams 2021-10-29 413 acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
3e23d17ce1980c Alison Schofield 2021-06-17 414
3b94ce7b7bc1b4 Dan Williams 2021-06-09 415 /*
3b94ce7b7bc1b4 Dan Williams 2021-06-09 416 * Root level scanned with host-bridge as dports, now scan host-bridges
3b94ce7b7bc1b4 Dan Williams 2021-06-09 417 * for their role as CXL uports to their CXL-capable PCIe Root Ports.
3b94ce7b7bc1b4 Dan Williams 2021-06-09 418 */
8fdcb1704f61a8 Dan Williams 2021-06-15 419 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
3b94ce7b7bc1b4 Dan Williams 2021-06-09 420 add_host_bridge_uport);
f4ce1f766f1ebf Dan Williams 2021-10-29 421 if (rc < 0)
f4ce1f766f1ebf Dan Williams 2021-10-29 422 return rc;
8fdcb1704f61a8 Dan Williams 2021-06-15 423
8fdcb1704f61a8 Dan Williams 2021-06-15 424 if (IS_ENABLED(CONFIG_CXL_PMEM))
8fdcb1704f61a8 Dan Williams 2021-06-15 425 rc = device_for_each_child(&root_port->dev, root_port,
8fdcb1704f61a8 Dan Williams 2021-06-15 426 add_root_nvdimm_bridge);
8fdcb1704f61a8 Dan Williams 2021-06-15 427 if (rc < 0)
8fdcb1704f61a8 Dan Williams 2021-06-15 428 return rc;
f4ce1f766f1ebf Dan Williams 2021-10-29 429
8fdcb1704f61a8 Dan Williams 2021-06-15 430 return 0;
4812be97c015bd Dan Williams 2021-06-09 431 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
next parent reply other threads:[~2021-11-29 11:44 UTC|newest]
Thread overview: 133+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-25 21:53 kernel test robot [this message]
2021-11-29 11:42 ` [PATCH 14/23] cxl: Introduce topology host registration Dan Carpenter
2021-11-29 11:42 ` Dan Carpenter
-- strict thread matches above, loose matches on Subject: below --
2021-11-20 0:02 [PATCH 00/23] Add drivers for CXL ports and mem devices Ben Widawsky
2021-11-20 0:02 ` [PATCH 01/23] cxl: Rename CXL_MEM to CXL_PCI Ben Widawsky
2021-11-22 14:47 ` Jonathan Cameron
2021-11-24 4:15 ` Dan Williams
2021-11-20 0:02 ` [PATCH 02/23] cxl: Flesh out register names Ben Widawsky
2021-11-22 14:49 ` Jonathan Cameron
2021-11-24 4:24 ` Dan Williams
2021-11-20 0:02 ` [PATCH 03/23] cxl/pci: Extract device status check Ben Widawsky
2021-11-22 15:03 ` Jonathan Cameron
2021-11-24 19:30 ` Dan Williams
2021-11-20 0:02 ` [PATCH 04/23] cxl/pci: Implement Interface Ready Timeout Ben Widawsky
2021-11-22 15:02 ` Jonathan Cameron
2021-11-22 17:17 ` Ben Widawsky
2021-11-22 17:53 ` Jonathan Cameron
2021-11-24 19:56 ` Dan Williams
2021-11-25 6:17 ` Ben Widawsky
2021-11-25 7:14 ` Dan Williams
2021-11-20 0:02 ` [PATCH 05/23] cxl/pci: Don't poll doorbell for mailbox access Ben Widawsky
2021-11-22 15:11 ` Jonathan Cameron
2021-11-22 17:24 ` Ben Widawsky
2021-11-24 21:55 ` Dan Williams
2021-11-29 18:33 ` Ben Widawsky
2021-11-29 19:02 ` Dan Williams
2021-11-29 19:11 ` Ben Widawsky
2021-11-29 19:18 ` Dan Williams
2021-11-29 19:31 ` Ben Widawsky
2021-11-29 19:37 ` Dan Williams
2021-11-29 19:50 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 06/23] cxl/pci: Don't check media status for mbox access Ben Widawsky
2021-11-22 15:19 ` Jonathan Cameron
2021-11-24 21:58 ` Dan Williams
2021-11-20 0:02 ` [PATCH 07/23] cxl/pci: Add new DVSEC definitions Ben Widawsky
2021-11-22 15:22 ` Jonathan Cameron
2021-11-22 17:32 ` Ben Widawsky
2021-11-24 22:03 ` Dan Williams
2021-11-20 0:02 ` [PATCH 08/23] cxl/acpi: Map component registers for Root Ports Ben Widawsky
2021-11-22 15:51 ` Jonathan Cameron
2021-11-22 19:28 ` Ben Widawsky
2021-11-24 22:18 ` Dan Williams
2021-11-20 0:02 ` [PATCH 09/23] cxl: Introduce module_cxl_driver Ben Widawsky
2021-11-22 15:54 ` Jonathan Cameron
2021-11-24 22:22 ` Dan Williams
2021-11-20 0:02 ` [PATCH 10/23] cxl/core: Convert decoder range to resource Ben Widawsky
2021-11-22 16:08 ` Jonathan Cameron
2021-11-24 22:41 ` Dan Williams
2021-11-20 0:02 ` [PATCH 11/23] cxl/core: Document and tighten up decoder APIs Ben Widawsky
2021-11-22 16:13 ` Jonathan Cameron
2021-11-24 22:55 ` Dan Williams
2021-11-20 0:02 ` [PATCH 12/23] cxl: Introduce endpoint decoders Ben Widawsky
2021-11-22 16:20 ` Jonathan Cameron
2021-11-22 19:37 ` Ben Widawsky
2021-11-25 0:07 ` Dan Williams
2021-11-29 20:05 ` Ben Widawsky
2021-11-29 20:07 ` Dan Williams
2021-11-29 20:12 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 13/23] cxl/core: Move target population locking to caller Ben Widawsky
2021-11-22 16:33 ` Jonathan Cameron
2021-11-22 21:58 ` Ben Widawsky
2021-11-23 11:05 ` Jonathan Cameron
2021-11-25 0:34 ` Dan Williams
2021-11-20 0:02 ` [PATCH 14/23] cxl: Introduce topology host registration Ben Widawsky
2021-11-22 18:20 ` Jonathan Cameron
2021-11-22 22:30 ` Ben Widawsky
2021-11-25 1:09 ` Dan Williams
2021-11-29 21:23 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 15/23] cxl/core: Store global list of root ports Ben Widawsky
2021-11-22 18:22 ` Jonathan Cameron
2021-11-22 22:32 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 16/23] cxl/pci: Cache device DVSEC offset Ben Widawsky
2021-11-22 16:46 ` Jonathan Cameron
2021-11-22 22:34 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 17/23] cxl: Cache and pass DVSEC ranges Ben Widawsky
2021-11-20 4:29 ` kernel test robot
2021-11-20 4:29 ` kernel test robot
2021-11-22 17:00 ` Jonathan Cameron
2021-11-22 22:50 ` Ben Widawsky
2021-11-26 11:37 ` Jonathan Cameron
2021-11-20 0:02 ` [PATCH 18/23] cxl/pci: Implement wait for media active Ben Widawsky
2021-11-22 17:03 ` Jonathan Cameron
2021-11-22 22:57 ` Ben Widawsky
2021-11-23 11:09 ` Jonathan Cameron
2021-11-23 16:04 ` Ben Widawsky
2021-11-23 17:48 ` Bjorn Helgaas
2021-11-23 19:37 ` Ben Widawsky
2021-11-26 11:36 ` Jonathan Cameron
2021-11-20 0:02 ` [PATCH 19/23] cxl/pci: Store component register base in cxlds Ben Widawsky
2021-11-20 7:28 ` kernel test robot
2021-11-20 7:28 ` kernel test robot
2021-11-22 17:11 ` Jonathan Cameron
2021-11-22 23:01 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 20/23] cxl/port: Introduce a port driver Ben Widawsky
2021-11-20 3:14 ` kernel test robot
2021-11-20 3:14 ` kernel test robot
2021-11-20 5:38 ` kernel test robot
2021-11-20 5:38 ` kernel test robot
2021-11-22 17:41 ` Jonathan Cameron
2021-11-22 23:38 ` Ben Widawsky
2021-11-23 11:38 ` Jonathan Cameron
2021-11-23 16:14 ` Ben Widawsky
2021-11-23 18:21 ` Bjorn Helgaas
2021-11-23 22:03 ` Ben Widawsky
2021-11-23 22:36 ` Dan Williams
2021-11-23 23:38 ` Ben Widawsky
2021-11-23 23:55 ` Bjorn Helgaas
2021-11-24 0:40 ` Dan Williams
2021-11-24 6:33 ` Christoph Hellwig
2021-11-24 7:17 ` Dan Williams
2021-11-24 7:28 ` Christoph Hellwig
2021-11-24 7:33 ` Greg Kroah-Hartman
2021-11-24 7:54 ` Dan Williams
2021-11-24 8:21 ` Greg Kroah-Hartman
2021-11-24 18:24 ` Dan Williams
2021-12-02 21:24 ` Bjorn Helgaas
2021-12-03 1:38 ` Dan Williams
2021-12-03 22:03 ` Bjorn Helgaas
2021-12-04 1:24 ` Dan Williams
2021-12-07 2:56 ` Bjorn Helgaas
2021-12-07 4:48 ` Dan Williams
2021-11-24 21:31 ` Bjorn Helgaas
2021-11-20 0:02 ` [PATCH 21/23] cxl: Unify port enumeration for decoders Ben Widawsky
2021-11-22 17:48 ` Jonathan Cameron
2021-11-22 23:44 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 22/23] cxl/mem: Introduce cxl_mem driver Ben Widawsky
2021-11-20 0:40 ` Randy Dunlap
2021-11-21 3:55 ` Ben Widawsky
2021-11-22 18:17 ` Jonathan Cameron
2021-11-23 0:05 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 23/23] cxl/mem: Disable switch hierarchies for now Ben Widawsky
2021-11-22 18:19 ` Jonathan Cameron
2021-11-22 19:17 ` Ben Widawsky
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