From: Maxime Ripard <maxime@cerno.tech>
To: Daniel Vetter <daniel.vetter@intel.com>,
David Airlie <airlied@linux.ie>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
Maxime Ripard <maxime@cerno.tech>
Cc: Dom Cobley <dom@raspberrypi.com>,
Tim Gover <tim.gover@raspberrypi.com>,
Dave Stevenson <dave.stevenson@raspberrypi.com>,
dri-devel@lists.freedesktop.org,
Werner Sembach <wse@tuxedocomputers.com>,
Phil Elwell <phil@raspberrypi.com>
Subject: [PATCH 05/11] drm/vc4: hdmi: Replace CSC_CTL hardcoded value by defines
Date: Fri, 3 Dec 2021 11:54:14 +0100 [thread overview]
Message-ID: <20211203105420.573494-6-maxime@cerno.tech> (raw)
In-Reply-To: <20211203105420.573494-1-maxime@cerno.tech>
On BCM2711, the HDMI_CSC_CTL register value has been hardcoded to an
opaque value. Let's replace it with properly defined values.
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 5 ++---
drivers/gpu/drm/vc4/vc4_regs.h | 3 +++
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 0f8b1e907fae..682c3c907cbe 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -779,9 +779,8 @@ static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
const struct drm_display_mode *mode)
{
unsigned long flags;
- u32 csc_ctl;
-
- csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
+ u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
+ VC5_MT_CP_CSC_CTL_MODE);
spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 489f921ef44d..952f2aad0785 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -774,6 +774,9 @@ enum {
# define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
# define VC4_HD_CSC_CTL_ENABLE BIT(0)
+# define VC5_MT_CP_CSC_CTL_ENABLE BIT(2)
+# define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0)
+
# define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
/* HVS display list information. */
--
2.33.1
next prev parent reply other threads:[~2021-12-03 10:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-03 10:54 [PATCH 00/11] drm/vc4: hdmi: Yet Another Approach to HDMI YUV output Maxime Ripard
2021-12-03 10:54 ` [PATCH 01/11] drm/edid: Rename drm_hdmi_avi_infoframe_colorspace to _colorimetry Maxime Ripard
2021-12-03 10:54 ` [PATCH 02/11] drm/vc4: hdmi: Add full range RGB helper Maxime Ripard
2021-12-03 10:54 ` [PATCH 03/11] drm/vc4: hdmi: Use full range helper in csc functions Maxime Ripard
2021-12-03 10:54 ` [PATCH 04/11] drm/vc4: hdmi: Move XBAR setup to csc_setup Maxime Ripard
2021-12-03 10:54 ` Maxime Ripard [this message]
2021-12-03 10:54 ` [PATCH 06/11] drm/vc4: hdmi: Define colorspace matrices Maxime Ripard
2021-12-03 10:54 ` [PATCH 07/11] drm/vc4: hdmi: Change CSC callback prototype Maxime Ripard
2021-12-03 10:54 ` [PATCH 08/11] drm/vc4: hdmi: Move clock validation to its own function Maxime Ripard
2021-12-03 10:54 ` [PATCH 09/11] drm/vc4: hdmi: Move clock calculation into " Maxime Ripard
2021-12-03 10:54 ` [PATCH 10/11] drm/vc4: hdmi: Support HDMI YUV output Maxime Ripard
2021-12-03 12:56 ` kernel test robot
2021-12-03 12:56 ` kernel test robot
2021-12-04 0:30 ` kernel test robot
2021-12-04 0:30 ` kernel test robot
2021-12-03 10:54 ` [PATCH 11/11] drm/vc4: hdmi: Force YUV422 if the rate is too high Maxime Ripard
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