From: Matthew Auld <matthew.auld@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [PATCH v3 0/8] DG2 accelerated migration/clearing support Date: Mon, 6 Dec 2021 13:31:32 +0000 [thread overview] Message-ID: <20211206133140.3166205-1-matthew.auld@intel.com> (raw) Enable accelerated moves and clearing on DG2. On such HW we have minimum page size restrictions when accessing LMEM from the GTT, where we now have to use 64K GTT pages or larger. With the ppGTT the page-table also has a slightly different layout from past generations when using the 64K GTT mode(which is still enabled on via some PDE bit), where it is now compacted down to 32 qword entries. Note that on discrete the paging structures must also be placed in LMEM, and we need to able to modify them via the GTT itself(see patch 7), which is one of the complications here. The series needs to be applied on top of the DG2 enabling branch: https://cgit.freedesktop.org/~ramaling/linux/log/?h=dg2_enabling_ww49.3 Matthew Auld (8): drm/i915/migrate: don't check the scratch page drm/i915/migrate: fix offset calculation drm/i915/migrate: fix length calculation drm/i915/selftests: handle object rounding drm/i915/gtt: allow overriding the pt alignment drm/i915/gtt: add xehpsdv_ppgtt_insert_entry drm/i915/migrate: add acceleration support for DG2 drm/i915/migrate: turn on acceleration for DG2 drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 50 +++++- drivers/gpu/drm/i915/gt/intel_gtt.h | 10 +- drivers/gpu/drm/i915/gt/intel_migrate.c | 195 ++++++++++++++++----- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 16 +- drivers/gpu/drm/i915/gt/selftest_migrate.c | 1 + 5 files changed, 221 insertions(+), 51 deletions(-) -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Auld <matthew.auld@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v3 0/8] DG2 accelerated migration/clearing support Date: Mon, 6 Dec 2021 13:31:32 +0000 [thread overview] Message-ID: <20211206133140.3166205-1-matthew.auld@intel.com> (raw) Enable accelerated moves and clearing on DG2. On such HW we have minimum page size restrictions when accessing LMEM from the GTT, where we now have to use 64K GTT pages or larger. With the ppGTT the page-table also has a slightly different layout from past generations when using the 64K GTT mode(which is still enabled on via some PDE bit), where it is now compacted down to 32 qword entries. Note that on discrete the paging structures must also be placed in LMEM, and we need to able to modify them via the GTT itself(see patch 7), which is one of the complications here. The series needs to be applied on top of the DG2 enabling branch: https://cgit.freedesktop.org/~ramaling/linux/log/?h=dg2_enabling_ww49.3 Matthew Auld (8): drm/i915/migrate: don't check the scratch page drm/i915/migrate: fix offset calculation drm/i915/migrate: fix length calculation drm/i915/selftests: handle object rounding drm/i915/gtt: allow overriding the pt alignment drm/i915/gtt: add xehpsdv_ppgtt_insert_entry drm/i915/migrate: add acceleration support for DG2 drm/i915/migrate: turn on acceleration for DG2 drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 50 +++++- drivers/gpu/drm/i915/gt/intel_gtt.h | 10 +- drivers/gpu/drm/i915/gt/intel_migrate.c | 195 ++++++++++++++++----- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 16 +- drivers/gpu/drm/i915/gt/selftest_migrate.c | 1 + 5 files changed, 221 insertions(+), 51 deletions(-) -- 2.31.1
next reply other threads:[~2021-12-06 13:32 UTC|newest] Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-06 13:31 Matthew Auld [this message] 2021-12-06 13:31 ` [Intel-gfx] [PATCH v3 0/8] DG2 accelerated migration/clearing support Matthew Auld 2021-12-06 13:31 ` [PATCH v3 1/8] drm/i915/migrate: don't check the scratch page Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 13:31 ` [PATCH v3 2/8] drm/i915/migrate: fix offset calculation Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 13:31 ` [PATCH v3 3/8] drm/i915/migrate: fix length calculation Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 13:31 ` [PATCH v3 4/8] drm/i915/selftests: handle object rounding Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 13:31 ` [PATCH v3 5/8] drm/i915/gtt: allow overriding the pt alignment Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-13 15:32 ` Ramalingam C 2021-12-13 15:32 ` [Intel-gfx] " Ramalingam C 2021-12-06 13:31 ` [PATCH v3 6/8] drm/i915/gtt: add xehpsdv_ppgtt_insert_entry Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 13:31 ` [PATCH v3 7/8] drm/i915/migrate: add acceleration support for DG2 Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-14 10:56 ` Ramalingam C 2021-12-14 10:56 ` [Intel-gfx] " Ramalingam C 2021-12-14 12:32 ` Matthew Auld 2021-12-14 12:32 ` [Intel-gfx] " Matthew Auld 2021-12-16 15:01 ` Ramalingam C 2021-12-16 15:01 ` [Intel-gfx] " Ramalingam C 2021-12-06 13:31 ` [PATCH v3 8/8] drm/i915/migrate: turn on acceleration " Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 14:05 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for DG2 accelerated migration/clearing support (rev2) Patchwork 2021-12-06 14:49 ` [PATCH v3 0/8] DG2 accelerated migration/clearing support Daniel Stone 2021-12-06 14:49 ` [Intel-gfx] " Daniel Stone 2021-12-06 15:13 ` Matthew Auld 2021-12-06 15:13 ` [Intel-gfx] " Matthew Auld
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