* drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 749)
@ 2021-12-17 7:25 ` Dan Carpenter
0 siblings, 0 replies; 5+ messages in thread
From: kernel test robot @ 2021-12-16 9:28 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 18437 bytes --]
CC: kbuild-all(a)lists.01.org
CC: linux-kernel(a)vger.kernel.org
TO: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
CC: Alex Deucher <alexander.deucher@amd.com>
CC: Joshua Aberback <joshua.aberback@amd.com>
CC: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 2b14864acbaaf03d9c01982e243a84632524c3ac
commit: ea7154d8d9fb26129f51e4d763febe97a13228a5 drm/amd/display: Update dcn30_apply_idle_power_optimizations() code
date: 11 months ago
:::::: branch date: 14 hours ago
:::::: commit date: 11 months ago
config: x86_64-randconfig-m001-20211207 (https://download.01.org/0day-ci/archive/20211216/202112161717.aP6FA32v-lkp(a)intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 749)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:767 dcn30_apply_idle_power_optimizations() error: we previously assumed 'plane' could be null (see line 749)
Old smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:483 dcn30_init_hw() warn: variable dereferenced before check 'res_pool->dccg' (see line 435)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:636 dcn30_init_hw() error: we previously assumed 'dc->clk_mgr' could be null (see line 431)
vim +/stream +765 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 709
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 710 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 711 {
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 712 union dmub_rb_cmd cmd;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 713 uint32_t tmr_delay = 0, tmr_scale = 0;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 714 struct dc_cursor_attributes cursor_attr;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 715 bool cursor_cache_enable = false;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 716 struct dc_stream_state *stream = NULL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 717 struct dc_plane_state *plane = NULL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 718
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 719 if (!dc->ctx->dmub_srv)
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 720 return false;
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 721
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 722 if (enable) {
48e48e59847821 Zhan Liu 2020-08-28 723 if (dc->current_state) {
48e48e59847821 Zhan Liu 2020-08-28 724 int i;
48e48e59847821 Zhan Liu 2020-08-28 725
48e48e59847821 Zhan Liu 2020-08-28 726 /* First, check no-memory-requests case */
48e48e59847821 Zhan Liu 2020-08-28 727 for (i = 0; i < dc->current_state->stream_count; i++) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 728 if (dc->current_state->stream_status[i].plane_count)
48e48e59847821 Zhan Liu 2020-08-28 729 /* Fail eligibility on a visible stream */
48e48e59847821 Zhan Liu 2020-08-28 730 break;
48e48e59847821 Zhan Liu 2020-08-28 731 }
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 732
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 733 if (i == dc->current_state->stream_count) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 734 /* Enable no-memory-requests case */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 735 memset(&cmd, 0, sizeof(cmd));
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 736 cmd.mall.header.type = DMUB_CMD__MALL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 737 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 738 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 739
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 740 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 741 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 742
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 743 return true;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 744 }
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 745
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 746 stream = dc->current_state->streams[0];
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 747 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 748
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @749 if (stream && plane) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 750 cursor_cache_enable = stream->cursor_position.enable &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 751 plane->address.grph.cursor_cache_addr.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 752 cursor_attr = stream->cursor_attributes;
a87a9a73d0e283 Alex Deucher 2020-10-26 753 }
a87a9a73d0e283 Alex Deucher 2020-10-26 754
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 755 /*
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 756 * Second, check MALL eligibility
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 757 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 758 * single display only, single surface only, 8 and 16 bit formats only, no VM,
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 759 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 760 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 761 * TODO: When we implement multi-display, PSR displays will be allowed if there is
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 762 * a non-PSR display present, since in that case we can't do D0i3.2
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 763 */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 764 if (dc->current_state->stream_count == 1 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @765 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 766 dc->current_state->stream_status[0].plane_count == 1 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @767 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 768 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 769 plane->address.page_table_base.quad_part == 0 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 770 dc->hwss.does_plane_fit_in_mall &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 771 dc->hwss.does_plane_fit_in_mall(dc, plane,
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 772 cursor_cache_enable ? &cursor_attr : NULL)) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 773 unsigned int v_total = stream->adjust.v_total_max ?
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 774 stream->adjust.v_total_max : stream->timing.v_total;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 775 unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 776 100LL / (v_total * stream->timing.h_total);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 777
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 778 /*
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 779 * one frame time in microsec:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 780 * Delay_Us = 1000000 / refresh
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 781 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 782 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 783 * one frame time modified by 'additional timer percent' (p):
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 784 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 785 * = dynamic_delay_us * (1 + p / 100)
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 786 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 787 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 788 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 789 * formula for timer duration based on parameters, from regspec:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 790 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 791 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 792 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 793 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 794 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 795 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 796 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 797 *
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 798 * need to round up the result of the division before the subtraction
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 799 */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 800 unsigned int denom = refresh_hz * 6528;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 801 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 802
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 803 tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 804 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 805 denom) - 64LL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 806
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 807 /* scale should be increased until it fits into 6 bits */
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 808 while (tmr_delay & ~0x3F) {
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 809 tmr_scale++;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 810
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 811 if (tmr_scale > 3) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 812 /* Delay exceeds range of hysteresis timer */
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 813 ASSERT(false);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 814 return false;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 815 }
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 816
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 817 denom *= 2;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 818 tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 819 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 820 denom) - 64LL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 821 }
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 822
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 823 /* Copy HW cursor */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 824 if (cursor_cache_enable) {
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 825 memset(&cmd, 0, sizeof(cmd));
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 826 cmd.mall.header.type = DMUB_CMD__MALL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 827 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 828 cmd.mall.header.payload_bytes =
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 829 sizeof(cmd.mall) - sizeof(cmd.mall.header);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 830
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 831 switch (cursor_attr.color_format) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 832 case CURSOR_MODE_MONO:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 833 cmd.mall.cursor_bpp = 2;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 834 break;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 835 case CURSOR_MODE_COLOR_1BIT_AND:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 836 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 837 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 838 cmd.mall.cursor_bpp = 32;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 839 break;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 840
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 841 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 842 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 843 cmd.mall.cursor_bpp = 64;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 844 break;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 845 }
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 846
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 847 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 848 cmd.mall.cursor_copy_dst.quad_part =
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 849 plane->address.grph.cursor_cache_addr.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 850 cmd.mall.cursor_width = cursor_attr.width;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 851 cmd.mall.cursor_height = cursor_attr.height;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 852 cmd.mall.cursor_pitch = cursor_attr.pitch;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 853
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 854 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 855 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 856 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 857
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 858 /* Use copied cursor, and it's okay to not switch back */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 859 cursor_attr.address.quad_part =
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 860 plane->address.grph.cursor_cache_addr.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 861 dc_stream_set_cursor_attributes(stream, &cursor_attr);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 862 }
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 863
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 864 /* Enable MALL */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 865 memset(&cmd, 0, sizeof(cmd));
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 866 cmd.mall.header.type = DMUB_CMD__MALL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 867 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 868 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 869 cmd.mall.tmr_delay = tmr_delay;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 870 cmd.mall.tmr_scale = tmr_scale;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 871 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 872
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 873 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 874 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 875
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 876 return true;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 877 }
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 878 }
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 879
48e48e59847821 Zhan Liu 2020-08-28 880 /* No applicable optimizations */
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 881 return false;
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 882 }
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 883
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 884 /* Disable MALL */
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 885 memset(&cmd, 0, sizeof(cmd));
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 886 cmd.mall.header.type = DMUB_CMD__MALL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 887 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 888 cmd.mall.header.payload_bytes =
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 889 sizeof(cmd.mall) - sizeof(cmd.mall.header);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 890
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 891 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 892 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 893 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 894
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 895 return true;
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 896 }
3e19095534caec Joshua Aberback 2020-04-29 897
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 5+ messages in thread
* drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 749)
@ 2021-12-17 7:25 ` Dan Carpenter
0 siblings, 0 replies; 5+ messages in thread
From: Dan Carpenter @ 2021-12-17 7:25 UTC (permalink / raw)
To: kbuild, Bhawanpreet Lakha
Cc: lkp, kbuild-all, linux-kernel, Alex Deucher, Joshua Aberback,
Nicholas Kazlauskas
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 2b14864acbaaf03d9c01982e243a84632524c3ac
commit: ea7154d8d9fb26129f51e4d763febe97a13228a5 drm/amd/display: Update dcn30_apply_idle_power_optimizations() code
config: x86_64-randconfig-m001-20211207 (https://download.01.org/0day-ci/archive/20211216/202112161717.aP6FA32v-lkp@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 749)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:767 dcn30_apply_idle_power_optimizations() error: we previously assumed 'plane' could be null (see line 749)
Old smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:483 dcn30_init_hw() warn: variable dereferenced before check 'res_pool->dccg' (see line 435)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:636 dcn30_init_hw() error: we previously assumed 'dc->clk_mgr' could be null (see line 431)
vim +/stream +765 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 710 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 711 {
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 712 union dmub_rb_cmd cmd;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 713 uint32_t tmr_delay = 0, tmr_scale = 0;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 714 struct dc_cursor_attributes cursor_attr;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 715 bool cursor_cache_enable = false;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 716 struct dc_stream_state *stream = NULL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 717 struct dc_plane_state *plane = NULL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 718
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 719 if (!dc->ctx->dmub_srv)
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 720 return false;
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 721
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 722 if (enable) {
48e48e59847821 Zhan Liu 2020-08-28 723 if (dc->current_state) {
48e48e59847821 Zhan Liu 2020-08-28 724 int i;
48e48e59847821 Zhan Liu 2020-08-28 725
48e48e59847821 Zhan Liu 2020-08-28 726 /* First, check no-memory-requests case */
48e48e59847821 Zhan Liu 2020-08-28 727 for (i = 0; i < dc->current_state->stream_count; i++) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 728 if (dc->current_state->stream_status[i].plane_count)
48e48e59847821 Zhan Liu 2020-08-28 729 /* Fail eligibility on a visible stream */
48e48e59847821 Zhan Liu 2020-08-28 730 break;
48e48e59847821 Zhan Liu 2020-08-28 731 }
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 732
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 733 if (i == dc->current_state->stream_count) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 734 /* Enable no-memory-requests case */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 735 memset(&cmd, 0, sizeof(cmd));
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 736 cmd.mall.header.type = DMUB_CMD__MALL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 737 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 738 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 739
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 740 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 741 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 742
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 743 return true;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 744 }
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 745
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 746 stream = dc->current_state->streams[0];
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 747 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 748
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @749 if (stream && plane) {
^^^^^^^^^^^^^^^
Checks for NULL
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 750 cursor_cache_enable = stream->cursor_position.enable &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 751 plane->address.grph.cursor_cache_addr.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 752 cursor_attr = stream->cursor_attributes;
a87a9a73d0e283 Alex Deucher 2020-10-26 753 }
a87a9a73d0e283 Alex Deucher 2020-10-26 754
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 755 /*
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 756 * Second, check MALL eligibility
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 757 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 758 * single display only, single surface only, 8 and 16 bit formats only, no VM,
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 759 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 760 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 761 * TODO: When we implement multi-display, PSR displays will be allowed if there is
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 762 * a non-PSR display present, since in that case we can't do D0i3.2
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 763 */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 764 if (dc->current_state->stream_count == 1 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @765 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
^^^^^^^^
Unchecked dereferences.
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 766 dc->current_state->stream_status[0].plane_count == 1 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @767 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
^^^^^^^^^^^^^
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 768 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 769 plane->address.page_table_base.quad_part == 0 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 770 dc->hwss.does_plane_fit_in_mall &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 771 dc->hwss.does_plane_fit_in_mall(dc, plane,
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 772 cursor_cache_enable ? &cursor_attr : NULL)) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 773 unsigned int v_total = stream->adjust.v_total_max ?
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 774 stream->adjust.v_total_max : stream->timing.v_total;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 775 unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 776 100LL / (v_total * stream->timing.h_total);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 777
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 778 /*
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 779 * one frame time in microsec:
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply [flat|nested] 5+ messages in thread
* drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 749)
@ 2021-12-17 7:25 ` Dan Carpenter
0 siblings, 0 replies; 5+ messages in thread
From: Dan Carpenter @ 2021-12-17 7:25 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 7959 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 2b14864acbaaf03d9c01982e243a84632524c3ac
commit: ea7154d8d9fb26129f51e4d763febe97a13228a5 drm/amd/display: Update dcn30_apply_idle_power_optimizations() code
config: x86_64-randconfig-m001-20211207 (https://download.01.org/0day-ci/archive/20211216/202112161717.aP6FA32v-lkp(a)intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 749)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:767 dcn30_apply_idle_power_optimizations() error: we previously assumed 'plane' could be null (see line 749)
Old smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:483 dcn30_init_hw() warn: variable dereferenced before check 'res_pool->dccg' (see line 435)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:636 dcn30_init_hw() error: we previously assumed 'dc->clk_mgr' could be null (see line 431)
vim +/stream +765 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 710 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 711 {
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 712 union dmub_rb_cmd cmd;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 713 uint32_t tmr_delay = 0, tmr_scale = 0;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 714 struct dc_cursor_attributes cursor_attr;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 715 bool cursor_cache_enable = false;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 716 struct dc_stream_state *stream = NULL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 717 struct dc_plane_state *plane = NULL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 718
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 719 if (!dc->ctx->dmub_srv)
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 720 return false;
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 721
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 722 if (enable) {
48e48e59847821 Zhan Liu 2020-08-28 723 if (dc->current_state) {
48e48e59847821 Zhan Liu 2020-08-28 724 int i;
48e48e59847821 Zhan Liu 2020-08-28 725
48e48e59847821 Zhan Liu 2020-08-28 726 /* First, check no-memory-requests case */
48e48e59847821 Zhan Liu 2020-08-28 727 for (i = 0; i < dc->current_state->stream_count; i++) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 728 if (dc->current_state->stream_status[i].plane_count)
48e48e59847821 Zhan Liu 2020-08-28 729 /* Fail eligibility on a visible stream */
48e48e59847821 Zhan Liu 2020-08-28 730 break;
48e48e59847821 Zhan Liu 2020-08-28 731 }
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 732
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 733 if (i == dc->current_state->stream_count) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 734 /* Enable no-memory-requests case */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 735 memset(&cmd, 0, sizeof(cmd));
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 736 cmd.mall.header.type = DMUB_CMD__MALL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 737 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 738 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 739
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 740 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 741 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 742
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 743 return true;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 744 }
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 745
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 746 stream = dc->current_state->streams[0];
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 747 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 748
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @749 if (stream && plane) {
^^^^^^^^^^^^^^^
Checks for NULL
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 750 cursor_cache_enable = stream->cursor_position.enable &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 751 plane->address.grph.cursor_cache_addr.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 752 cursor_attr = stream->cursor_attributes;
a87a9a73d0e283 Alex Deucher 2020-10-26 753 }
a87a9a73d0e283 Alex Deucher 2020-10-26 754
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 755 /*
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 756 * Second, check MALL eligibility
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 757 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 758 * single display only, single surface only, 8 and 16 bit formats only, no VM,
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 759 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 760 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 761 * TODO: When we implement multi-display, PSR displays will be allowed if there is
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 762 * a non-PSR display present, since in that case we can't do D0i3.2
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 763 */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 764 if (dc->current_state->stream_count == 1 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @765 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
^^^^^^^^
Unchecked dereferences.
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 766 dc->current_state->stream_status[0].plane_count == 1 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @767 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
^^^^^^^^^^^^^
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 768 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 769 plane->address.page_table_base.quad_part == 0 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 770 dc->hwss.does_plane_fit_in_mall &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 771 dc->hwss.does_plane_fit_in_mall(dc, plane,
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 772 cursor_cache_enable ? &cursor_attr : NULL)) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 773 unsigned int v_total = stream->adjust.v_total_max ?
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 774 stream->adjust.v_total_max : stream->timing.v_total;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 775 unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 776 100LL / (v_total * stream->timing.h_total);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 777
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 778 /*
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 779 * one frame time in microsec:
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 5+ messages in thread
* drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 749)
@ 2021-12-11 18:19 kernel test robot
0 siblings, 0 replies; 5+ messages in thread
From: kernel test robot @ 2021-12-11 18:19 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 18437 bytes --]
CC: kbuild-all(a)lists.01.org
CC: linux-kernel(a)vger.kernel.org
TO: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
CC: Alex Deucher <alexander.deucher@amd.com>
CC: Joshua Aberback <joshua.aberback@amd.com>
CC: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 6f513529296fd4f696afb4354c46508abe646541
commit: ea7154d8d9fb26129f51e4d763febe97a13228a5 drm/amd/display: Update dcn30_apply_idle_power_optimizations() code
date: 11 months ago
:::::: branch date: 17 hours ago
:::::: commit date: 11 months ago
config: x86_64-randconfig-m001-20211207 (https://download.01.org/0day-ci/archive/20211212/202112120210.IMVuMFg2-lkp(a)intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 749)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:767 dcn30_apply_idle_power_optimizations() error: we previously assumed 'plane' could be null (see line 749)
Old smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:483 dcn30_init_hw() warn: variable dereferenced before check 'res_pool->dccg' (see line 435)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:636 dcn30_init_hw() error: we previously assumed 'dc->clk_mgr' could be null (see line 431)
vim +/stream +765 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 709
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 710 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 711 {
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 712 union dmub_rb_cmd cmd;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 713 uint32_t tmr_delay = 0, tmr_scale = 0;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 714 struct dc_cursor_attributes cursor_attr;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 715 bool cursor_cache_enable = false;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 716 struct dc_stream_state *stream = NULL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 717 struct dc_plane_state *plane = NULL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 718
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 719 if (!dc->ctx->dmub_srv)
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 720 return false;
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 721
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 722 if (enable) {
48e48e59847821 Zhan Liu 2020-08-28 723 if (dc->current_state) {
48e48e59847821 Zhan Liu 2020-08-28 724 int i;
48e48e59847821 Zhan Liu 2020-08-28 725
48e48e59847821 Zhan Liu 2020-08-28 726 /* First, check no-memory-requests case */
48e48e59847821 Zhan Liu 2020-08-28 727 for (i = 0; i < dc->current_state->stream_count; i++) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 728 if (dc->current_state->stream_status[i].plane_count)
48e48e59847821 Zhan Liu 2020-08-28 729 /* Fail eligibility on a visible stream */
48e48e59847821 Zhan Liu 2020-08-28 730 break;
48e48e59847821 Zhan Liu 2020-08-28 731 }
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 732
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 733 if (i == dc->current_state->stream_count) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 734 /* Enable no-memory-requests case */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 735 memset(&cmd, 0, sizeof(cmd));
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 736 cmd.mall.header.type = DMUB_CMD__MALL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 737 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 738 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 739
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 740 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 741 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 742
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 743 return true;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 744 }
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 745
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 746 stream = dc->current_state->streams[0];
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 747 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 748
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @749 if (stream && plane) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 750 cursor_cache_enable = stream->cursor_position.enable &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 751 plane->address.grph.cursor_cache_addr.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 752 cursor_attr = stream->cursor_attributes;
a87a9a73d0e283 Alex Deucher 2020-10-26 753 }
a87a9a73d0e283 Alex Deucher 2020-10-26 754
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 755 /*
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 756 * Second, check MALL eligibility
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 757 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 758 * single display only, single surface only, 8 and 16 bit formats only, no VM,
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 759 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 760 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 761 * TODO: When we implement multi-display, PSR displays will be allowed if there is
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 762 * a non-PSR display present, since in that case we can't do D0i3.2
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 763 */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 764 if (dc->current_state->stream_count == 1 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @765 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 766 dc->current_state->stream_status[0].plane_count == 1 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @767 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 768 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 769 plane->address.page_table_base.quad_part == 0 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 770 dc->hwss.does_plane_fit_in_mall &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 771 dc->hwss.does_plane_fit_in_mall(dc, plane,
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 772 cursor_cache_enable ? &cursor_attr : NULL)) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 773 unsigned int v_total = stream->adjust.v_total_max ?
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 774 stream->adjust.v_total_max : stream->timing.v_total;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 775 unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 776 100LL / (v_total * stream->timing.h_total);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 777
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 778 /*
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 779 * one frame time in microsec:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 780 * Delay_Us = 1000000 / refresh
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 781 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 782 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 783 * one frame time modified by 'additional timer percent' (p):
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 784 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 785 * = dynamic_delay_us * (1 + p / 100)
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 786 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 787 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 788 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 789 * formula for timer duration based on parameters, from regspec:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 790 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 791 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 792 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 793 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 794 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 795 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 796 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 797 *
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 798 * need to round up the result of the division before the subtraction
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 799 */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 800 unsigned int denom = refresh_hz * 6528;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 801 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 802
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 803 tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 804 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 805 denom) - 64LL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 806
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 807 /* scale should be increased until it fits into 6 bits */
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 808 while (tmr_delay & ~0x3F) {
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 809 tmr_scale++;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 810
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 811 if (tmr_scale > 3) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 812 /* Delay exceeds range of hysteresis timer */
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 813 ASSERT(false);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 814 return false;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 815 }
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 816
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 817 denom *= 2;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 818 tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 819 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 820 denom) - 64LL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 821 }
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 822
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 823 /* Copy HW cursor */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 824 if (cursor_cache_enable) {
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 825 memset(&cmd, 0, sizeof(cmd));
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 826 cmd.mall.header.type = DMUB_CMD__MALL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 827 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 828 cmd.mall.header.payload_bytes =
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 829 sizeof(cmd.mall) - sizeof(cmd.mall.header);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 830
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 831 switch (cursor_attr.color_format) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 832 case CURSOR_MODE_MONO:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 833 cmd.mall.cursor_bpp = 2;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 834 break;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 835 case CURSOR_MODE_COLOR_1BIT_AND:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 836 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 837 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 838 cmd.mall.cursor_bpp = 32;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 839 break;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 840
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 841 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 842 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 843 cmd.mall.cursor_bpp = 64;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 844 break;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 845 }
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 846
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 847 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 848 cmd.mall.cursor_copy_dst.quad_part =
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 849 plane->address.grph.cursor_cache_addr.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 850 cmd.mall.cursor_width = cursor_attr.width;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 851 cmd.mall.cursor_height = cursor_attr.height;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 852 cmd.mall.cursor_pitch = cursor_attr.pitch;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 853
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 854 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 855 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 856 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 857
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 858 /* Use copied cursor, and it's okay to not switch back */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 859 cursor_attr.address.quad_part =
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 860 plane->address.grph.cursor_cache_addr.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 861 dc_stream_set_cursor_attributes(stream, &cursor_attr);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 862 }
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 863
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 864 /* Enable MALL */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 865 memset(&cmd, 0, sizeof(cmd));
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 866 cmd.mall.header.type = DMUB_CMD__MALL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 867 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 868 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 869 cmd.mall.tmr_delay = tmr_delay;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 870 cmd.mall.tmr_scale = tmr_scale;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 871 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 872
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 873 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 874 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 875
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 876 return true;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 877 }
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 878 }
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 879
48e48e59847821 Zhan Liu 2020-08-28 880 /* No applicable optimizations */
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 881 return false;
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 882 }
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 883
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 884 /* Disable MALL */
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 885 memset(&cmd, 0, sizeof(cmd));
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 886 cmd.mall.header.type = DMUB_CMD__MALL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 887 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 888 cmd.mall.header.payload_bytes =
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 889 sizeof(cmd.mall) - sizeof(cmd.mall.header);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 890
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 891 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 892 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 893 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 894
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 895 return true;
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 896 }
3e19095534caec Joshua Aberback 2020-04-29 897
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 5+ messages in thread
* drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 749)
@ 2021-11-28 11:58 kernel test robot
0 siblings, 0 replies; 5+ messages in thread
From: kernel test robot @ 2021-11-28 11:58 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 18437 bytes --]
CC: kbuild-all(a)lists.01.org
CC: linux-kernel(a)vger.kernel.org
TO: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
CC: Alex Deucher <alexander.deucher@amd.com>
CC: Joshua Aberback <joshua.aberback@amd.com>
CC: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 3498e7f2bb415e447354a3debef6738d9655768c
commit: ea7154d8d9fb26129f51e4d763febe97a13228a5 drm/amd/display: Update dcn30_apply_idle_power_optimizations() code
date: 10 months ago
:::::: branch date: 13 hours ago
:::::: commit date: 10 months ago
config: x86_64-randconfig-m001-20211116 (https://download.01.org/0day-ci/archive/20211128/202111281952.f2nmRW94-lkp(a)intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 749)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:767 dcn30_apply_idle_power_optimizations() error: we previously assumed 'plane' could be null (see line 749)
Old smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:483 dcn30_init_hw() warn: variable dereferenced before check 'res_pool->dccg' (see line 435)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:636 dcn30_init_hw() error: we previously assumed 'dc->clk_mgr' could be null (see line 431)
vim +/stream +765 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 709
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 710 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 711 {
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 712 union dmub_rb_cmd cmd;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 713 uint32_t tmr_delay = 0, tmr_scale = 0;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 714 struct dc_cursor_attributes cursor_attr;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 715 bool cursor_cache_enable = false;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 716 struct dc_stream_state *stream = NULL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 717 struct dc_plane_state *plane = NULL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 718
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 719 if (!dc->ctx->dmub_srv)
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 720 return false;
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 721
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 722 if (enable) {
48e48e59847821 Zhan Liu 2020-08-28 723 if (dc->current_state) {
48e48e59847821 Zhan Liu 2020-08-28 724 int i;
48e48e59847821 Zhan Liu 2020-08-28 725
48e48e59847821 Zhan Liu 2020-08-28 726 /* First, check no-memory-requests case */
48e48e59847821 Zhan Liu 2020-08-28 727 for (i = 0; i < dc->current_state->stream_count; i++) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 728 if (dc->current_state->stream_status[i].plane_count)
48e48e59847821 Zhan Liu 2020-08-28 729 /* Fail eligibility on a visible stream */
48e48e59847821 Zhan Liu 2020-08-28 730 break;
48e48e59847821 Zhan Liu 2020-08-28 731 }
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 732
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 733 if (i == dc->current_state->stream_count) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 734 /* Enable no-memory-requests case */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 735 memset(&cmd, 0, sizeof(cmd));
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 736 cmd.mall.header.type = DMUB_CMD__MALL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 737 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 738 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 739
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 740 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 741 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 742
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 743 return true;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 744 }
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 745
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 746 stream = dc->current_state->streams[0];
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 747 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 748
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @749 if (stream && plane) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 750 cursor_cache_enable = stream->cursor_position.enable &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 751 plane->address.grph.cursor_cache_addr.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 752 cursor_attr = stream->cursor_attributes;
a87a9a73d0e283 Alex Deucher 2020-10-26 753 }
a87a9a73d0e283 Alex Deucher 2020-10-26 754
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 755 /*
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 756 * Second, check MALL eligibility
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 757 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 758 * single display only, single surface only, 8 and 16 bit formats only, no VM,
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 759 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 760 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 761 * TODO: When we implement multi-display, PSR displays will be allowed if there is
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 762 * a non-PSR display present, since in that case we can't do D0i3.2
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 763 */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 764 if (dc->current_state->stream_count == 1 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @765 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 766 dc->current_state->stream_status[0].plane_count == 1 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 @767 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 768 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 769 plane->address.page_table_base.quad_part == 0 &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 770 dc->hwss.does_plane_fit_in_mall &&
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 771 dc->hwss.does_plane_fit_in_mall(dc, plane,
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 772 cursor_cache_enable ? &cursor_attr : NULL)) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 773 unsigned int v_total = stream->adjust.v_total_max ?
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 774 stream->adjust.v_total_max : stream->timing.v_total;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 775 unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 776 100LL / (v_total * stream->timing.h_total);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 777
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 778 /*
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 779 * one frame time in microsec:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 780 * Delay_Us = 1000000 / refresh
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 781 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 782 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 783 * one frame time modified by 'additional timer percent' (p):
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 784 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 785 * = dynamic_delay_us * (1 + p / 100)
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 786 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 787 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 788 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 789 * formula for timer duration based on parameters, from regspec:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 790 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 791 *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 792 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 793 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 794 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 795 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 796 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 797 *
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 798 * need to round up the result of the division before the subtraction
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 799 */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 800 unsigned int denom = refresh_hz * 6528;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 801 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 802
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 803 tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 804 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 805 denom) - 64LL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 806
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 807 /* scale should be increased until it fits into 6 bits */
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 808 while (tmr_delay & ~0x3F) {
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 809 tmr_scale++;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 810
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 811 if (tmr_scale > 3) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 812 /* Delay exceeds range of hysteresis timer */
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 813 ASSERT(false);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 814 return false;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 815 }
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 816
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 817 denom *= 2;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 818 tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 819 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 820 denom) - 64LL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 821 }
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 822
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 823 /* Copy HW cursor */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 824 if (cursor_cache_enable) {
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 825 memset(&cmd, 0, sizeof(cmd));
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 826 cmd.mall.header.type = DMUB_CMD__MALL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 827 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 828 cmd.mall.header.payload_bytes =
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 829 sizeof(cmd.mall) - sizeof(cmd.mall.header);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 830
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 831 switch (cursor_attr.color_format) {
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 832 case CURSOR_MODE_MONO:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 833 cmd.mall.cursor_bpp = 2;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 834 break;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 835 case CURSOR_MODE_COLOR_1BIT_AND:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 836 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 837 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 838 cmd.mall.cursor_bpp = 32;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 839 break;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 840
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 841 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 842 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 843 cmd.mall.cursor_bpp = 64;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 844 break;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 845 }
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 846
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 847 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 848 cmd.mall.cursor_copy_dst.quad_part =
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 849 plane->address.grph.cursor_cache_addr.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 850 cmd.mall.cursor_width = cursor_attr.width;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 851 cmd.mall.cursor_height = cursor_attr.height;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 852 cmd.mall.cursor_pitch = cursor_attr.pitch;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 853
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 854 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 855 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 856 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 857
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 858 /* Use copied cursor, and it's okay to not switch back */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 859 cursor_attr.address.quad_part =
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 860 plane->address.grph.cursor_cache_addr.quad_part;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 861 dc_stream_set_cursor_attributes(stream, &cursor_attr);
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 862 }
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 863
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 864 /* Enable MALL */
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 865 memset(&cmd, 0, sizeof(cmd));
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 866 cmd.mall.header.type = DMUB_CMD__MALL;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 867 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 868 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 869 cmd.mall.tmr_delay = tmr_delay;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 870 cmd.mall.tmr_scale = tmr_scale;
ea7154d8d9fb26 Bhawanpreet Lakha 2021-01-19 871 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 872
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 873 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 874 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 875
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 876 return true;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 877 }
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 878 }
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 879
48e48e59847821 Zhan Liu 2020-08-28 880 /* No applicable optimizations */
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 881 return false;
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 882 }
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 883
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 884 /* Disable MALL */
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 885 memset(&cmd, 0, sizeof(cmd));
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 886 cmd.mall.header.type = DMUB_CMD__MALL;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 887 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 888 cmd.mall.header.payload_bytes =
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 889 sizeof(cmd.mall) - sizeof(cmd.mall.header);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 890
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 891 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 892 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 893 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
52f2e83e2fe559 Bhawanpreet Lakha 2020-05-29 894
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 895 return true;
d99f13878d6f9c Bhawanpreet Lakha 2020-05-21 896 }
3e19095534caec Joshua Aberback 2020-04-29 897
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-12-17 7:25 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-16 9:28 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 749) kernel test robot
2021-12-17 7:25 ` Dan Carpenter
2021-12-17 7:25 ` Dan Carpenter
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