[RESEND PATCH] imx: Enable ACTLR.SMP in SPL for i.MX6

[RESEND PATCH] imx: Enable ACTLR.SMP in SPL for i.MX6

[Sven Schwermer]

Similar to what has been done before with c5437e5b for u-boot proper, we
enable the SMP bit for SPL as well. This is necessary when SDP booting
straight into Linux, i.e. falcon boot. When SDP boot mode is active, the
ROM code does not set this bit which makes the caches not work once
activated in Linux.

Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
---

 arch/arm/include/asm/mach-imx/sys_proto.h | 5 +++++
 arch/arm/mach-imx/cache.c                 | 2 +-
 arch/arm/mach-imx/mx6/soc.c               | 3 +++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 444834995e..b12cbdf60e 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -236,4 +236,9 @@ unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
 				unsigned long reg3);
 
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7)
+void enable_ca7_smp(void);
+#endif
+
 #endif
diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
index 4e3b49a3fd..ab9b621a2a 100644
--- a/arch/arm/mach-imx/cache.c
+++ b/arch/arm/mach-imx/cache.c
@@ -11,7 +11,7 @@
 #include <asm/io.h>
 #include <asm/mach-imx/sys_proto.h>
 
-static void enable_ca7_smp(void)
+void enable_ca7_smp(void)
 {
 	u32 val;
 
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index aacfc854a2..41f1a6e64e 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -487,6 +487,9 @@ int arch_cpu_init(void)
 	if (is_mx6dqp())
 		noc_setup();
 #endif
+
+	enable_ca7_smp();
+
 	return 0;
 }
 
-- 
2.34.1

Re: [RESEND PATCH] imx: Enable ACTLR.SMP in SPL for i.MX6

[Fabio Estevam]

Hi Sven,

Thanks for your patch.

On Sat, Jan 1, 2022 at 3:47 PM Sven Schwermer <sven@svenschwermer.de> wrote:
>
> Similar to what has been done before with c5437e5b for u-boot proper, we
> enable the SMP bit for SPL as well. This is necessary when SDP booting
> straight into Linux, i.e. falcon boot. When SDP boot mode is active, the
> ROM code does not set this bit which makes the caches not work once
> activated in Linux.

I suggest adding the data about the boot time difference that you
noticed when booting
FIT image via SPL in falcon mode versus U-Boot proper (1.2s versus 5s).

> Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
> ---
>
>  arch/arm/include/asm/mach-imx/sys_proto.h | 5 +++++
>  arch/arm/mach-imx/cache.c                 | 2 +-
>  arch/arm/mach-imx/mx6/soc.c               | 3 +++
>  3 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
> index 444834995e..b12cbdf60e 100644
> --- a/arch/arm/include/asm/mach-imx/sys_proto.h
> +++ b/arch/arm/include/asm/mach-imx/sys_proto.h
> @@ -236,4 +236,9 @@ unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
>                                 unsigned long reg3);
>
>  void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
> +
> +#if defined(CONFIG_MX6) || defined(CONFIG_MX7)

Please add || defined(CONFIG_MX7ULP) too.

> +void enable_ca7_smp(void);
> +#endif
> +
>  #endif
> diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
> index 4e3b49a3fd..ab9b621a2a 100644
> --- a/arch/arm/mach-imx/cache.c
> +++ b/arch/arm/mach-imx/cache.c
> @@ -11,7 +11,7 @@
>  #include <asm/io.h>
>  #include <asm/mach-imx/sys_proto.h>
>
> -static void enable_ca7_smp(void)
> +void enable_ca7_smp(void)
>  {
>         u32 val;
>
> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
> index aacfc854a2..41f1a6e64e 100644
> --- a/arch/arm/mach-imx/mx6/soc.c
> +++ b/arch/arm/mach-imx/mx6/soc.c
> @@ -487,6 +487,9 @@ int arch_cpu_init(void)
>         if (is_mx6dqp())
>                 noc_setup();
>  #endif
> +
> +       enable_ca7_smp();
> +

Since this affects all i.MX Cortex-A7 devices, please also add
enable_ca7_smp() in:
arch/arm/mach-imx/mx7/soc.c
arch/arm/mach-imx/mx7ulp/soc.c

Thanks