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From: Weiwei Li <liweiwei@iscas.ac.cn>
To: anup@brainfault.org, palmer@dabbelt.com,
	alistair.francis@wdc.com, bin.meng@windriver.com,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, Weiwei Li <liweiwei@iscas.ac.cn>,
	lazyparser@gmail.com
Subject: [PATCH v4 1/4] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
Date: Sun, 16 Jan 2022 10:59:22 +0800	[thread overview]
Message-ID: <20220116025925.29973-2-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20220116025925.29973-1-liweiwei@iscas.ac.cn>

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 target/riscv/cpu_helper.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 434a83e66a..d84cde424d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -626,6 +626,9 @@ restart:
             return TRANSLATE_FAIL;
         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
             /* Inner PTE, continue walking */
+            if (pte & (PTE_D | PTE_A | PTE_U)) {
+                return TRANSLATE_FAIL;
+            }
             base = ppn << PGSHIFT;
         } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
             /* Reserved leaf PTE flags: PTE_W */
-- 
2.17.1



WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn>
To: anup@brainfault.org, palmer@dabbelt.com,
	alistair.francis@wdc.com, bin.meng@windriver.com,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
	Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH v4 1/4] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
Date: Sun, 16 Jan 2022 10:59:22 +0800	[thread overview]
Message-ID: <20220116025925.29973-2-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20220116025925.29973-1-liweiwei@iscas.ac.cn>

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 target/riscv/cpu_helper.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 434a83e66a..d84cde424d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -626,6 +626,9 @@ restart:
             return TRANSLATE_FAIL;
         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
             /* Inner PTE, continue walking */
+            if (pte & (PTE_D | PTE_A | PTE_U)) {
+                return TRANSLATE_FAIL;
+            }
             base = ppn << PGSHIFT;
         } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
             /* Reserved leaf PTE flags: PTE_W */
-- 
2.17.1



  reply	other threads:[~2022-01-16  3:03 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-16  2:59 [PATCH v4 0/4] support subsets of virtual memory extension Weiwei Li
2022-01-16  2:59 ` Weiwei Li
2022-01-16  2:59 ` Weiwei Li [this message]
2022-01-16  2:59   ` [PATCH v4 1/4] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Weiwei Li
2022-01-16  2:59 ` [PATCH v4 2/4] target/riscv: add support for svnapot extension Weiwei Li
2022-01-16  2:59   ` Weiwei Li
2022-01-16  4:29   ` Anup Patel
2022-01-16  4:29     ` Anup Patel
2022-01-16  2:59 ` [PATCH v4 3/4] target/riscv: add support for svinval extension Weiwei Li
2022-01-16  2:59   ` Weiwei Li
2022-01-16  2:59 ` [PATCH v4 4/4] target/riscv: add support for svpbmt extension Weiwei Li
2022-01-16  2:59   ` Weiwei Li
2022-01-17  7:18   ` Guo Ren
2022-01-17  7:18     ` Guo Ren
2022-01-17  8:28     ` Weiwei Li
2022-01-17  8:28       ` Weiwei Li

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