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From: Sascha Hauer <s.hauer@pengutronix.de>
To: dri-devel@lists.freedesktop.org
Cc: linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
	kernel@pengutronix.de, "Andy Yan" <andy.yan@rock-chips.com>,
	"Benjamin Gaignard" <benjamin.gaignard@collabora.com>,
	"Michael Riesch" <michael.riesch@wolfvision.net>,
	"Sandy Huang" <hjc@rock-chips.com>,
	"Heiko Stübner" <heiko@sntech.de>,
	"Peter Geis" <pgwipeout@gmail.com>,
	"Douglas Anderson" <dianders@chromium.org>,
	"Yakir Yang" <ykk@rock-chips.com>,
	marcheu@chromium.org
Subject: [PATCH 07/27] drm/rockchip: dw_hdmi: Use auto-generated tables
Date: Wed, 26 Jan 2022 15:55:29 +0100	[thread overview]
Message-ID: <20220126145549.617165-8-s.hauer@pengutronix.de> (raw)
In-Reply-To: <20220126145549.617165-1-s.hauer@pengutronix.de>

From: Douglas Anderson <dianders at chromium.org>

The previous tables for mpll_cfg and curr_ctrl were created using the
20-pages of example settings provided by the PHY vendor.  Those
example settings weren't particularly dense, so there were places
where we were guessing what the settings would be for 10-bit and
12-bit (not that we use those anyway).  It was also always a lot of
extra work every time we wanted to add a new clock rate since we had
to cross-reference several tables.

In <http://crosreview.com/285855> I've gone through the work to figure
out how to generate this table automatically.  Let's now use the
automatically generated table and then we'll never need to look at it
again.

We only support 8-bit mode right now and only support a small number
of clock rates and and I've verified that the only 8-bit rate that was
affected was 148.5.  That mode appears to have been wrong in the old
table.

Changes since v3:
- new patch

Signed-off-by: Douglas Anderson <dianders at chromium.org>
Signed-off-by: Yakir Yang <ykk at rock-chips.com>
Reviewed-by: Stéphane Marchesin <marcheu at chromium.org>
---
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 130 +++++++++++---------
 1 file changed, 69 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index b9928e622adf..160107b333ef 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -87,80 +87,88 @@ struct rockchip_hdmi {
 
 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
 	{
-		27000000, {
-			{ 0x00b3, 0x0000},
-			{ 0x2153, 0x0000},
-			{ 0x40f3, 0x0000}
+		30666000, {
+			{ 0x00b3, 0x0000 },
+			{ 0x2153, 0x0000 },
+			{ 0x40f3, 0x0000 },
 		},
-	}, {
-		36000000, {
-			{ 0x00b3, 0x0000},
-			{ 0x2153, 0x0000},
-			{ 0x40f3, 0x0000}
+	},  {
+		36800000, {
+			{ 0x00b3, 0x0000 },
+			{ 0x2153, 0x0000 },
+			{ 0x40a2, 0x0001 },
 		},
-	}, {
-		40000000, {
-			{ 0x00b3, 0x0000},
-			{ 0x2153, 0x0000},
-			{ 0x40f3, 0x0000}
+	},  {
+		46000000, {
+			{ 0x00b3, 0x0000 },
+			{ 0x2142, 0x0001 },
+			{ 0x40a2, 0x0001 },
 		},
-	}, {
-		54000000, {
-			{ 0x0072, 0x0001},
-			{ 0x2142, 0x0001},
-			{ 0x40a2, 0x0001},
+	},  {
+		61333000, {
+			{ 0x0072, 0x0001 },
+			{ 0x2142, 0x0001 },
+			{ 0x40a2, 0x0001 },
 		},
-	}, {
-		65000000, {
-			{ 0x0072, 0x0001},
-			{ 0x2142, 0x0001},
-			{ 0x40a2, 0x0001},
+	},  {
+		73600000, {
+			{ 0x0072, 0x0001 },
+			{ 0x2142, 0x0001 },
+			{ 0x4061, 0x0002 },
 		},
-	}, {
-		66000000, {
-			{ 0x013e, 0x0003},
-			{ 0x217e, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		92000000, {
+			{ 0x0072, 0x0001 },
+			{ 0x2145, 0x0002 },
+			{ 0x4061, 0x0002 },
 		},
-	}, {
-		74250000, {
-			{ 0x0072, 0x0001},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		122666000, {
+			{ 0x0051, 0x0002 },
+			{ 0x2145, 0x0002 },
+			{ 0x4061, 0x0002 },
 		},
-	}, {
-		83500000, {
-			{ 0x0072, 0x0001},
+	},  {
+		147200000, {
+			{ 0x0051, 0x0002 },
+			{ 0x2145, 0x0002 },
+			{ 0x4064, 0x0003 },
 		},
-	}, {
-		108000000, {
-			{ 0x0051, 0x0002},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		184000000, {
+			{ 0x0051, 0x0002 },
+			{ 0x214c, 0x0003 },
+			{ 0x4064, 0x0003 },
 		},
-	}, {
-		106500000, {
-			{ 0x0051, 0x0002},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		226666000, {
+			{ 0x0040, 0x0003 },
+			{ 0x214c, 0x0003 },
+			{ 0x4064, 0x0003 },
 		},
-	}, {
-		146250000, {
-			{ 0x0051, 0x0002},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		272000000, {
+			{ 0x0040, 0x0003 },
+			{ 0x214c, 0x0003 },
+			{ 0x5a64, 0x0003 },
 		},
-	}, {
-		148500000, {
-			{ 0x0051, 0x0003},
-			{ 0x214c, 0x0003},
-			{ 0x4064, 0x0003}
+	},  {
+		340000000, {
+			{ 0x0040, 0x0003 },
+			{ 0x3b4c, 0x0003 },
+			{ 0x5a64, 0x0003 },
 		},
-	}, {
+	},  {
+		600000000, {
+			{ 0x1a40, 0x0003 },
+			{ 0x3b4c, 0x0003 },
+			{ 0x5a64, 0x0003 },
+		},
+	},  {
 		~0UL, {
-			{ 0x00a0, 0x000a },
-			{ 0x2001, 0x000f },
-			{ 0x4002, 0x000f },
+			{ 0x0000, 0x0000 },
+			{ 0x0000, 0x0000 },
+			{ 0x0000, 0x0000 },
 		},
 	}
 };
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: Sascha Hauer <s.hauer@pengutronix.de>
To: dri-devel@lists.freedesktop.org
Cc: devicetree@vger.kernel.org,
	Benjamin Gaignard <benjamin.gaignard@collabora.com>,
	Peter Geis <pgwipeout@gmail.com>,
	Sandy Huang <hjc@rock-chips.com>,
	marcheu@chromium.org, Douglas Anderson <dianders@chromium.org>,
	linux-rockchip@lists.infradead.org,
	Michael Riesch <michael.riesch@wolfvision.net>,
	kernel@pengutronix.de, Yakir Yang <ykk@rock-chips.com>,
	Andy Yan <andy.yan@rock-chips.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 07/27] drm/rockchip: dw_hdmi: Use auto-generated tables
Date: Wed, 26 Jan 2022 15:55:29 +0100	[thread overview]
Message-ID: <20220126145549.617165-8-s.hauer@pengutronix.de> (raw)
In-Reply-To: <20220126145549.617165-1-s.hauer@pengutronix.de>

From: Douglas Anderson <dianders at chromium.org>

The previous tables for mpll_cfg and curr_ctrl were created using the
20-pages of example settings provided by the PHY vendor.  Those
example settings weren't particularly dense, so there were places
where we were guessing what the settings would be for 10-bit and
12-bit (not that we use those anyway).  It was also always a lot of
extra work every time we wanted to add a new clock rate since we had
to cross-reference several tables.

In <http://crosreview.com/285855> I've gone through the work to figure
out how to generate this table automatically.  Let's now use the
automatically generated table and then we'll never need to look at it
again.

We only support 8-bit mode right now and only support a small number
of clock rates and and I've verified that the only 8-bit rate that was
affected was 148.5.  That mode appears to have been wrong in the old
table.

Changes since v3:
- new patch

Signed-off-by: Douglas Anderson <dianders at chromium.org>
Signed-off-by: Yakir Yang <ykk at rock-chips.com>
Reviewed-by: Stéphane Marchesin <marcheu at chromium.org>
---
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 130 +++++++++++---------
 1 file changed, 69 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index b9928e622adf..160107b333ef 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -87,80 +87,88 @@ struct rockchip_hdmi {
 
 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
 	{
-		27000000, {
-			{ 0x00b3, 0x0000},
-			{ 0x2153, 0x0000},
-			{ 0x40f3, 0x0000}
+		30666000, {
+			{ 0x00b3, 0x0000 },
+			{ 0x2153, 0x0000 },
+			{ 0x40f3, 0x0000 },
 		},
-	}, {
-		36000000, {
-			{ 0x00b3, 0x0000},
-			{ 0x2153, 0x0000},
-			{ 0x40f3, 0x0000}
+	},  {
+		36800000, {
+			{ 0x00b3, 0x0000 },
+			{ 0x2153, 0x0000 },
+			{ 0x40a2, 0x0001 },
 		},
-	}, {
-		40000000, {
-			{ 0x00b3, 0x0000},
-			{ 0x2153, 0x0000},
-			{ 0x40f3, 0x0000}
+	},  {
+		46000000, {
+			{ 0x00b3, 0x0000 },
+			{ 0x2142, 0x0001 },
+			{ 0x40a2, 0x0001 },
 		},
-	}, {
-		54000000, {
-			{ 0x0072, 0x0001},
-			{ 0x2142, 0x0001},
-			{ 0x40a2, 0x0001},
+	},  {
+		61333000, {
+			{ 0x0072, 0x0001 },
+			{ 0x2142, 0x0001 },
+			{ 0x40a2, 0x0001 },
 		},
-	}, {
-		65000000, {
-			{ 0x0072, 0x0001},
-			{ 0x2142, 0x0001},
-			{ 0x40a2, 0x0001},
+	},  {
+		73600000, {
+			{ 0x0072, 0x0001 },
+			{ 0x2142, 0x0001 },
+			{ 0x4061, 0x0002 },
 		},
-	}, {
-		66000000, {
-			{ 0x013e, 0x0003},
-			{ 0x217e, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		92000000, {
+			{ 0x0072, 0x0001 },
+			{ 0x2145, 0x0002 },
+			{ 0x4061, 0x0002 },
 		},
-	}, {
-		74250000, {
-			{ 0x0072, 0x0001},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		122666000, {
+			{ 0x0051, 0x0002 },
+			{ 0x2145, 0x0002 },
+			{ 0x4061, 0x0002 },
 		},
-	}, {
-		83500000, {
-			{ 0x0072, 0x0001},
+	},  {
+		147200000, {
+			{ 0x0051, 0x0002 },
+			{ 0x2145, 0x0002 },
+			{ 0x4064, 0x0003 },
 		},
-	}, {
-		108000000, {
-			{ 0x0051, 0x0002},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		184000000, {
+			{ 0x0051, 0x0002 },
+			{ 0x214c, 0x0003 },
+			{ 0x4064, 0x0003 },
 		},
-	}, {
-		106500000, {
-			{ 0x0051, 0x0002},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		226666000, {
+			{ 0x0040, 0x0003 },
+			{ 0x214c, 0x0003 },
+			{ 0x4064, 0x0003 },
 		},
-	}, {
-		146250000, {
-			{ 0x0051, 0x0002},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		272000000, {
+			{ 0x0040, 0x0003 },
+			{ 0x214c, 0x0003 },
+			{ 0x5a64, 0x0003 },
 		},
-	}, {
-		148500000, {
-			{ 0x0051, 0x0003},
-			{ 0x214c, 0x0003},
-			{ 0x4064, 0x0003}
+	},  {
+		340000000, {
+			{ 0x0040, 0x0003 },
+			{ 0x3b4c, 0x0003 },
+			{ 0x5a64, 0x0003 },
 		},
-	}, {
+	},  {
+		600000000, {
+			{ 0x1a40, 0x0003 },
+			{ 0x3b4c, 0x0003 },
+			{ 0x5a64, 0x0003 },
+		},
+	},  {
 		~0UL, {
-			{ 0x00a0, 0x000a },
-			{ 0x2001, 0x000f },
-			{ 0x4002, 0x000f },
+			{ 0x0000, 0x0000 },
+			{ 0x0000, 0x0000 },
+			{ 0x0000, 0x0000 },
 		},
 	}
 };
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: Sascha Hauer <s.hauer@pengutronix.de>
To: dri-devel@lists.freedesktop.org
Cc: linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
	kernel@pengutronix.de, "Andy Yan" <andy.yan@rock-chips.com>,
	"Benjamin Gaignard" <benjamin.gaignard@collabora.com>,
	"Michael Riesch" <michael.riesch@wolfvision.net>,
	"Sandy Huang" <hjc@rock-chips.com>,
	"Heiko Stübner" <heiko@sntech.de>,
	"Peter Geis" <pgwipeout@gmail.com>,
	"Douglas Anderson" <dianders@chromium.org>,
	"Yakir Yang" <ykk@rock-chips.com>,
	marcheu@chromium.org
Subject: [PATCH 07/27] drm/rockchip: dw_hdmi: Use auto-generated tables
Date: Wed, 26 Jan 2022 15:55:29 +0100	[thread overview]
Message-ID: <20220126145549.617165-8-s.hauer@pengutronix.de> (raw)
In-Reply-To: <20220126145549.617165-1-s.hauer@pengutronix.de>

From: Douglas Anderson <dianders at chromium.org>

The previous tables for mpll_cfg and curr_ctrl were created using the
20-pages of example settings provided by the PHY vendor.  Those
example settings weren't particularly dense, so there were places
where we were guessing what the settings would be for 10-bit and
12-bit (not that we use those anyway).  It was also always a lot of
extra work every time we wanted to add a new clock rate since we had
to cross-reference several tables.

In <http://crosreview.com/285855> I've gone through the work to figure
out how to generate this table automatically.  Let's now use the
automatically generated table and then we'll never need to look at it
again.

We only support 8-bit mode right now and only support a small number
of clock rates and and I've verified that the only 8-bit rate that was
affected was 148.5.  That mode appears to have been wrong in the old
table.

Changes since v3:
- new patch

Signed-off-by: Douglas Anderson <dianders at chromium.org>
Signed-off-by: Yakir Yang <ykk at rock-chips.com>
Reviewed-by: Stéphane Marchesin <marcheu at chromium.org>
---
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 130 +++++++++++---------
 1 file changed, 69 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index b9928e622adf..160107b333ef 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -87,80 +87,88 @@ struct rockchip_hdmi {
 
 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
 	{
-		27000000, {
-			{ 0x00b3, 0x0000},
-			{ 0x2153, 0x0000},
-			{ 0x40f3, 0x0000}
+		30666000, {
+			{ 0x00b3, 0x0000 },
+			{ 0x2153, 0x0000 },
+			{ 0x40f3, 0x0000 },
 		},
-	}, {
-		36000000, {
-			{ 0x00b3, 0x0000},
-			{ 0x2153, 0x0000},
-			{ 0x40f3, 0x0000}
+	},  {
+		36800000, {
+			{ 0x00b3, 0x0000 },
+			{ 0x2153, 0x0000 },
+			{ 0x40a2, 0x0001 },
 		},
-	}, {
-		40000000, {
-			{ 0x00b3, 0x0000},
-			{ 0x2153, 0x0000},
-			{ 0x40f3, 0x0000}
+	},  {
+		46000000, {
+			{ 0x00b3, 0x0000 },
+			{ 0x2142, 0x0001 },
+			{ 0x40a2, 0x0001 },
 		},
-	}, {
-		54000000, {
-			{ 0x0072, 0x0001},
-			{ 0x2142, 0x0001},
-			{ 0x40a2, 0x0001},
+	},  {
+		61333000, {
+			{ 0x0072, 0x0001 },
+			{ 0x2142, 0x0001 },
+			{ 0x40a2, 0x0001 },
 		},
-	}, {
-		65000000, {
-			{ 0x0072, 0x0001},
-			{ 0x2142, 0x0001},
-			{ 0x40a2, 0x0001},
+	},  {
+		73600000, {
+			{ 0x0072, 0x0001 },
+			{ 0x2142, 0x0001 },
+			{ 0x4061, 0x0002 },
 		},
-	}, {
-		66000000, {
-			{ 0x013e, 0x0003},
-			{ 0x217e, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		92000000, {
+			{ 0x0072, 0x0001 },
+			{ 0x2145, 0x0002 },
+			{ 0x4061, 0x0002 },
 		},
-	}, {
-		74250000, {
-			{ 0x0072, 0x0001},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		122666000, {
+			{ 0x0051, 0x0002 },
+			{ 0x2145, 0x0002 },
+			{ 0x4061, 0x0002 },
 		},
-	}, {
-		83500000, {
-			{ 0x0072, 0x0001},
+	},  {
+		147200000, {
+			{ 0x0051, 0x0002 },
+			{ 0x2145, 0x0002 },
+			{ 0x4064, 0x0003 },
 		},
-	}, {
-		108000000, {
-			{ 0x0051, 0x0002},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		184000000, {
+			{ 0x0051, 0x0002 },
+			{ 0x214c, 0x0003 },
+			{ 0x4064, 0x0003 },
 		},
-	}, {
-		106500000, {
-			{ 0x0051, 0x0002},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		226666000, {
+			{ 0x0040, 0x0003 },
+			{ 0x214c, 0x0003 },
+			{ 0x4064, 0x0003 },
 		},
-	}, {
-		146250000, {
-			{ 0x0051, 0x0002},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		272000000, {
+			{ 0x0040, 0x0003 },
+			{ 0x214c, 0x0003 },
+			{ 0x5a64, 0x0003 },
 		},
-	}, {
-		148500000, {
-			{ 0x0051, 0x0003},
-			{ 0x214c, 0x0003},
-			{ 0x4064, 0x0003}
+	},  {
+		340000000, {
+			{ 0x0040, 0x0003 },
+			{ 0x3b4c, 0x0003 },
+			{ 0x5a64, 0x0003 },
 		},
-	}, {
+	},  {
+		600000000, {
+			{ 0x1a40, 0x0003 },
+			{ 0x3b4c, 0x0003 },
+			{ 0x5a64, 0x0003 },
+		},
+	},  {
 		~0UL, {
-			{ 0x00a0, 0x000a },
-			{ 0x2001, 0x000f },
-			{ 0x4002, 0x000f },
+			{ 0x0000, 0x0000 },
+			{ 0x0000, 0x0000 },
+			{ 0x0000, 0x0000 },
 		},
 	}
 };
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Sascha Hauer <s.hauer@pengutronix.de>
To: dri-devel@lists.freedesktop.org
Cc: linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
	kernel@pengutronix.de, "Andy Yan" <andy.yan@rock-chips.com>,
	"Benjamin Gaignard" <benjamin.gaignard@collabora.com>,
	"Michael Riesch" <michael.riesch@wolfvision.net>,
	"Sandy Huang" <hjc@rock-chips.com>,
	"Heiko Stübner" <heiko@sntech.de>,
	"Peter Geis" <pgwipeout@gmail.com>,
	"Douglas Anderson" <dianders@chromium.org>,
	"Yakir Yang" <ykk@rock-chips.com>,
	marcheu@chromium.org
Subject: [PATCH 07/27] drm/rockchip: dw_hdmi: Use auto-generated tables
Date: Wed, 26 Jan 2022 15:55:29 +0100	[thread overview]
Message-ID: <20220126145549.617165-8-s.hauer@pengutronix.de> (raw)
In-Reply-To: <20220126145549.617165-1-s.hauer@pengutronix.de>

From: Douglas Anderson <dianders at chromium.org>

The previous tables for mpll_cfg and curr_ctrl were created using the
20-pages of example settings provided by the PHY vendor.  Those
example settings weren't particularly dense, so there were places
where we were guessing what the settings would be for 10-bit and
12-bit (not that we use those anyway).  It was also always a lot of
extra work every time we wanted to add a new clock rate since we had
to cross-reference several tables.

In <http://crosreview.com/285855> I've gone through the work to figure
out how to generate this table automatically.  Let's now use the
automatically generated table and then we'll never need to look at it
again.

We only support 8-bit mode right now and only support a small number
of clock rates and and I've verified that the only 8-bit rate that was
affected was 148.5.  That mode appears to have been wrong in the old
table.

Changes since v3:
- new patch

Signed-off-by: Douglas Anderson <dianders at chromium.org>
Signed-off-by: Yakir Yang <ykk at rock-chips.com>
Reviewed-by: Stéphane Marchesin <marcheu at chromium.org>
---
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 130 +++++++++++---------
 1 file changed, 69 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index b9928e622adf..160107b333ef 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -87,80 +87,88 @@ struct rockchip_hdmi {
 
 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
 	{
-		27000000, {
-			{ 0x00b3, 0x0000},
-			{ 0x2153, 0x0000},
-			{ 0x40f3, 0x0000}
+		30666000, {
+			{ 0x00b3, 0x0000 },
+			{ 0x2153, 0x0000 },
+			{ 0x40f3, 0x0000 },
 		},
-	}, {
-		36000000, {
-			{ 0x00b3, 0x0000},
-			{ 0x2153, 0x0000},
-			{ 0x40f3, 0x0000}
+	},  {
+		36800000, {
+			{ 0x00b3, 0x0000 },
+			{ 0x2153, 0x0000 },
+			{ 0x40a2, 0x0001 },
 		},
-	}, {
-		40000000, {
-			{ 0x00b3, 0x0000},
-			{ 0x2153, 0x0000},
-			{ 0x40f3, 0x0000}
+	},  {
+		46000000, {
+			{ 0x00b3, 0x0000 },
+			{ 0x2142, 0x0001 },
+			{ 0x40a2, 0x0001 },
 		},
-	}, {
-		54000000, {
-			{ 0x0072, 0x0001},
-			{ 0x2142, 0x0001},
-			{ 0x40a2, 0x0001},
+	},  {
+		61333000, {
+			{ 0x0072, 0x0001 },
+			{ 0x2142, 0x0001 },
+			{ 0x40a2, 0x0001 },
 		},
-	}, {
-		65000000, {
-			{ 0x0072, 0x0001},
-			{ 0x2142, 0x0001},
-			{ 0x40a2, 0x0001},
+	},  {
+		73600000, {
+			{ 0x0072, 0x0001 },
+			{ 0x2142, 0x0001 },
+			{ 0x4061, 0x0002 },
 		},
-	}, {
-		66000000, {
-			{ 0x013e, 0x0003},
-			{ 0x217e, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		92000000, {
+			{ 0x0072, 0x0001 },
+			{ 0x2145, 0x0002 },
+			{ 0x4061, 0x0002 },
 		},
-	}, {
-		74250000, {
-			{ 0x0072, 0x0001},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		122666000, {
+			{ 0x0051, 0x0002 },
+			{ 0x2145, 0x0002 },
+			{ 0x4061, 0x0002 },
 		},
-	}, {
-		83500000, {
-			{ 0x0072, 0x0001},
+	},  {
+		147200000, {
+			{ 0x0051, 0x0002 },
+			{ 0x2145, 0x0002 },
+			{ 0x4064, 0x0003 },
 		},
-	}, {
-		108000000, {
-			{ 0x0051, 0x0002},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		184000000, {
+			{ 0x0051, 0x0002 },
+			{ 0x214c, 0x0003 },
+			{ 0x4064, 0x0003 },
 		},
-	}, {
-		106500000, {
-			{ 0x0051, 0x0002},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		226666000, {
+			{ 0x0040, 0x0003 },
+			{ 0x214c, 0x0003 },
+			{ 0x4064, 0x0003 },
 		},
-	}, {
-		146250000, {
-			{ 0x0051, 0x0002},
-			{ 0x2145, 0x0002},
-			{ 0x4061, 0x0002}
+	},  {
+		272000000, {
+			{ 0x0040, 0x0003 },
+			{ 0x214c, 0x0003 },
+			{ 0x5a64, 0x0003 },
 		},
-	}, {
-		148500000, {
-			{ 0x0051, 0x0003},
-			{ 0x214c, 0x0003},
-			{ 0x4064, 0x0003}
+	},  {
+		340000000, {
+			{ 0x0040, 0x0003 },
+			{ 0x3b4c, 0x0003 },
+			{ 0x5a64, 0x0003 },
 		},
-	}, {
+	},  {
+		600000000, {
+			{ 0x1a40, 0x0003 },
+			{ 0x3b4c, 0x0003 },
+			{ 0x5a64, 0x0003 },
+		},
+	},  {
 		~0UL, {
-			{ 0x00a0, 0x000a },
-			{ 0x2001, 0x000f },
-			{ 0x4002, 0x000f },
+			{ 0x0000, 0x0000 },
+			{ 0x0000, 0x0000 },
+			{ 0x0000, 0x0000 },
 		},
 	}
 };
-- 
2.30.2


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

  parent reply	other threads:[~2022-01-26 14:58 UTC|newest]

Thread overview: 221+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-26 14:55 [PATCH v4 00/27] drm/rockchip: RK356x VOP2 support Sascha Hauer
2022-01-26 14:55 ` Sascha Hauer
2022-01-26 14:55 ` Sascha Hauer
2022-01-26 14:55 ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 01/27] drm/encoder: Add of_graph port to struct drm_encoder Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 15:04   ` Aw: " Frank Wunderlich
2022-01-26 15:04     ` Frank Wunderlich
2022-01-26 15:04     ` Frank Wunderlich
2022-01-26 15:04     ` Frank Wunderlich
2022-01-26 14:55 ` [PATCH 02/27] drm/rockchip: dw_hdmi: Do not leave clock enabled in error case Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 03/27] drm/rockchip: dw_hdmi: rename vpll clock to reference clock Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 04/27] drm/rockchip: dw_hdmi: add rk3568 support Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 05/27] drm/rockchip: dw_hdmi: add regulator support Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 06/27] drm/rockchip: dw_hdmi: Add support for hclk Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` Sascha Hauer [this message]
2022-01-26 14:55   ` [PATCH 07/27] drm/rockchip: dw_hdmi: Use auto-generated tables Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 15:54   ` Doug Anderson
2022-01-26 15:54     ` Doug Anderson
2022-01-26 15:54     ` Doug Anderson
2022-01-26 15:54     ` Doug Anderson
2022-01-27 11:20     ` Sascha Hauer
2022-01-27 11:20       ` Sascha Hauer
2022-01-27 11:20       ` Sascha Hauer
2022-01-27 11:20       ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 08/27] drm/rockchip: dw_hdmi: drop mode_valid hook Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 09/27] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 15:42   ` Doug Anderson
2022-01-26 15:42     ` Doug Anderson
2022-01-26 15:42     ` Doug Anderson
2022-01-26 15:42     ` Doug Anderson
2022-01-27 11:06     ` Sascha Hauer
2022-01-27 11:06       ` Sascha Hauer
2022-01-27 11:06       ` Sascha Hauer
2022-01-27 11:06       ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 10/27] drm/rockchip: dw_hdmi: add default 594Mhz clk for 4K@60hz Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 11/27] clk: rockchip: rk3568: Add more PLL rates Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 12/27] dt-bindings: display: rockchip: dw-hdmi: Add compatible for rk3568 HDMI Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 13/27] dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-02-09  3:29   ` Rob Herring
2022-02-09  3:29     ` Rob Herring
2022-02-09  3:29     ` Rob Herring
2022-02-09  3:29     ` Rob Herring
2022-01-26 14:55 ` [PATCH 14/27] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-02-09  3:30   ` Rob Herring
2022-02-09  3:30     ` Rob Herring
2022-02-09  3:30     ` Rob Herring
2022-02-09  3:30     ` Rob Herring
2022-01-26 14:55 ` [PATCH 15/27] dt-bindings: display: rockchip: dw-hdmi: Add regulator support Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-02-09  3:30   ` Rob Herring
2022-02-09  3:30     ` Rob Herring
2022-02-09  3:30     ` Rob Herring
2022-02-09  3:30     ` Rob Herring
2022-01-26 14:55 ` [PATCH 16/27] dt-bindings: display: rockchip: dw-hdmi: Add additional clock Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-02-09  3:31   ` Rob Herring
2022-02-09  3:31     ` Rob Herring
2022-02-09  3:31     ` Rob Herring
2022-02-09  3:31     ` Rob Herring
2022-01-26 14:55 ` [PATCH 17/27] dt-bindings: display: rockchip: Add binding for VOP2 Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 22:10   ` Rob Herring
2022-01-26 22:10     ` Rob Herring
2022-01-26 22:10     ` Rob Herring
2022-01-26 22:10     ` Rob Herring
2022-02-01 17:22   ` Rob Herring
2022-02-01 17:22     ` Rob Herring
2022-02-01 17:22     ` Rob Herring
2022-02-01 17:22     ` Rob Herring
2022-01-26 14:55 ` [PATCH 18/27] arm64: dts: rockchip: rk3399: reorder hmdi clocks Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 19/27] arm64: dts: rockchip: rk3399: rename HDMI ref clock to 'ref' Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 20/27] arm64: dts: rockchip: rk356x: Add VOP2 nodes Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-02-09  3:32   ` Rob Herring
2022-02-09  3:32     ` Rob Herring
2022-02-09  3:32     ` Rob Herring
2022-02-09  3:32     ` Rob Herring
2022-01-26 14:55 ` [PATCH 21/27] arm64: dts: rockchip: rk356x: Add HDMI nodes Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 16:04   ` Peter Geis
2022-01-26 16:04     ` Peter Geis
2022-01-26 16:04     ` Peter Geis
2022-01-26 16:04     ` Peter Geis
2022-01-26 17:56     ` Robin Murphy
2022-01-26 17:56       ` Robin Murphy
2022-01-26 17:56       ` Robin Murphy
2022-01-26 17:56       ` Robin Murphy
2022-01-26 18:44       ` Peter Geis
2022-01-26 18:44         ` Peter Geis
2022-01-26 18:44         ` Peter Geis
2022-01-26 18:44         ` Peter Geis
2022-01-26 19:24         ` Robin Murphy
2022-01-26 19:24           ` Robin Murphy
2022-01-26 19:24           ` Robin Murphy
2022-01-26 19:24           ` Robin Murphy
2022-01-26 20:00           ` Peter Geis
2022-01-26 20:00             ` Peter Geis
2022-01-26 20:00             ` Peter Geis
2022-01-26 20:00             ` Peter Geis
2022-01-26 14:55 ` [PATCH 22/27] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 23/27] arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 24/27] clk: rk3568: drop CLK_SET_RATE_PARENT from dclk_vop* Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-29 17:48   ` Heiko Stübner
2022-01-29 17:48     ` Heiko Stübner
2022-01-29 17:48     ` Heiko Stübner
2022-01-29 17:48     ` Heiko Stübner
2022-01-31  8:10     ` Sascha Hauer
2022-01-31  8:10       ` Sascha Hauer
2022-01-31  8:10       ` Sascha Hauer
2022-01-31  8:10       ` Sascha Hauer
2022-02-08 11:41       ` Heiko Stübner
2022-02-08 11:41         ` Heiko Stübner
2022-02-08 11:41         ` Heiko Stübner
2022-02-08 11:41         ` Heiko Stübner
2022-01-26 14:55 ` [PATCH 25/27] clk: rk3568: Add CLK_SET_RATE_PARENT to the HDMI reference clock Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 26/27] drm/rockchip: Make VOP driver optional Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 27/27] drm: rockchip: Add VOP2 driver Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 14:55   ` Sascha Hauer
2022-01-26 17:10   ` Aw: " Frank Wunderlich
2022-01-26 17:10     ` Frank Wunderlich
2022-01-26 17:10     ` Frank Wunderlich
2022-01-26 17:10     ` Frank Wunderlich
2022-01-27  9:17   ` Piotr Oniszczuk
2022-01-27  9:17     ` Piotr Oniszczuk
2022-01-27  9:17     ` Piotr Oniszczuk
2022-01-27  9:17     ` Piotr Oniszczuk
2022-01-27 11:00     ` Sascha Hauer
2022-01-27 11:00       ` Sascha Hauer
2022-01-27 11:00       ` Sascha Hauer
2022-01-27 11:00       ` Sascha Hauer
2022-01-27 14:43       ` Piotr Oniszczuk
2022-01-27 14:43         ` Piotr Oniszczuk
2022-01-27 14:43         ` Piotr Oniszczuk
2022-01-27 14:43         ` Piotr Oniszczuk
     [not found]       ` <9d23b94a-c8db-6588-fadf-97ea5e748f8a@pscan.uk>
2022-01-28  9:19         ` MiPi DSI interface for RK3566 ? Sascha Hauer
2022-01-29 10:55   ` [PATCH 27/27] drm: rockchip: Add VOP2 driver kernel test robot
2022-01-27 14:16 ` [PATCH v4 00/27] drm/rockchip: RK356x VOP2 support Michael Riesch
2022-01-27 14:16   ` Michael Riesch
2022-01-27 14:16   ` Michael Riesch
2022-01-27 14:16   ` Michael Riesch
2022-02-08 11:57 ` (subset) " Heiko Stuebner
2022-02-08 11:57   ` Heiko Stuebner
2022-02-08 11:57   ` Heiko Stuebner
2022-02-08 11:57   ` Heiko Stuebner
2022-02-08 13:21 ` Heiko Stuebner
2022-02-08 13:21   ` Heiko Stuebner
2022-02-08 13:21   ` Heiko Stuebner
2022-02-08 13:21   ` Heiko Stuebner

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