* [PATCH V3 0/2] EDAC: synopsys: fix some bugs in v3.x Synopsys EDAC DDR driver
@ 2022-04-24 1:33 ` Sherry Sun
0 siblings, 0 replies; 6+ messages in thread
From: Sherry Sun @ 2022-04-24 1:33 UTC (permalink / raw)
To: michal.simek, bp, Shubhrajyoti.datta, mchehab, tony.luck,
james.morse, rric
Cc: linux-edac, linux-kernel, linux-arm-kernel, linux-imx
The two patches fix some issues for v3.x Synopsys EDAC DDR in synopsys_edac.c.
For the details, please check the patch commit log. This has been verified on
i.MX8MP platform.
Sherry Sun (2):
EDAC/synopsys: Disable the error interrupt on Synopsys EDAC v3.x
hardware
EDAC/synopsys: Re-enable the interrupts in intr_handler for v3.x
Synopsys EDAC DDR
drivers/edac/synopsys_edac.c | 44 ++++++++++++++++++++----------------
1 file changed, 25 insertions(+), 19 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V3 0/2] EDAC: synopsys: fix some bugs in v3.x Synopsys EDAC DDR driver
@ 2022-04-24 1:33 ` Sherry Sun
0 siblings, 0 replies; 6+ messages in thread
From: Sherry Sun @ 2022-04-24 1:33 UTC (permalink / raw)
To: michal.simek, bp, Shubhrajyoti.datta, mchehab, tony.luck,
james.morse, rric
Cc: linux-edac, linux-kernel, linux-arm-kernel, linux-imx
The two patches fix some issues for v3.x Synopsys EDAC DDR in synopsys_edac.c.
For the details, please check the patch commit log. This has been verified on
i.MX8MP platform.
Sherry Sun (2):
EDAC/synopsys: Disable the error interrupt on Synopsys EDAC v3.x
hardware
EDAC/synopsys: Re-enable the interrupts in intr_handler for v3.x
Synopsys EDAC DDR
drivers/edac/synopsys_edac.c | 44 ++++++++++++++++++++----------------
1 file changed, 25 insertions(+), 19 deletions(-)
--
2.17.1
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V3 1/2] EDAC/synopsys: Disable the error interrupt on Synopsys EDAC v3.x hardware
2022-04-24 1:33 ` Sherry Sun
@ 2022-04-24 1:33 ` Sherry Sun
-1 siblings, 0 replies; 6+ messages in thread
From: Sherry Sun @ 2022-04-24 1:33 UTC (permalink / raw)
To: michal.simek, bp, Shubhrajyoti.datta, mchehab, tony.luck,
james.morse, rric
Cc: linux-edac, linux-kernel, linux-arm-kernel, linux-imx
v3.x Synopsys EDAC DDR doesn't have the QOS Interrupt register, change
to use the ECC Clear Register to disable the error interrupts.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in V3:
1. Improve the patch title and commit message as Borislav suggested.
---
drivers/edac/synopsys_edac.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 40b1abeca856..88a481043d4c 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -865,8 +865,11 @@ static void enable_intr(struct synps_edac_priv *priv)
static void disable_intr(struct synps_edac_priv *priv)
{
/* Disable UE/CE Interrupts */
- writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
- priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+ if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+ writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+ else
+ writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+ priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
}
static int setup_irq(struct mem_ctl_info *mci,
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V3 1/2] EDAC/synopsys: Disable the error interrupt on Synopsys EDAC v3.x hardware
@ 2022-04-24 1:33 ` Sherry Sun
0 siblings, 0 replies; 6+ messages in thread
From: Sherry Sun @ 2022-04-24 1:33 UTC (permalink / raw)
To: michal.simek, bp, Shubhrajyoti.datta, mchehab, tony.luck,
james.morse, rric
Cc: linux-edac, linux-kernel, linux-arm-kernel, linux-imx
v3.x Synopsys EDAC DDR doesn't have the QOS Interrupt register, change
to use the ECC Clear Register to disable the error interrupts.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in V3:
1. Improve the patch title and commit message as Borislav suggested.
---
drivers/edac/synopsys_edac.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 40b1abeca856..88a481043d4c 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -865,8 +865,11 @@ static void enable_intr(struct synps_edac_priv *priv)
static void disable_intr(struct synps_edac_priv *priv)
{
/* Disable UE/CE Interrupts */
- writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
- priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+ if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+ writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+ else
+ writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+ priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
}
static int setup_irq(struct mem_ctl_info *mci,
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V3 2/2] EDAC/synopsys: Re-enable the interrupts in intr_handler for v3.x Synopsys EDAC DDR
2022-04-24 1:33 ` Sherry Sun
@ 2022-04-24 1:33 ` Sherry Sun
-1 siblings, 0 replies; 6+ messages in thread
From: Sherry Sun @ 2022-04-24 1:33 UTC (permalink / raw)
To: michal.simek, bp, Shubhrajyoti.datta, mchehab, tony.luck,
james.morse, rric
Cc: linux-edac, linux-kernel, linux-arm-kernel, linux-imx
zynqmp_get_error_info() writes 0 to the ECC_CLR_OFST register after an
interrupt for a {un-,}correctable error is raised, which disables the
error interrupts, then the interrupt handler will be called only once.
Therefore, re-enable the error interrupt line at the end of intr_handler
for v3.x Synopsys EDAC DDR.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in V3:
1. Improve the patch title and commit message as Borislav suggested.
2. Simply move {enable,disable}_intr() upwards instead of the enable_intr()
forward declaration.
---
drivers/edac/synopsys_edac.c | 47 +++++++++++++++++++-----------------
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 88a481043d4c..a14baeca6400 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -527,6 +527,28 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
memset(p, 0, sizeof(*p));
}
+static void enable_intr(struct synps_edac_priv *priv)
+{
+ /* Enable UE/CE Interrupts */
+ if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+ writel(DDR_UE_MASK | DDR_CE_MASK,
+ priv->baseaddr + ECC_CLR_OFST);
+ else
+ writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+ priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
+
+}
+
+static void disable_intr(struct synps_edac_priv *priv)
+{
+ /* Disable UE/CE Interrupts */
+ if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+ writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+ else
+ writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+ priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+}
+
/**
* intr_handler - Interrupt Handler for ECC interrupts.
* @irq: IRQ number.
@@ -568,6 +590,9 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
/* v3.0 of the controller does not have this register */
if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
+ else
+ enable_intr(priv);
+
return IRQ_HANDLED;
}
@@ -850,28 +875,6 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev)
init_csrows(mci);
}
-static void enable_intr(struct synps_edac_priv *priv)
-{
- /* Enable UE/CE Interrupts */
- if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
- writel(DDR_UE_MASK | DDR_CE_MASK,
- priv->baseaddr + ECC_CLR_OFST);
- else
- writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
- priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
-
-}
-
-static void disable_intr(struct synps_edac_priv *priv)
-{
- /* Disable UE/CE Interrupts */
- if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
- writel(0x0, priv->baseaddr + ECC_CLR_OFST);
- else
- writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
- priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
-}
-
static int setup_irq(struct mem_ctl_info *mci,
struct platform_device *pdev)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V3 2/2] EDAC/synopsys: Re-enable the interrupts in intr_handler for v3.x Synopsys EDAC DDR
@ 2022-04-24 1:33 ` Sherry Sun
0 siblings, 0 replies; 6+ messages in thread
From: Sherry Sun @ 2022-04-24 1:33 UTC (permalink / raw)
To: michal.simek, bp, Shubhrajyoti.datta, mchehab, tony.luck,
james.morse, rric
Cc: linux-edac, linux-kernel, linux-arm-kernel, linux-imx
zynqmp_get_error_info() writes 0 to the ECC_CLR_OFST register after an
interrupt for a {un-,}correctable error is raised, which disables the
error interrupts, then the interrupt handler will be called only once.
Therefore, re-enable the error interrupt line at the end of intr_handler
for v3.x Synopsys EDAC DDR.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in V3:
1. Improve the patch title and commit message as Borislav suggested.
2. Simply move {enable,disable}_intr() upwards instead of the enable_intr()
forward declaration.
---
drivers/edac/synopsys_edac.c | 47 +++++++++++++++++++-----------------
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 88a481043d4c..a14baeca6400 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -527,6 +527,28 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
memset(p, 0, sizeof(*p));
}
+static void enable_intr(struct synps_edac_priv *priv)
+{
+ /* Enable UE/CE Interrupts */
+ if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+ writel(DDR_UE_MASK | DDR_CE_MASK,
+ priv->baseaddr + ECC_CLR_OFST);
+ else
+ writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+ priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
+
+}
+
+static void disable_intr(struct synps_edac_priv *priv)
+{
+ /* Disable UE/CE Interrupts */
+ if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+ writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+ else
+ writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+ priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+}
+
/**
* intr_handler - Interrupt Handler for ECC interrupts.
* @irq: IRQ number.
@@ -568,6 +590,9 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
/* v3.0 of the controller does not have this register */
if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
+ else
+ enable_intr(priv);
+
return IRQ_HANDLED;
}
@@ -850,28 +875,6 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev)
init_csrows(mci);
}
-static void enable_intr(struct synps_edac_priv *priv)
-{
- /* Enable UE/CE Interrupts */
- if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
- writel(DDR_UE_MASK | DDR_CE_MASK,
- priv->baseaddr + ECC_CLR_OFST);
- else
- writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
- priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
-
-}
-
-static void disable_intr(struct synps_edac_priv *priv)
-{
- /* Disable UE/CE Interrupts */
- if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
- writel(0x0, priv->baseaddr + ECC_CLR_OFST);
- else
- writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
- priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
-}
-
static int setup_irq(struct mem_ctl_info *mci,
struct platform_device *pdev)
{
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-04-24 1:36 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-24 1:33 [PATCH V3 0/2] EDAC: synopsys: fix some bugs in v3.x Synopsys EDAC DDR driver Sherry Sun
2022-04-24 1:33 ` Sherry Sun
2022-04-24 1:33 ` [PATCH V3 1/2] EDAC/synopsys: Disable the error interrupt on Synopsys EDAC v3.x hardware Sherry Sun
2022-04-24 1:33 ` Sherry Sun
2022-04-24 1:33 ` [PATCH V3 2/2] EDAC/synopsys: Re-enable the interrupts in intr_handler for v3.x Synopsys EDAC DDR Sherry Sun
2022-04-24 1:33 ` Sherry Sun
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