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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 31/32] hw/arm/virt: Fix CPU's default NUMA node ID
Date: Mon,  9 May 2022 12:58:47 +0100	[thread overview]
Message-ID: <20220509115848.3521805-32-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org>

From: Gavin Shan <gshan@redhat.com>

When CPU-to-NUMA association isn't explicitly provided by users,
the default one is given by mc->get_default_cpu_node_id(). However,
the CPU topology isn't fully considered in the default association
and this causes CPU topology broken warnings on booting Linux guest.

For example, the following warning messages are observed when the
Linux guest is booted with the following command lines.

  /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
  -accel kvm -machine virt,gic-version=host               \
  -cpu host                                               \
  -smp 6,sockets=2,cores=3,threads=1                      \
  -m 1024M,slots=16,maxmem=64G                            \
  -object memory-backend-ram,id=mem0,size=128M            \
  -object memory-backend-ram,id=mem1,size=128M            \
  -object memory-backend-ram,id=mem2,size=128M            \
  -object memory-backend-ram,id=mem3,size=128M            \
  -object memory-backend-ram,id=mem4,size=128M            \
  -object memory-backend-ram,id=mem4,size=384M            \
  -numa node,nodeid=0,memdev=mem0                         \
  -numa node,nodeid=1,memdev=mem1                         \
  -numa node,nodeid=2,memdev=mem2                         \
  -numa node,nodeid=3,memdev=mem3                         \
  -numa node,nodeid=4,memdev=mem4                         \
  -numa node,nodeid=5,memdev=mem5
         :
  alternatives: patching kernel code
  BUG: arch topology borken
  the CLS domain not a subset of the MC domain
  <the above error log repeats>
  BUG: arch topology borken
  the DIE domain not a subset of the NODE domain

With current implementation of mc->get_default_cpu_node_id(),
CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
That's incorrect because CPU#0/1/2 should be associated with same
NUMA node because they're seated in same socket.

This fixes the issue by considering the socket ID when the default
CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
With this applied, no more CPU topology broken warnings are seen
from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
there are no CPUs associated with NODE#2/3/4/5.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-6-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index c25023a083a..1a45f44435e 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2554,7 +2554,9 @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
 
 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
 {
-    return idx % ms->numa_state->num_nodes;
+    int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
+
+    return socket_id % ms->numa_state->num_nodes;
 }
 
 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
-- 
2.25.1



  parent reply	other threads:[~2022-05-09 12:24 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-09 11:58 [PULL 00/32] target-arm queue Peter Maydell
2022-05-09 11:58 ` [PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm Peter Maydell
2022-05-09 11:58 ` [PULL 02/32] target/arm: Handle cpreg registration for missing EL Peter Maydell
2022-05-09 11:58 ` [PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks Peter Maydell
2022-05-09 11:58 ` [PULL 04/32] target/arm: Merge zcr reginfo Peter Maydell
2022-05-09 11:58 ` [PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2 Peter Maydell
2022-05-09 11:58 ` [PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c Peter Maydell
2022-05-09 11:58 ` [PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Peter Maydell
2022-05-09 11:58 ` [PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Peter Maydell
2022-05-09 11:58 ` [PULL 09/32] target/arm: Split out aa32_max_features Peter Maydell
2022-05-09 11:58 ` [PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers Peter Maydell
2022-05-09 11:58 ` [PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes Peter Maydell
2022-05-09 11:58 ` [PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max Peter Maydell
2022-05-09 11:58 ` [PULL 13/32] target/arm: Enable FEAT_Debugv8p4 " Peter Maydell
2022-05-09 11:58 ` [PULL 14/32] target/arm: Add minimal RAS registers Peter Maydell
2022-05-09 11:58 ` [PULL 15/32] target/arm: Enable SCR and HCR bits for RAS Peter Maydell
2022-05-09 11:58 ` [PULL 16/32] target/arm: Implement virtual SError exceptions Peter Maydell
2022-05-09 11:58 ` [PULL 17/32] target/arm: Implement ESB instruction Peter Maydell
2022-05-09 11:58 ` [PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max Peter Maydell
2022-05-09 11:58 ` [PULL 19/32] target/arm: Enable FEAT_IESB " Peter Maydell
2022-05-09 11:58 ` [PULL 20/32] target/arm: Enable FEAT_CSV2 " Peter Maydell
2022-05-09 11:58 ` [PULL 21/32] target/arm: Enable FEAT_CSV2_2 " Peter Maydell
2022-05-09 11:58 ` [PULL 22/32] target/arm: Enable FEAT_CSV3 " Peter Maydell
2022-05-09 11:58 ` [PULL 23/32] target/arm: Enable FEAT_DGH " Peter Maydell
2022-05-09 11:58 ` [PULL 24/32] target/arm: Define cortex-a76 Peter Maydell
2022-05-09 11:58 ` [PULL 25/32] target/arm: Define neoverse-n1 Peter Maydell
2022-05-09 11:58 ` [PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT Peter Maydell
2022-05-09 11:58 ` [PULL 27/32] qapi/machine.json: Add cluster-id Peter Maydell
2022-05-09 11:58 ` [PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu() Peter Maydell
2022-05-09 11:58 ` [PULL 29/32] hw/arm/virt: Consider SMP configuration in CPU topology Peter Maydell
2022-05-09 11:58 ` [PULL 30/32] qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu() Peter Maydell
2022-05-09 11:58 ` Peter Maydell [this message]
2022-05-09 11:58 ` [PULL 32/32] hw/acpi/aml-build: Use existing CPU topology to build PPTT table Peter Maydell
2022-05-09 18:06 ` [PULL 00/32] target-arm queue Richard Henderson

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