From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c
Date: Mon, 9 May 2022 12:58:22 +0100 [thread overview]
Message-ID: <20220509115848.3521805-7-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.
This will shortly be used from cpu_tcg.c also.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 6 ++++
target/arm/cpu64.c | 64 +++---------------------------------------
target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++
3 files changed, 69 insertions(+), 60 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 255833479d4..343b465d516 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1307,4 +1307,10 @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
#endif
+#ifdef CONFIG_USER_ONLY
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+#else
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+#endif
+
#endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c841d55d0e9..33a0a719003 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -34,65 +34,9 @@
#include "hvf_arm.h"
#include "qapi/visitor.h"
#include "hw/qdev-properties.h"
-#include "cpregs.h"
+#include "internals.h"
-#ifndef CONFIG_USER_ONLY
-static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
- ARMCPU *cpu = env_archcpu(env);
-
- /* Number of cores is in [25:24]; otherwise we RAZ */
- return (cpu->core_count - 1) << 24;
-}
-#endif
-
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
-#ifndef CONFIG_USER_ONLY
- { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
- .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
- .writefn = arm_cp_write_ignore },
- { .name = "L2CTLR",
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
- .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
- .writefn = arm_cp_write_ignore },
-#endif
- { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2ECTLR",
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR",
- .cp = 15, .opc1 = 0, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUECTLR",
- .cp = 15, .opc1 = 1, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUMERRSR",
- .cp = 15, .opc1 = 2, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2MERRSR",
- .cp = 15, .opc1 = 3, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-};
-
static void aarch64_a57_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -143,7 +87,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->gic_num_lrs = 4;
cpu->gic_vpribits = 5;
cpu->gic_vprebits = 5;
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
}
static void aarch64_a53_initfn(Object *obj)
@@ -196,7 +140,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->gic_num_lrs = 4;
cpu->gic_vpribits = 5;
cpu->gic_vprebits = 5;
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
}
static void aarch64_a72_initfn(Object *obj)
@@ -247,7 +191,7 @@ static void aarch64_a72_initfn(Object *obj)
cpu->gic_num_lrs = 4;
cpu->gic_vpribits = 5;
cpu->gic_vprebits = 5;
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
}
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 9338088b226..d078f06931c 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -20,6 +20,65 @@
#endif
#include "cpregs.h"
+#ifndef CONFIG_USER_ONLY
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ ARMCPU *cpu = env_archcpu(env);
+
+ /* Number of cores is in [25:24]; otherwise we RAZ */
+ return (cpu->core_count - 1) << 24;
+}
+
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+ { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
+ .access = PL1_RW, .readfn = l2ctlr_read,
+ .writefn = arm_cp_write_ignore },
+ { .name = "L2CTLR",
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
+ .access = PL1_RW, .readfn = l2ctlr_read,
+ .writefn = arm_cp_write_ignore },
+ { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "L2ECTLR",
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR",
+ .cp = 15, .opc1 = 0, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUECTLR",
+ .cp = 15, .opc1 = 1, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUMERRSR",
+ .cp = 15, .opc1 = 2, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "L2MERRSR",
+ .cp = 15, .opc1 = 3, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+};
+
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
+{
+ define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+}
+#endif /* !CONFIG_USER_ONLY */
+
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
--
2.25.1
next prev parent reply other threads:[~2022-05-09 12:02 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-09 11:58 [PULL 00/32] target-arm queue Peter Maydell
2022-05-09 11:58 ` [PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm Peter Maydell
2022-05-09 11:58 ` [PULL 02/32] target/arm: Handle cpreg registration for missing EL Peter Maydell
2022-05-09 11:58 ` [PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks Peter Maydell
2022-05-09 11:58 ` [PULL 04/32] target/arm: Merge zcr reginfo Peter Maydell
2022-05-09 11:58 ` [PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2 Peter Maydell
2022-05-09 11:58 ` Peter Maydell [this message]
2022-05-09 11:58 ` [PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Peter Maydell
2022-05-09 11:58 ` [PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Peter Maydell
2022-05-09 11:58 ` [PULL 09/32] target/arm: Split out aa32_max_features Peter Maydell
2022-05-09 11:58 ` [PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers Peter Maydell
2022-05-09 11:58 ` [PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes Peter Maydell
2022-05-09 11:58 ` [PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max Peter Maydell
2022-05-09 11:58 ` [PULL 13/32] target/arm: Enable FEAT_Debugv8p4 " Peter Maydell
2022-05-09 11:58 ` [PULL 14/32] target/arm: Add minimal RAS registers Peter Maydell
2022-05-09 11:58 ` [PULL 15/32] target/arm: Enable SCR and HCR bits for RAS Peter Maydell
2022-05-09 11:58 ` [PULL 16/32] target/arm: Implement virtual SError exceptions Peter Maydell
2022-05-09 11:58 ` [PULL 17/32] target/arm: Implement ESB instruction Peter Maydell
2022-05-09 11:58 ` [PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max Peter Maydell
2022-05-09 11:58 ` [PULL 19/32] target/arm: Enable FEAT_IESB " Peter Maydell
2022-05-09 11:58 ` [PULL 20/32] target/arm: Enable FEAT_CSV2 " Peter Maydell
2022-05-09 11:58 ` [PULL 21/32] target/arm: Enable FEAT_CSV2_2 " Peter Maydell
2022-05-09 11:58 ` [PULL 22/32] target/arm: Enable FEAT_CSV3 " Peter Maydell
2022-05-09 11:58 ` [PULL 23/32] target/arm: Enable FEAT_DGH " Peter Maydell
2022-05-09 11:58 ` [PULL 24/32] target/arm: Define cortex-a76 Peter Maydell
2022-05-09 11:58 ` [PULL 25/32] target/arm: Define neoverse-n1 Peter Maydell
2022-05-09 11:58 ` [PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT Peter Maydell
2022-05-09 11:58 ` [PULL 27/32] qapi/machine.json: Add cluster-id Peter Maydell
2022-05-09 11:58 ` [PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu() Peter Maydell
2022-05-09 11:58 ` [PULL 29/32] hw/arm/virt: Consider SMP configuration in CPU topology Peter Maydell
2022-05-09 11:58 ` [PULL 30/32] qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu() Peter Maydell
2022-05-09 11:58 ` [PULL 31/32] hw/arm/virt: Fix CPU's default NUMA node ID Peter Maydell
2022-05-09 11:58 ` [PULL 32/32] hw/acpi/aml-build: Use existing CPU topology to build PPTT table Peter Maydell
2022-05-09 18:06 ` [PULL 00/32] target-arm queue Richard Henderson
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