* [PATCH 1/2] drm/amdgpu: introduce two work mode for imu
@ 2022-05-20 3:04 Huang Rui
2022-05-20 3:04 ` [PATCH 2/2] drm/amdgpu: use the callback function for reset status polling on IMU Huang Rui
0 siblings, 1 reply; 4+ messages in thread
From: Huang Rui @ 2022-05-20 3:04 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
IMU has two work mode such as debug mode and mission mode. Current GC
v11_0_0 is using the debug mode.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h | 6 +++++
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 30 ++++++++++++++-----------
3 files changed, 24 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
index 56cf127cdf93..cfc4a92837f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
@@ -24,6 +24,11 @@
#ifndef __AMDGPU_IMU_H__
#define __AMDGPU_IMU_H__
+enum imu_work_mode {
+ DEBUG_MODE,
+ MISSION_MODE
+};
+
struct amdgpu_imu_funcs {
int (*init_microcode)(struct amdgpu_device *adev);
int (*load_microcode)(struct amdgpu_device *adev);
@@ -46,6 +51,7 @@ struct imu_rlc_ram_golden {
struct amdgpu_imu {
const struct amdgpu_imu_funcs *funcs;
+ enum imu_work_mode mode;
};
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 8c0a3fc7aaa6..e331ea387ef0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6291,6 +6291,7 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
{
+ adev->gfx.imu.mode = DEBUG_MODE;
adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
index 5d2dfeff8fe5..da18d6724125 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
@@ -125,9 +125,11 @@ static void imu_v11_0_setup(struct amdgpu_device *adev)
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff);
- imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
- imu_reg_val |= 0x1;
- WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
+ if (adev->gfx.imu.mode == DEBUG_MODE) {
+ imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
+ imu_reg_val |= 0x1;
+ WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
+ }
//disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB
imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);
@@ -144,16 +146,18 @@ static int imu_v11_0_start(struct amdgpu_device *adev)
imu_reg_val &= 0xfffffffe;
WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
- for (i = 0; i < adev->usec_timeout; i++) {
- imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
- if ((imu_reg_val & 0x1f) == 0x1f)
- break;
- udelay(1);
- }
-
- if (i >= adev->usec_timeout) {
- dev_err(adev->dev, "init imu: IMU start timeout\n");
- return -ETIMEDOUT;
+ if (adev->gfx.imu.mode == DEBUG_MODE) {
+ for (i = 0; i < adev->usec_timeout; i++) {
+ imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
+ if ((imu_reg_val & 0x1f) == 0x1f)
+ break;
+ udelay(1);
+ }
+
+ if (i >= adev->usec_timeout) {
+ dev_err(adev->dev, "init imu: IMU start timeout\n");
+ return -ETIMEDOUT;
+ }
}
return 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/amdgpu: use the callback function for reset status polling on IMU
2022-05-20 3:04 [PATCH 1/2] drm/amdgpu: introduce two work mode for imu Huang Rui
@ 2022-05-20 3:04 ` Huang Rui
2022-05-26 14:49 ` Alex Deucher
2022-05-26 17:50 ` Alex Deucher
0 siblings, 2 replies; 4+ messages in thread
From: Huang Rui @ 2022-05-20 3:04 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
Switch to use the callback function to poll the reset status on IMU.
Because it will have different sequency on other ASICs.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h | 1 +
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 35 ++++++++++++++++---------
2 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
index cfc4a92837f0..484e936812e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
@@ -35,6 +35,7 @@ struct amdgpu_imu_funcs {
void (*setup_imu)(struct amdgpu_device *adev);
int (*start_imu)(struct amdgpu_device *adev);
void (*program_rlc_ram)(struct amdgpu_device *adev);
+ int (*wait_for_reset_status)(struct amdgpu_device *adev);
};
struct imu_rlc_ram_golden {
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
index da18d6724125..64da0ad688d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
@@ -117,6 +117,25 @@ static int imu_v11_0_load_microcode(struct amdgpu_device *adev)
return 0;
}
+static int imu_v11_0_wait_for_reset_status(struct amdgpu_device *adev)
+{
+ int i, imu_reg_val = 0;
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
+ if ((imu_reg_val & 0x1f) == 0x1f)
+ break;
+ udelay(1);
+ }
+
+ if (i >= adev->usec_timeout) {
+ dev_err(adev->dev, "init imu: IMU start timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
static void imu_v11_0_setup(struct amdgpu_device *adev)
{
int imu_reg_val;
@@ -146,19 +165,8 @@ static int imu_v11_0_start(struct amdgpu_device *adev)
imu_reg_val &= 0xfffffffe;
WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
- if (adev->gfx.imu.mode == DEBUG_MODE) {
- for (i = 0; i < adev->usec_timeout; i++) {
- imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
- if ((imu_reg_val & 0x1f) == 0x1f)
- break;
- udelay(1);
- }
-
- if (i >= adev->usec_timeout) {
- dev_err(adev->dev, "init imu: IMU start timeout\n");
- return -ETIMEDOUT;
- }
- }
+ if (adev->gfx.imu.mode == DEBUG_MODE)
+ return imu_v11_0_wait_for_reset_status(adev);
return 0;
}
@@ -368,4 +376,5 @@ const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs = {
.setup_imu = imu_v11_0_setup,
.start_imu = imu_v11_0_start,
.program_rlc_ram = imu_v11_0_program_rlc_ram,
+ .wait_for_reset_status = imu_v11_0_wait_for_reset_status,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu: use the callback function for reset status polling on IMU
2022-05-20 3:04 ` [PATCH 2/2] drm/amdgpu: use the callback function for reset status polling on IMU Huang Rui
@ 2022-05-26 14:49 ` Alex Deucher
2022-05-26 17:50 ` Alex Deucher
1 sibling, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2022-05-26 14:49 UTC (permalink / raw)
To: Huang Rui; +Cc: Alex Deucher, amd-gfx list
Series is: Acked-by: Alex Deucher <alexander.deucher@amd.com>
On Thu, May 19, 2022 at 11:05 PM Huang Rui <ray.huang@amd.com> wrote:
>
> Switch to use the callback function to poll the reset status on IMU.
> Because it will have different sequency on other ASICs.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 35 ++++++++++++++++---------
> 2 files changed, 23 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
> index cfc4a92837f0..484e936812e4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
> @@ -35,6 +35,7 @@ struct amdgpu_imu_funcs {
> void (*setup_imu)(struct amdgpu_device *adev);
> int (*start_imu)(struct amdgpu_device *adev);
> void (*program_rlc_ram)(struct amdgpu_device *adev);
> + int (*wait_for_reset_status)(struct amdgpu_device *adev);
> };
>
> struct imu_rlc_ram_golden {
> diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
> index da18d6724125..64da0ad688d2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
> @@ -117,6 +117,25 @@ static int imu_v11_0_load_microcode(struct amdgpu_device *adev)
> return 0;
> }
>
> +static int imu_v11_0_wait_for_reset_status(struct amdgpu_device *adev)
> +{
> + int i, imu_reg_val = 0;
> +
> + for (i = 0; i < adev->usec_timeout; i++) {
> + imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
> + if ((imu_reg_val & 0x1f) == 0x1f)
> + break;
> + udelay(1);
> + }
> +
> + if (i >= adev->usec_timeout) {
> + dev_err(adev->dev, "init imu: IMU start timeout\n");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> static void imu_v11_0_setup(struct amdgpu_device *adev)
> {
> int imu_reg_val;
> @@ -146,19 +165,8 @@ static int imu_v11_0_start(struct amdgpu_device *adev)
> imu_reg_val &= 0xfffffffe;
> WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
>
> - if (adev->gfx.imu.mode == DEBUG_MODE) {
> - for (i = 0; i < adev->usec_timeout; i++) {
> - imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
> - if ((imu_reg_val & 0x1f) == 0x1f)
> - break;
> - udelay(1);
> - }
> -
> - if (i >= adev->usec_timeout) {
> - dev_err(adev->dev, "init imu: IMU start timeout\n");
> - return -ETIMEDOUT;
> - }
> - }
> + if (adev->gfx.imu.mode == DEBUG_MODE)
> + return imu_v11_0_wait_for_reset_status(adev);
>
> return 0;
> }
> @@ -368,4 +376,5 @@ const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs = {
> .setup_imu = imu_v11_0_setup,
> .start_imu = imu_v11_0_start,
> .program_rlc_ram = imu_v11_0_program_rlc_ram,
> + .wait_for_reset_status = imu_v11_0_wait_for_reset_status,
> };
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu: use the callback function for reset status polling on IMU
2022-05-20 3:04 ` [PATCH 2/2] drm/amdgpu: use the callback function for reset status polling on IMU Huang Rui
2022-05-26 14:49 ` Alex Deucher
@ 2022-05-26 17:50 ` Alex Deucher
1 sibling, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2022-05-26 17:50 UTC (permalink / raw)
To: Huang Rui; +Cc: Alex Deucher, amd-gfx list
On Thu, May 19, 2022 at 11:05 PM Huang Rui <ray.huang@amd.com> wrote:
>
> Switch to use the callback function to poll the reset status on IMU.
> Because it will have different sequency on other ASICs.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 35 ++++++++++++++++---------
> 2 files changed, 23 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
> index cfc4a92837f0..484e936812e4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
> @@ -35,6 +35,7 @@ struct amdgpu_imu_funcs {
> void (*setup_imu)(struct amdgpu_device *adev);
> int (*start_imu)(struct amdgpu_device *adev);
> void (*program_rlc_ram)(struct amdgpu_device *adev);
> + int (*wait_for_reset_status)(struct amdgpu_device *adev);
> };
>
> struct imu_rlc_ram_golden {
> diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
> index da18d6724125..64da0ad688d2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
> @@ -117,6 +117,25 @@ static int imu_v11_0_load_microcode(struct amdgpu_device *adev)
> return 0;
> }
>
> +static int imu_v11_0_wait_for_reset_status(struct amdgpu_device *adev)
> +{
> + int i, imu_reg_val = 0;
> +
> + for (i = 0; i < adev->usec_timeout; i++) {
> + imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
> + if ((imu_reg_val & 0x1f) == 0x1f)
> + break;
> + udelay(1);
> + }
> +
> + if (i >= adev->usec_timeout) {
> + dev_err(adev->dev, "init imu: IMU start timeout\n");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> static void imu_v11_0_setup(struct amdgpu_device *adev)
> {
> int imu_reg_val;
> @@ -146,19 +165,8 @@ static int imu_v11_0_start(struct amdgpu_device *adev)
> imu_reg_val &= 0xfffffffe;
> WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
>
> - if (adev->gfx.imu.mode == DEBUG_MODE) {
> - for (i = 0; i < adev->usec_timeout; i++) {
> - imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
> - if ((imu_reg_val & 0x1f) == 0x1f)
> - break;
> - udelay(1);
> - }
> -
> - if (i >= adev->usec_timeout) {
> - dev_err(adev->dev, "init imu: IMU start timeout\n");
> - return -ETIMEDOUT;
> - }
> - }
You can drop the stack variable i in this function now. With that
fixed, the series is:
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> + if (adev->gfx.imu.mode == DEBUG_MODE)
> + return imu_v11_0_wait_for_reset_status(adev);
>
> return 0;
> }
> @@ -368,4 +376,5 @@ const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs = {
> .setup_imu = imu_v11_0_setup,
> .start_imu = imu_v11_0_start,
> .program_rlc_ram = imu_v11_0_program_rlc_ram,
> + .wait_for_reset_status = imu_v11_0_wait_for_reset_status,
> };
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-05-26 17:50 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-20 3:04 [PATCH 1/2] drm/amdgpu: introduce two work mode for imu Huang Rui
2022-05-20 3:04 ` [PATCH 2/2] drm/amdgpu: use the callback function for reset status polling on IMU Huang Rui
2022-05-26 14:49 ` Alex Deucher
2022-05-26 17:50 ` Alex Deucher
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