From: Wangseok Lee <wangseok.lee@samsung.com> To: "robh+dt@kernel.org" <robh+dt@kernel.org>, "krzk+dt@kernel.org" <krzk+dt@kernel.org>, "kishon@ti.com" <kishon@ti.com>, "vkoul@kernel.org" <vkoul@kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "jesper.nilsson@axis.com" <jesper.nilsson@axis.com>, "lars.persson@axis.com" <lars.persson@axis.com> Cc: "bhelgaas@google.com" <bhelgaas@google.com>, "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "kw@linux.com" <kw@linux.com>, "linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>, "kernel@axis.com" <kernel@axis.com>, Moon-Ki Jun <moonki.jun@samsung.com>, Sang Min Kim <hypmean.kim@samsung.com>, Dongjin Yang <dj76.yang@samsung.com> Subject: [PATCH v2 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Date: Fri, 03 Jun 2022 11:31:58 +0900 [thread overview] Message-ID: <20220603023158epcms2p6949f6cd93926b9e811e1b4d52fbef91b@epcms2p6> (raw) In-Reply-To: <20220603015431epcms2p6203908cebe6a320854136559a32b54cb@epcms2p6> Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis Communications and PCIe phy is designed based on SAMSUNG PHY. changes since v1 : -'make dt_binding_check' result improvement -Add the missing property list -Align the indentation of continued lines/entries Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com> --- .../bindings/phy/axis,artpec8-pcie-phy.yaml | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml new file mode 100644 index 0000000..ab9766f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARTPEC-8 SoC PCIe PHY Device Tree Bindings + +maintainers: + - Jesper Nilsson <jesper.nilsson@axis.com> + +properties: + compatible: + const: axis,artpec8-pcie-phy + + reg: + items: + - description: PHY registers. + - description: PHY coding sublayer registers. + + reg-names: + items: + - const: phy + - const: pcs + + "#phy-cells": + const: 0 + + clocks: + items: + - description: PCIe PHY reference clock + + clock-names: + items: + - const: ref_clk + + num-lanes: + const: 2 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - clocks + - clock-names + - num-lanes + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + artpec8 { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@16c80000 { + compatible = "axis,artpec8-pcie-phy"; + reg = <0x0 0x16c80000 0x0 0x2000>, + <0x0 0x16c90000 0x0 0x1000>; + reg-names = "phy", "pcs"; + #phy-cells = <0>; + clocks = <&clock_cmu_fsys 53>; + clock-names = "ref_clk"; + num-lanes = <2>; + }; + }; +... -- 2.9.5
WARNING: multiple messages have this Message-ID (diff)
From: Wangseok Lee <wangseok.lee@samsung.com> To: "robh+dt@kernel.org" <robh+dt@kernel.org>, "krzk+dt@kernel.org" <krzk+dt@kernel.org>, "kishon@ti.com" <kishon@ti.com>, "vkoul@kernel.org" <vkoul@kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "jesper.nilsson@axis.com" <jesper.nilsson@axis.com>, "lars.persson@axis.com" <lars.persson@axis.com> Cc: "bhelgaas@google.com" <bhelgaas@google.com>, "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "kw@linux.com" <kw@linux.com>, "linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>, "kernel@axis.com" <kernel@axis.com>, Moon-Ki Jun <moonki.jun@samsung.com>, Sang Min Kim <hypmean.kim@samsung.com>, Dongjin Yang <dj76.yang@samsung.com> Subject: [PATCH v2 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Date: Fri, 03 Jun 2022 11:31:58 +0900 [thread overview] Message-ID: <20220603023158epcms2p6949f6cd93926b9e811e1b4d52fbef91b@epcms2p6> (raw) In-Reply-To: <20220603015431epcms2p6203908cebe6a320854136559a32b54cb@epcms2p6> Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis Communications and PCIe phy is designed based on SAMSUNG PHY. changes since v1 : -'make dt_binding_check' result improvement -Add the missing property list -Align the indentation of continued lines/entries Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com> --- .../bindings/phy/axis,artpec8-pcie-phy.yaml | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml new file mode 100644 index 0000000..ab9766f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARTPEC-8 SoC PCIe PHY Device Tree Bindings + +maintainers: + - Jesper Nilsson <jesper.nilsson@axis.com> + +properties: + compatible: + const: axis,artpec8-pcie-phy + + reg: + items: + - description: PHY registers. + - description: PHY coding sublayer registers. + + reg-names: + items: + - const: phy + - const: pcs + + "#phy-cells": + const: 0 + + clocks: + items: + - description: PCIe PHY reference clock + + clock-names: + items: + - const: ref_clk + + num-lanes: + const: 2 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - clocks + - clock-names + - num-lanes + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + artpec8 { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@16c80000 { + compatible = "axis,artpec8-pcie-phy"; + reg = <0x0 0x16c80000 0x0 0x2000>, + <0x0 0x16c90000 0x0 0x1000>; + reg-names = "phy", "pcs"; + #phy-cells = <0>; + clocks = <&clock_cmu_fsys 53>; + clock-names = "ref_clk"; + num-lanes = <2>; + }; + }; +... -- 2.9.5 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2022-06-03 2:32 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20220603015431epcms2p6203908cebe6a320854136559a32b54cb@epcms2p6> 2022-06-03 1:54 ` [PATCH v2 0/5] Add support for Axis, ARTPEC-8 PCIe driver Wangseok Lee 2022-06-03 1:54 ` Wangseok Lee [not found] ` <CGME20220603015431epcms2p6203908cebe6a320854136559a32b54cb@epcms2p5> 2022-06-03 2:23 ` [PATCH v2 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee 2022-06-03 2:23 ` Wangseok Lee 2022-06-06 10:12 ` Krzysztof Kozlowski 2022-06-06 10:12 ` Krzysztof Kozlowski [not found] ` <CGME20220603015431epcms2p6203908cebe6a320854136559a32b54cb@epcms2p8> 2022-06-08 3:30 ` Wangseok Lee 2022-06-08 3:30 ` Wangseok Lee 2022-06-08 3:30 ` [PATCH v2 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee 2022-06-08 3:30 ` Wangseok Lee [not found] ` <CGME20220603015431epcms2p6203908cebe6a320854136559a32b54cb@epcms2p2> 2022-06-03 2:34 ` [PATCH v2 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee 2022-06-03 2:34 ` Wangseok Lee 2022-06-03 16:03 ` Bjorn Helgaas 2022-06-03 16:03 ` Bjorn Helgaas 2022-06-07 7:03 ` Jesper Nilsson 2022-06-07 7:03 ` Jesper Nilsson [not found] ` <CGME20220603160329epcas2p1bdb17f3c29513d82b156bae743d8e00d@epcms2p5> 2022-06-10 0:03 ` Wangseok Lee 2022-06-10 0:03 ` Wangseok Lee 2022-06-10 15:30 ` Bjorn Helgaas 2022-06-10 15:30 ` Bjorn Helgaas [not found] ` <CGME20220610153050epcas2p3b0d83f4f56ffe81a06aae73d8994a3d1@epcms2p7> 2022-06-13 1:50 ` Wangseok Lee 2022-06-13 1:50 ` Wangseok Lee 2022-06-06 10:23 ` Krzysztof Kozlowski 2022-06-06 10:23 ` Krzysztof Kozlowski [not found] ` <CGME20220603015431epcms2p6203908cebe6a320854136559a32b54cb@epcms2p7> 2022-06-03 2:38 ` [PATCH v2 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee 2022-06-03 2:38 ` Wangseok Lee 2022-06-06 10:28 ` Krzysztof Kozlowski 2022-06-06 10:28 ` Krzysztof Kozlowski [not found] ` <CGME20220603015431epcms2p6203908cebe6a320854136559a32b54cb@epcms2p4> 2022-06-03 2:43 ` [PATCH v2 5/5] MAINTAINERS: Add maintainer for Axis " Wangseok Lee 2022-06-03 2:43 ` Wangseok Lee 2022-06-03 16:09 ` Bjorn Helgaas 2022-06-03 16:09 ` Bjorn Helgaas 2022-06-07 7:05 ` Jesper Nilsson 2022-06-07 7:05 ` Jesper Nilsson 2022-06-08 3:31 ` [PATCH v2 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee 2022-06-08 3:31 ` Wangseok Lee 2022-06-03 2:31 ` Wangseok Lee [this message] 2022-06-03 2:31 ` [PATCH v2 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee 2022-06-06 10:14 ` Krzysztof Kozlowski 2022-06-06 10:14 ` Krzysztof Kozlowski 2022-06-08 4:14 ` [PATCH v2 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee 2022-06-08 4:14 ` Wangseok Lee
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