From: John.C.Harrison@Intel.com
To: Intel-GFX@Lists.FreeDesktop.Org
Cc: "Matthew Brost" <matthew.brost@intel.com>,
"Daniele Ceraolo Spurio" <daniele.ceraolospurio@intel.com>,
"Michał Winiarski" <michal.winiarski@intel.com>,
"John Harrison" <John.C.Harrison@Intel.com>,
DRI-Devel@Lists.FreeDesktop.Org
Subject: [PATCH 1/6] drm/i915/guc: Route semaphores to GuC for Gen12+
Date: Wed, 27 Jul 2022 19:42:20 -0700 [thread overview]
Message-ID: <20220728024225.2363663-2-John.C.Harrison@Intel.com> (raw)
In-Reply-To: <20220728024225.2363663-1-John.C.Harrison@Intel.com>
From: Michał Winiarski <michal.winiarski@intel.com>
In GuC submission mode, there is an option to use auto-switch out
semaphores and have GuC auto-switch in a waiting context. This
requires routing the semaphore interrupt to GuC.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 4 ++++
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 14 ++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index 8dc063f087eb1..a7092f711e9cd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -102,6 +102,10 @@
#define GUC_SEND_TRIGGER (1<<0)
#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
+#define GEN12_GUC_SEM_INTR_ENABLES _MMIO(0xc71c)
+#define GUC_SEM_INTR_ROUTE_TO_GUC BIT(31)
+#define GUC_SEM_INTR_ENABLE_ALL (0xff)
+
#define GUC_NUM_DOORBELLS 256
/* format of the HW-monitored doorbell cacheline */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 76916aed897ad..0b8c6450fa344 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4191,13 +4191,27 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
void intel_guc_submission_enable(struct intel_guc *guc)
{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ /* Enable and route to GuC */
+ if (GRAPHICS_VER(gt->i915) >= 12)
+ intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES,
+ GUC_SEM_INTR_ROUTE_TO_GUC |
+ GUC_SEM_INTR_ENABLE_ALL);
+
guc_init_lrc_mapping(guc);
guc_init_engine_stats(guc);
}
void intel_guc_submission_disable(struct intel_guc *guc)
{
+ struct intel_gt *gt = guc_to_gt(guc);
+
/* Note: By the time we're here, GuC may have already been reset */
+
+ /* Disable and route to host */
+ if (GRAPHICS_VER(gt->i915) >= 12)
+ intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES, 0x0);
}
static bool __guc_submission_supported(struct intel_guc *guc)
--
2.37.1
WARNING: multiple messages have this Message-ID (diff)
From: John.C.Harrison@Intel.com
To: Intel-GFX@Lists.FreeDesktop.Org
Cc: "Michał Winiarski" <michal.winiarski@intel.com>,
DRI-Devel@Lists.FreeDesktop.Org
Subject: [Intel-gfx] [PATCH 1/6] drm/i915/guc: Route semaphores to GuC for Gen12+
Date: Wed, 27 Jul 2022 19:42:20 -0700 [thread overview]
Message-ID: <20220728024225.2363663-2-John.C.Harrison@Intel.com> (raw)
In-Reply-To: <20220728024225.2363663-1-John.C.Harrison@Intel.com>
From: Michał Winiarski <michal.winiarski@intel.com>
In GuC submission mode, there is an option to use auto-switch out
semaphores and have GuC auto-switch in a waiting context. This
requires routing the semaphore interrupt to GuC.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 4 ++++
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 14 ++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index 8dc063f087eb1..a7092f711e9cd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -102,6 +102,10 @@
#define GUC_SEND_TRIGGER (1<<0)
#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
+#define GEN12_GUC_SEM_INTR_ENABLES _MMIO(0xc71c)
+#define GUC_SEM_INTR_ROUTE_TO_GUC BIT(31)
+#define GUC_SEM_INTR_ENABLE_ALL (0xff)
+
#define GUC_NUM_DOORBELLS 256
/* format of the HW-monitored doorbell cacheline */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 76916aed897ad..0b8c6450fa344 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4191,13 +4191,27 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
void intel_guc_submission_enable(struct intel_guc *guc)
{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ /* Enable and route to GuC */
+ if (GRAPHICS_VER(gt->i915) >= 12)
+ intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES,
+ GUC_SEM_INTR_ROUTE_TO_GUC |
+ GUC_SEM_INTR_ENABLE_ALL);
+
guc_init_lrc_mapping(guc);
guc_init_engine_stats(guc);
}
void intel_guc_submission_disable(struct intel_guc *guc)
{
+ struct intel_gt *gt = guc_to_gt(guc);
+
/* Note: By the time we're here, GuC may have already been reset */
+
+ /* Disable and route to host */
+ if (GRAPHICS_VER(gt->i915) >= 12)
+ intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES, 0x0);
}
static bool __guc_submission_supported(struct intel_guc *guc)
--
2.37.1
next prev parent reply other threads:[~2022-07-28 2:43 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-28 2:42 [PATCH 0/6] Random assortment of (mostly) GuC related patches John.C.Harrison
2022-07-28 2:42 ` [Intel-gfx] " John.C.Harrison
2022-07-28 2:42 ` John.C.Harrison [this message]
2022-07-28 2:42 ` [Intel-gfx] [PATCH 1/6] drm/i915/guc: Route semaphores to GuC for Gen12+ John.C.Harrison
2022-07-28 2:42 ` [PATCH 2/6] drm/i915/guc: Fix issues with live_preempt_cancel John.C.Harrison
2022-07-28 2:42 ` [Intel-gfx] " John.C.Harrison
2022-07-28 2:45 ` John Harrison
2022-07-28 2:45 ` [Intel-gfx] " John Harrison
2022-07-28 2:42 ` [PATCH 3/6] drm/i915/guc: Add selftest for a hung GuC John.C.Harrison
2022-07-28 2:42 ` [Intel-gfx] " John.C.Harrison
2022-07-28 18:21 ` John Harrison
2022-07-28 18:21 ` [Intel-gfx] " John Harrison
2022-07-28 18:26 ` John.C.Harrison
2022-07-28 18:26 ` [Intel-gfx] " John.C.Harrison
2022-07-28 18:33 ` John Harrison
2022-07-28 18:33 ` [Intel-gfx] " John Harrison
2022-07-28 2:42 ` [PATCH 4/6] drm/i915/selftest: Cope with not having an RCS engine John.C.Harrison
2022-07-28 2:42 ` [Intel-gfx] " John.C.Harrison
2022-07-28 2:42 ` [PATCH 5/6] drm/i915/guc: Support larger contexts on newer hardware John.C.Harrison
2022-07-28 2:42 ` [Intel-gfx] " John.C.Harrison
2022-07-28 2:46 ` John Harrison
2022-07-28 2:46 ` [Intel-gfx] " John Harrison
2022-07-28 2:42 ` [PATCH 6/6] drm/i915/guc: Don't abort on CTB_UNUSED status John.C.Harrison
2022-07-28 2:42 ` [Intel-gfx] " John.C.Harrison
2022-07-28 19:06 ` Michal Wajdeczko
2022-07-28 19:38 ` John Harrison
2022-07-29 0:00 ` Ceraolo Spurio, Daniele
2022-07-29 0:35 ` John Harrison
2022-07-28 3:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Random assortment of (mostly) GuC related patches (rev3) Patchwork
2022-07-28 3:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-07-28 3:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-07-28 10:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-07-28 19:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Random assortment of (mostly) GuC related patches (rev4) Patchwork
2022-07-28 19:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-07-28 19:40 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-07-29 0:40 ` John Harrison
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