* [PATCH 00/50] pinctrl: renesas: Reserved field optimizations
@ 2022-04-13 17:23 Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 01/50] pinctrl: renesas: r8a77470: Use fixed-width description for IPSR regs Geert Uytterhoeven
` (50 more replies)
0 siblings, 51 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Hi Linus,
Lots of register in pin control subdrivers for Renesas SoCs contain
reserved or unused fields. As the macros for describing these registers
(PINMUX_CFG_REG() and PINMUX_CFG_REG_VAR() for registers with
fixed-width resp. variable-width fields) require describing all fields,
the resulting data structures contain lots of dummy (zero) values: 2^N
values for a field of N-bits wide. To reduce data size, reserved bit
fields wider than 3 bits were typically split in multiple 2-bit fields.
This patch series aims to improve this by introducing a shorthand for
describing reserved variable-width register fields without dummy values.
- Patch 1 converts a few register definitions for registers with
fixed-width fields that accidentally used the equivalent but larger
description format intended for registers with variable-width
fields,
- Patch 2 introduces a shorthand for describing reserved register
fields,
- Patches 3-22 convert reserved field descriptions in the various
SoC-specific pin control subdrivers to the new shorthands,
- Patches 23-49 convert register definitions for registers with
reserved fixed-width fields to the equivalent definitions with
variable-width fields where it makes sense,
- Patch 50 updates the checker to flag possible conversions to
variable-width reserved fields.
The total kernel size reduction due to patches 3-49 is:
- 12685 bytes on ARM32 SoCs (multi-platform),
- 5416 bytes on ARM64 SoCs (multi-platform),
- 2575 bytes on SH SoCs (sum of mutually-exclusive single platforms).
I've been running with these changes on R-Mobile APE6 and A1, R-Car
M2-W, H3 ES1.x, H3 ES2.0, M3-W, M3-N, V3M, E3, D3, V3U, and S4, and
SH-Mobile AG5 during the past six weeks, without any issues.
I plan to queue these in renesas-pinctrl-for-v5.19.
Thanks for your comments!
Geert Uytterhoeven (50):
pinctrl: renesas: r8a77470: Use fixed-width description for IPSR regs
pinctrl: renesas: Add shorthand for reserved register fields
pinctrl: renesas: rmobile: Mark unused PORTCR bits reserved
pinctrl: renesas: emev2: Use shorthands for reserved fields
pinctrl: renesas: r8a77470: Use shorthands for reserved fields
pinctrl: renesas: r8a7778: Use shorthands for reserved fields
pinctrl: renesas: r8a7779: Use shorthands for reserved fields
pinctrl: renesas: r8a7790: Use shorthands for reserved fields
pinctrl: renesas: r8a7791: Use shorthands for reserved fields
pinctrl: renesas: r8a7792: Use shorthands for reserved fields
pinctrl: renesas: r8a7794: Use shorthands for reserved fields
pinctrl: renesas: r8a77950: Use shorthands for reserved fields
pinctrl: renesas: r8a77951: Use shorthands for reserved fields
pinctrl: renesas: r8a7796: Use shorthands for reserved fields
pinctrl: renesas: r8a77965: Use shorthands for reserved fields
pinctrl: renesas: r8a77970: Use shorthands for reserved fields
pinctrl: renesas: r8a77980: Use shorthands for reserved fields
pinctrl: renesas: r8a77990: Use shorthands for reserved fields
pinctrl: renesas: r8a77995: Use shorthands for reserved fields
pinctrl: renesas: r8a779a0: Use shorthands for reserved fields
pinctrl: renesas: r8a779f0: Use shorthands for reserved fields
pinctrl: renesas: sh7734: Use shorthands for reserved fields
pinctrl: renesas: r8a73a4: Optimize fixed-width reserved fields
pinctrl: renesas: r8a7740: Optimize fixed-width reserved fields
pinctrl: renesas: r8a77470: Optimize fixed-width reserved fields
pinctrl: renesas: r8a7779: Optimize fixed-width reserved fields
pinctrl: renesas: r8a7792: Optimize fixed-width reserved fields
pinctrl: renesas: r8a77950: Optimize fixed-width reserved fields
pinctrl: renesas: r8a77951: Optimize fixed-width reserved fields
pinctrl: renesas: r8a77965: Optimize fixed-width reserved fields
pinctrl: renesas: r8a7796: Optimize fixed-width reserved fields
pinctrl: renesas: r8a77970: Optimize fixed-width reserved fields
pinctrl: renesas: r8a77980: Optimize fixed-width reserved fields
pinctrl: renesas: r8a77990: Optimize fixed-width reserved fields
pinctrl: renesas: r8a77995: Optimize fixed-width reserved fields
pinctrl: renesas: r8a779a0: Optimize fixed-width reserved fields
pinctrl: renesas: r8a779f0: Optimize fixed-width reserved fields
pinctrl: renesas: sh7203: Optimize fixed-width reserved fields
pinctrl: renesas: sh7264: Optimize fixed-width reserved fields
pinctrl: renesas: sh7269: Optimize fixed-width reserved fields
pinctrl: renesas: sh73a0: Optimize fixed-width reserved fields
pinctrl: renesas: sh7720: Optimize fixed-width reserved fields
pinctrl: renesas: sh7722: Optimize fixed-width reserved fields
pinctrl: renesas: sh7723: Optimize fixed-width reserved fields
pinctrl: renesas: sh7724: Optimize fixed-width reserved fields
pinctrl: renesas: sh7734: Optimize fixed-width reserved fields
pinctrl: renesas: sh7757: Optimize fixed-width reserved fields
pinctrl: renesas: sh7785: Optimize fixed-width reserved fields
pinctrl: renesas: sh7786: Optimize fixed-width reserved fields
pinctrl: renesas: checker: Add reserved field checks
drivers/pinctrl/renesas/core.c | 43 +++--
drivers/pinctrl/renesas/pfc-emev2.c | 59 ++-----
drivers/pinctrl/renesas/pfc-r8a73a4.c | 58 ++-----
drivers/pinctrl/renesas/pfc-r8a7740.c | 74 ++++----
drivers/pinctrl/renesas/pfc-r8a77470.c | 176 +++++--------------
drivers/pinctrl/renesas/pfc-r8a7778.c | 98 +++--------
drivers/pinctrl/renesas/pfc-r8a7779.c | 82 +++------
drivers/pinctrl/renesas/pfc-r8a7790.c | 110 ++++--------
drivers/pinctrl/renesas/pfc-r8a7791.c | 111 ++++--------
drivers/pinctrl/renesas/pfc-r8a7792.c | 231 ++++++-------------------
drivers/pinctrl/renesas/pfc-r8a7794.c | 97 +++--------
drivers/pinctrl/renesas/pfc-r8a77950.c | 170 ++++--------------
drivers/pinctrl/renesas/pfc-r8a77951.c | 169 +++++-------------
drivers/pinctrl/renesas/pfc-r8a7796.c | 166 +++++-------------
drivers/pinctrl/renesas/pfc-r8a77965.c | 166 +++++-------------
drivers/pinctrl/renesas/pfc-r8a77970.c | 136 ++++-----------
drivers/pinctrl/renesas/pfc-r8a77980.c | 107 ++++--------
drivers/pinctrl/renesas/pfc-r8a77990.c | 132 ++++----------
drivers/pinctrl/renesas/pfc-r8a77995.c | 131 +++-----------
drivers/pinctrl/renesas/pfc-r8a779a0.c | 217 ++++++++---------------
drivers/pinctrl/renesas/pfc-r8a779f0.c | 100 ++++-------
drivers/pinctrl/renesas/pfc-sh7203.c | 53 +++---
drivers/pinctrl/renesas/pfc-sh7264.c | 104 +++++------
drivers/pinctrl/renesas/pfc-sh7269.c | 82 ++++-----
drivers/pinctrl/renesas/pfc-sh73a0.c | 87 ++++------
drivers/pinctrl/renesas/pfc-sh7720.c | 57 +++---
drivers/pinctrl/renesas/pfc-sh7722.c | 202 +++++++++------------
drivers/pinctrl/renesas/pfc-sh7723.c | 70 ++++----
drivers/pinctrl/renesas/pfc-sh7724.c | 7 +-
drivers/pinctrl/renesas/pfc-sh7734.c | 115 ++++--------
drivers/pinctrl/renesas/pfc-sh7757.c | 95 ++++------
drivers/pinctrl/renesas/pfc-sh7785.c | 60 +++----
drivers/pinctrl/renesas/pfc-sh7786.c | 21 +--
drivers/pinctrl/renesas/sh_pfc.h | 17 +-
34 files changed, 1116 insertions(+), 2487 deletions(-)
--
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 01/50] pinctrl: renesas: r8a77470: Use fixed-width description for IPSR regs
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 02/50] pinctrl: renesas: Add shorthand for reserved register fields Geert Uytterhoeven
` (49 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
All fields in the IPSR registers on RZ/G1C have the same width, but the
driver describes them using the PINMUX_CFG_REG_VAR() macro, which
is intended for fields with different widths. Convert the description
to use the PINMUX_CFG_REG() macro for fixed-width fields instead.
This reduces kernel size by 162 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77470.c | 72 +++++++-------------------
1 file changed, 18 insertions(+), 54 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77470.c b/drivers/pinctrl/renesas/pfc-r8a77470.c
index ee6e8fabab246c2b..63db71ebb7e955ec 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77470.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77470.c
@@ -2689,9 +2689,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_1_FN, FN_IP14_3_0,
GP_5_0_FN, FN_IP13_31_28, ))
},
- { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR0", 0xE6060040, 32, 4, GROUP(
/* IP0_31_28 [4] */
FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -2717,9 +2715,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR1", 0xE6060044, 32, 4, GROUP(
/* IP1_31_28 [4] */
FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -2745,9 +2741,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR2", 0xE6060048, 32, 4, GROUP(
/* IP2_31_28 [4] */
FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
@@ -2773,9 +2767,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR3", 0xE606004C, 32, 4, GROUP(
/* IP3_31_28 [4] */
FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
@@ -2802,9 +2794,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, FN_AVB_AVTP_CAPTURE_A,
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR4", 0xE6060050, 32, 4, GROUP(
/* IP4_31_28 [4] */
FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -2830,9 +2820,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR5", 0xE6060054, 32, 4, GROUP(
/* IP5_31_28 [4] */
FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0,
0, 0, 0, 0, 0, 0,
@@ -2858,9 +2846,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR6", 0xE6060058, 32, 4, GROUP(
/* IP6_31_28 [4] */
FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
0, 0, 0, 0, 0, 0, 0,
@@ -2886,9 +2872,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15,
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR7", 0xE606005C, 32, 4, GROUP(
/* IP7_31_28 [4] */
FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
@@ -2914,9 +2898,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
0, 0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR8", 0xE6060060, 32, 4, GROUP(
/* IP8_31_28 [4] */
FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
@@ -2942,9 +2924,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR9", 0xE6060064, 32, 4, GROUP(
/* IP9_31_28 [4] */
FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
@@ -2970,9 +2950,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR10", 0xE6060068, 32, 4, GROUP(
/* IP10_31_28 [4] */
FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2999,9 +2977,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR11", 0xE606006C, 32, 4, GROUP(
/* IP11_31_28 [4] */
FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3031,9 +3007,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR12", 0xE6060070, 32, 4, GROUP(
/* IP12_31_28 [4] */
FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3059,9 +3033,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR13", 0xE6060074, 32, 4, GROUP(
/* IP13_31_28 [4] */
FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
@@ -3088,9 +3060,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR14", 0xE6060078, 32, 4, GROUP(
/* IP14_31_28 [4] */
FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3116,9 +3086,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR15", 0xE606007C, 32, 4, GROUP(
/* IP15_31_28 [4] */
FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
0, 0, 0, 0, 0, 0,
@@ -3144,9 +3112,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR16", 0xE6060080, 32, 4, GROUP(
/* IP16_31_28 [4] */
FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3173,9 +3139,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
- GROUP(4, 4, 4, 4, 4, 4, 4, 4),
- GROUP(
+ { PINMUX_CFG_REG("IPSR17", 0xE6060084, 32, 4, GROUP(
/* IP17_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_27_24 [4] */
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 02/50] pinctrl: renesas: Add shorthand for reserved register fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 01/50] pinctrl: renesas: r8a77470: Use fixed-width description for IPSR regs Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 03/50] pinctrl: renesas: rmobile: Mark unused PORTCR bits reserved Geert Uytterhoeven
` (48 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Currently, reserved register fields must be fully described using dummy
enum IDs (zeroes), one for each possible state (2^bits states).
Add support for describing reserved fields using negative field width
values as shorthands, thus removing the need for dummy values. Apart
from the obvious size reduction due to the removal of the dummy values,
this will also enable merging adjacent reserved fields into a single
field, reducing the number of fields to describe, and thus kernel size.
Update the checker accordingly.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/core.c | 34 ++++++++++++++++++++------------
drivers/pinctrl/renesas/sh_pfc.h | 13 ++++++------
2 files changed, 28 insertions(+), 19 deletions(-)
diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c
index dae2201a62dc8f8b..356325df9c18f2ea 100644
--- a/drivers/pinctrl/renesas/core.c
+++ b/drivers/pinctrl/renesas/core.c
@@ -13,10 +13,11 @@
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
+#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
-#include <linux/init.h>
+#include <linux/math.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
@@ -214,7 +215,7 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
*maskp = (1 << crp->var_field_width[in_pos]) - 1;
*posp = crp->reg_width;
for (k = 0; k <= in_pos; k++)
- *posp -= crp->var_field_width[k];
+ *posp -= abs(crp->var_field_width[k]);
}
}
@@ -262,14 +263,17 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
if (!r_width)
break;
- for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
+ for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width, m++) {
u32 ncomb;
u32 n;
- if (f_width)
+ if (f_width) {
curr_width = f_width;
- else
- curr_width = config_reg->var_field_width[m];
+ } else {
+ curr_width = abs(config_reg->var_field_width[m]);
+ if (config_reg->var_field_width[m] < 0)
+ continue;
+ }
ncomb = 1 << curr_width;
for (n = 0; n < ncomb; n++) {
@@ -281,7 +285,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
}
}
pos += ncomb;
- m++;
}
k++;
}
@@ -875,7 +878,8 @@ static const struct sh_pfc_pin __init *sh_pfc_find_pin(
static void __init sh_pfc_check_cfg_reg(const char *drvname,
const struct pinmux_cfg_reg *cfg_reg)
{
- unsigned int i, n, rw, fw;
+ unsigned int i, n, rw;
+ int fw;
sh_pfc_check_reg(drvname, cfg_reg->reg,
GENMASK(cfg_reg->reg_width - 1, 0));
@@ -888,11 +892,15 @@ static void __init sh_pfc_check_cfg_reg(const char *drvname,
}
for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
- if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw))
- sh_pfc_warn("reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
- cfg_reg->reg, rw, rw + fw - 1);
- n += 1 << fw;
- rw += fw;
+ if (fw < 0) {
+ rw += -fw;
+ } else {
+ if (is0s(&cfg_reg->enum_ids[n], 1 << fw))
+ sh_pfc_warn("reg 0x%x: field [%u:%u] can be described as reserved\n",
+ cfg_reg->reg, rw, rw + fw - 1);
+ n += 1 << fw;
+ rw += fw;
+ }
}
if (rw != cfg_reg->reg_width)
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index f33e9f5e83a464e0..64e3dde997347ad5 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -112,7 +112,7 @@ struct pinmux_cfg_reg {
#define SET_NR_ENUM_IDS(n)
#endif
const u16 *enum_ids;
- const u8 *var_field_width;
+ const s8 *var_field_width;
};
#define GROUP(...) __VA_ARGS__
@@ -142,14 +142,15 @@ struct pinmux_cfg_reg {
* - r_width: Width of the register (in bits)
* - f_widths: List of widths of the register fields (in bits), from left
* to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
- * - ids: For each register field (from left to right, i.e. MSB to LSB),
- * 2^f_widths[i] enum IDs must be specified, one for each possible
- * combination of the register field bit values, all wrapped using
- * the GROUP() macro.
+ * Reserved fields are indicated by negating the field width.
+ * - ids: For each non-reserved register field (from left to right, i.e. MSB
+ * to LSB), 2^f_widths[i] enum IDs must be specified, one for each
+ * possible combination of the register field bit values, all wrapped
+ * using the GROUP() macro.
*/
#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
.reg = r, .reg_width = r_width, \
- .var_field_width = (const u8 []) { f_widths, 0 }, \
+ .var_field_width = (const s8 []) { f_widths, 0 }, \
SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
.enum_ids = (const u16 []) { ids }
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 03/50] pinctrl: renesas: rmobile: Mark unused PORTCR bits reserved
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 01/50] pinctrl: renesas: r8a77470: Use fixed-width description for IPSR regs Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 02/50] pinctrl: renesas: Add shorthand for reserved register fields Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 04/50] pinctrl: renesas: emev2: Use shorthands for reserved fields Geert Uytterhoeven
` (47 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
The PULMD bits and the SEC bit in the PORTCR register descriptions on
SH/R-Mobile SoCs are either unused or unsupported. Describe them as
reserved bits using a negative field width value, and drop the
corresponding dummy enum IDs.
This reduces kernel size by 2832 (R-Mobile APE6), 2544 (R-Mobile A1),
and/or 3228 (SH-Mobile AG5) bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/sh_pfc.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index 64e3dde997347ad5..12bc279f573311d5 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -739,14 +739,12 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
* PORTnCR helper macro for SH-Mobile/R-Mobile
*/
#define PORTCR(nr, reg) { \
- PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(2, 2, 1, 3), \
+ PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(-2, 2, -1, 3), \
GROUP( \
/* PULMD[1:0], handled by .set_bias() */ \
- 0, 0, 0, 0, \
/* IE and OE */ \
0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
/* SEC, not supported */ \
- 0, 0, \
/* PTMD[2:0] */ \
PORT##nr##_FN0, PORT##nr##_FN1, \
PORT##nr##_FN2, PORT##nr##_FN3, \
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 04/50] pinctrl: renesas: emev2: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (2 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 03/50] pinctrl: renesas: rmobile: Mark unused PORTCR bits reserved Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 05/50] pinctrl: renesas: r8a77470: " Geert Uytterhoeven
` (46 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 769 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-emev2.c | 59 +++++++----------------------
1 file changed, 13 insertions(+), 46 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-emev2.c b/drivers/pinctrl/renesas/pfc-emev2.c
index b3f50853d66ebcd7..1d8b540110f23e4c 100644
--- a/drivers/pinctrl/renesas/pfc-emev2.c
+++ b/drivers/pinctrl/renesas/pfc-emev2.c
@@ -1569,61 +1569,39 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
- 2, 2),
+ GROUP(-20, 2, 2, -6, 2),
GROUP(
- /* 31 - 12 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* 31 - 12 RESERVED */
/* 11 - 10 */
FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01,
FN_SEL_LCD3_11_10_10, 0,
/* 9 - 8 */
FN_SEL_LCD3_9_8_00, 0, FN_SEL_LCD3_9_8_10, 0,
- /* 7 - 2 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* 7 - 2 RESERVED */
/* 1 - 0 */
FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 2),
+ GROUP(-30, 2),
GROUP(
- /* 31 - 2 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* 31 - 2 RESERVED */
/* 1 - 0 */
FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 2),
+ GROUP(-30, 2),
GROUP(
- /* 31 - 2 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* 31 - 2 RESERVED */
/* 1 - 0 */
FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2),
+ GROUP(-18, 2, 2, 2, 2, 2, 2, 2),
GROUP(
- /* 31 - 14 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0,
+ /* 31 - 14 RESERVED */
/* 13 - 12 */
FN_SEL_AB_13_12_00, 0, FN_SEL_AB_13_12_10, 0,
/* 11 - 10 */
@@ -1643,14 +1621,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
- 2, 2, 2),
+ GROUP(-22, 2, 2, 2, 2, 2),
GROUP(
- /* 31 - 10 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* 31 - 10 RESERVED */
/* 9 - 8 */
FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, 0, 0,
/* 7 - 6 */
@@ -1664,15 +1637,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 2),
+ GROUP(-30, 2),
GROUP(
- /* 31 - 2 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* 31 - 2 RESERVED */
/* 1 - 0 */
FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
))
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 05/50] pinctrl: renesas: r8a77470: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (3 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 04/50] pinctrl: renesas: emev2: Use shorthands for reserved fields Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 06/50] pinctrl: renesas: r8a7778: " Geert Uytterhoeven
` (45 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 114 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77470.c | 54 ++++----------------------
1 file changed, 8 insertions(+), 46 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77470.c b/drivers/pinctrl/renesas/pfc-r8a77470.c
index 63db71ebb7e955ec..15a6dffdffcfd581 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77470.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77470.c
@@ -3165,25 +3165,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
- GROUP(1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1,
- 3, 3, 1, 2, 3, 3, 1),
+ GROUP(-5, 2, -2, 2, 2, 2, -1,
+ 3, 3, -1, 2, 3, 3, 1),
GROUP(
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
+ /* RESERVED [5] */
/* SEL_ADGA [2] */
FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
+ /* RESERVED [2] */
/* SEL_CANCLK [2] */
FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
FN_SEL_CANCLK_3,
@@ -3192,7 +3180,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_CAN0 [2] */
FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
/* RESERVED [1] */
- 0, 0,
/* SEL_I2C04 [3] */
FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
FN_SEL_I2C04_4, 0, 0, 0,
@@ -3200,7 +3187,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
FN_SEL_I2C03_4, 0, 0, 0,
/* RESERVED [1] */
- 0, 0,
/* SEL_I2C02 [2] */
FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
/* SEL_I2C01 [3] */
@@ -3213,8 +3199,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_AVB_0, FN_SEL_AVB_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
- GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, 1, 1, 1,
- 1, 1, 2, 1, 1, 2, 2, 1),
+ GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, -1, 1, -1,
+ 1, 1, -2, 1, 1, -2, 2, 1),
GROUP(
/* SEL_SCIFCLK [1] */
FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
@@ -3237,52 +3223,28 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_MSIOF2 [2] */
FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
/* RESERVED [1] */
- 0, 0,
/* SEL_MSIOF1 [1] */
FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
/* RESERVED [1] */
- 0, 0,
/* SEL_MSIOF0 [1] */
FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
/* SEL_RCN [1] */
FN_SEL_RCN_0, FN_SEL_RCN_1,
/* RESERVED [2] */
- 0, 0, 0, 0,
/* SEL_TMU2 [1] */
FN_SEL_TMU2_0, FN_SEL_TMU2_1,
/* SEL_TMU1 [1] */
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
/* RESERVED [2] */
- 0, 0, 0, 0,
/* SEL_HSCIF1 [2] */
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
/* SEL_HSCIF0 [1] */
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
- 2, 2, 2, 2, 2, 2, 2, 2, 2),
+ GROUP(-10, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
GROUP(
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
+ /* RESERVED [10] */
/* SEL_ADGB [2] */
FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
/* SEL_ADGC [2] */
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 06/50] pinctrl: renesas: r8a7778: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (4 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 05/50] pinctrl: renesas: r8a77470: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 07/50] pinctrl: renesas: r8a7779: " Geert Uytterhoeven
` (44 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 142 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a7778.c | 98 +++++++--------------------
1 file changed, 24 insertions(+), 74 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c
index a24672ca3c01babe..35bdb9af81607566 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7778.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7778.c
@@ -2240,11 +2240,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ GROUP(-1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 3, 4, 3, 3, 2),
GROUP(
- /* IP0_31 [1] */
- 0, 0,
+ /* IP0_31 [1] RESERVED */
/* IP0_30 [1] */
FN_A19, 0,
/* IP0_29 [1] */
@@ -2296,13 +2295,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
- GROUP(1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
+ GROUP(-2, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
3, 1, 1),
GROUP(
- /* IP1_31 [1] */
- 0, 0,
- /* IP1_30 [1] */
- 0, 0,
+ /* IP1_31_30 [2] RESERVED */
/* IP1_29_28 [2] */
FN_EX_CS1, FN_MMC_D4, 0, 0,
/* IP1_27_25 [3] */
@@ -2437,11 +2433,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
- GROUP(1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
+ GROUP(-1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
3, 3, 1),
GROUP(
- /* IP4_31 [1] */
- 0, 0,
+ /* IP4_31 [1] RESERVED */
/* IP4_30_29 [2] */
FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0,
/* IP4_28_27 [2] */
@@ -2481,12 +2476,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
- GROUP(1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
+ GROUP(-1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
1, 2, 2, 2),
GROUP(
- /* IP5_31 [1] */
- 0, 0,
+ /* IP5_31 [1] RESERVED */
/* IP5_30_29 [2] */
FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B,
/* IP5_28_26 [3] */
@@ -2619,12 +2613,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
- GROUP(1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
+ GROUP(-2, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
GROUP(
- /* IP8_31 [1] */
- 0, 0,
- /* IP8_30 [1] */
- 0, 0,
+ /* IP8_31_30 [2] RESERVED */
/* IP8_29_27 [3] */
FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5,
0, FN_HRX1_B, 0, 0,
@@ -2660,12 +2651,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
- GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP9_31 [1] */
- 0, 0,
- /* IP9_30 [1] */
- 0, 0,
+ /* IP9_31_30 [2] RESERVED */
/* IP9_29_27 [3] */
FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC,
FN_ETH_RXD1, FN_FMIN_C,
@@ -2703,24 +2691,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4,
- 3, 3, 3),
+ GROUP(-7, 3, 3, 3, 3, 4, 3, 3, 3),
GROUP(
- /* IP10_31 [1] */
- 0, 0,
- /* IP10_30 [1] */
- 0, 0,
- /* IP10_29 [1] */
- 0, 0,
- /* IP10_28 [1] */
- 0, 0,
- /* IP10_27 [1] */
- 0, 0,
- /* IP10_26 [1] */
- 0, 0,
- /* IP10_25 [1] */
- 0, 0,
+ /* IP10_31_25 [7] RESERVED */
/* IP10_24_22 [3] */
FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B,
FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0,
@@ -2754,12 +2728,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
- GROUP(1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
- 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(-1, 1, 2, 2, 3, 2, 2, -1, 1, 1, 1, 2,
+ -1, 1, 1, 1, 2, 1, -1, 1, 1, 1, 1, 1),
GROUP(
- /* SEL 31 [1] */
- 0, 0,
+ /* SEL 31 [1] RESERVED */
/* SEL_30 (SCIF5) [1] */
FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
/* SEL_29_28 (SCIF4) [2] */
@@ -2779,8 +2752,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_20_19 (SCIF0) [2] */
FN_SEL_SCIF0_A, FN_SEL_SCIF0_B,
FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
- /* SEL_18 [1] */
- 0, 0,
+ /* SEL_18 [1] RESERVED */
/* SEL_17 (SSI2) [1] */
FN_SEL_SSI2_A, FN_SEL_SSI2_B,
/* SEL_16 (SSI1) [1] */
@@ -2790,8 +2762,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_14_13 (VI0) [2] */
FN_SEL_VI0_A, FN_SEL_VI0_B,
FN_SEL_VI0_C, FN_SEL_VI0_D,
- /* SEL_12 [1] */
- 0, 0,
+ /* SEL_12 [1] RESERVED */
/* SEL_11 (SD2) [1] */
FN_SEL_SD2_A, FN_SEL_SD2_B,
/* SEL_10 (SD1) [1] */
@@ -2803,8 +2774,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_IRQ2_C, 0,
/* SEL_6 (IRQ1) [1] */
FN_SEL_IRQ1_A, FN_SEL_IRQ1_B,
- /* SEL_5 [1] */
- 0, 0,
+ /* SEL_5 [1] RESERVED */
/* SEL_4 (DREQ2) [1] */
FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
/* SEL_3 (DREQ1) [1] */
@@ -2818,18 +2788,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
- GROUP(1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
+ GROUP(-4, 1, 1, 2, 1, 1, -7,
+ 2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
GROUP(
- /* SEL_31 [1] */
- 0, 0,
- /* SEL_30 [1] */
- 0, 0,
- /* SEL_29 [1] */
- 0, 0,
- /* SEL_28 [1] */
- 0, 0,
+ /* SEL_31_28 [4] RESERVED */
/* SEL_27 (CAN1) [1] */
FN_SEL_CAN1_A, FN_SEL_CAN1_B,
/* SEL_26 (CAN0) [1] */
@@ -2841,20 +2804,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B,
/* SEL_22 (HSCIF0) [1] */
FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B,
- /* SEL_21 [1] */
- 0, 0,
- /* SEL_20 [1] */
- 0, 0,
- /* SEL_19 [1] */
- 0, 0,
- /* SEL_18 [1] */
- 0, 0,
- /* SEL_17 [1] */
- 0, 0,
- /* SEL_16 [1] */
- 0, 0,
- /* SEL_15 [1] */
- 0, 0,
+ /* SEL_21_15 [7] RESERVED */
/* SEL_14_13 (REMOCON) [2] */
FN_SEL_REMOCON_A, FN_SEL_REMOCON_B,
FN_SEL_REMOCON_C, 0,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 07/50] pinctrl: renesas: r8a7779: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (5 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 06/50] pinctrl: renesas: r8a7778: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 08/50] pinctrl: renesas: r8a7790: " Geert Uytterhoeven
` (43 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 197 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a7779.c | 71 +++++++++------------------
1 file changed, 23 insertions(+), 48 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7779.c b/drivers/pinctrl/renesas/pfc-r8a7779.c
index 296b5fb0f3490255..e674549193250b3b 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7779.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7779.c
@@ -3319,10 +3319,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
- GROUP(1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3),
+ GROUP(-1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3),
GROUP(
- /* IP0_31 [1] */
- 0, 0,
+ /* IP0_31 [1] RESERVED */
/* IP0_30_28 [3] */
FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
FN_HRTS1, FN_RX4_C, 0, 0,
@@ -3358,10 +3357,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SCIF_CLK, FN_TCLK0_C, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
- GROUP(3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2),
+ GROUP(-3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2),
GROUP(
- /* IP1_31_29 [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP1_31_29 [3] RESERVED */
/* IP1_28_25 [4] */
FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
@@ -3397,10 +3395,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
- GROUP(1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4),
+ GROUP(-1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4),
GROUP(
- /* IP2_31 [1] */
- 0, 0,
+ /* IP2_31 [1] RESERVED */
/* IP2_30_28 [3] */
FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
FN_AUDATA2, 0, 0, 0,
@@ -3545,11 +3542,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
- GROUP(1, 2, 1, 4, 3, 4, 2, 2, 2, 2, 1, 1,
+ GROUP(-1, 2, 1, 4, 3, 4, 2, 2, 2, 2, 1, 1,
1, 1, 1, 1, 3),
GROUP(
- /* IP5_31 [1] */
- 0, 0,
+ /* IP5_31 [1] RESERVED */
/* IP5_30_29 [2] */
FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
/* IP5_28 [1] */
@@ -3592,15 +3588,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_RX5, FN_RTS0_D_TANS_D, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
- GROUP(1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2,
+ GROUP(-1, 2, -2, 2, 2, 3, 2, 3, 3, 3, 1, 2,
2, 2, 2),
GROUP(
- /* IP6_31 [1] */
- 0, 0,
+ /* IP6_31 [1] RESERVED */
/* IP6_30_29 [2] */
FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
- /* IP_28_27 [2] */
- 0, 0, 0, 0,
+ /* IP_28_27 [2] RESERVED */
/* IP6_26_25 [2] */
FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
/* IP6_24_23 [2] */
@@ -3631,11 +3625,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
- GROUP(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
+ GROUP(-1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
3, 2, 2),
GROUP(
- /* IP7_31 [1] */
- 0, 0,
+ /* IP7_31 [1] RESERVED */
/* IP7_30_29 [2] */
FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
/* IP7_28_27 [2] */
@@ -3669,10 +3662,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
- GROUP(1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4),
+ GROUP(-1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4),
GROUP(
- /* IP8_31 [1] */
- 0, 0,
+ /* IP8_31 [1] RESERVED */
/* IP8_30_28 [3] */
FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
FN_PWMFSW0_C, 0, 0, 0,
@@ -3713,11 +3705,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
- GROUP(2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 1,
+ GROUP(-2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 1,
1, 1, 1, 2, 2),
GROUP(
- /* IP9_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP9_31_30 [2] RESERVED */
/* IP9_29_28 [2] */
FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
/* IP9_27_26 [2] */
@@ -3790,10 +3781,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
- GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP11_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP11_31_30 [2] RESERVED */
/* IP11_29_27 [3] */
FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
@@ -3826,19 +3816,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ADICLK_B, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
- GROUP(4, 4, 4, 2, 3, 3, 3, 3, 3, 3),
+ GROUP(-14, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP12_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP12_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP12_23_20 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP12_19_18 [2] */
- 0, 0, 0, 0,
+ /* IP12_31_18 [14] RESERVED */
/* IP12_17_15 [3] */
FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
FN_SCK4_B, 0, 0, 0,
@@ -3904,7 +3884,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
- GROUP(2, 2, 2, 2, 1, 1, 1, 3, 1, 2, 2, 2,
+ GROUP(2, 2, 2, 2, 1, 1, 1, 3, 1, -6,
2, 1, 1, 2, 1, 2, 2),
GROUP(
/* SEL_TMU1 [2] */
@@ -3926,12 +3906,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
/* SEL_ADI [1] */
FN_SEL_ADI_0, FN_SEL_ADI_1,
- /* [2] */
- 0, 0, 0, 0,
- /* [2] */
- 0, 0, 0, 0,
- /* [2] */
- 0, 0, 0, 0,
+ /* [6] RESERVED */
/* SEL_GPS [2] */
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
/* SEL_SIM [1] */
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 08/50] pinctrl: renesas: r8a7790: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (6 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 07/50] pinctrl: renesas: r8a7779: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 09/50] pinctrl: renesas: r8a7791: " Geert Uytterhoeven
` (42 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 445 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a7790.c | 110 ++++++++------------------
1 file changed, 32 insertions(+), 78 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c
index 9db9e61d96bcca5a..ee21d650991bcec3 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7790.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7790.c
@@ -5122,10 +5122,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_0_FN, FN_IP14_21_19 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
- GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
+ GROUP(-1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
GROUP(
- /* IP0_31 [1] */
- 0, 0,
+ /* IP0_31 [1] RESERVED */
/* IP0_30_27 [4] */
FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
@@ -5159,10 +5158,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
- GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
+ GROUP(-2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
GROUP(
- /* IP1_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP1_31_30 [2] RESERVED */
/* IP1_29_28 [2] */
FN_A1, FN_PWM4, 0, 0,
/* IP1_27_26 [2] */
@@ -5197,10 +5195,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
- GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
+ GROUP(-3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP2_31_29 [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP2_31_29 [3] RESERVED */
/* IP2_28_26 [3] */
FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
@@ -5261,10 +5258,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
- GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP4_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP4_31_30 [2] RESERVED */
/* IP4_29_27 [3] */
FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
@@ -5295,10 +5291,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
- GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
+ GROUP(-2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
GROUP(
- /* IP5_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP5_31_30 [2] RESERVED */
/* IP5_29_27 [3] */
FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
@@ -5368,10 +5363,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
+ GROUP(-1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
GROUP(
- /* IP7_31 [1] */
- 0, 0,
+ /* IP7_31 [1] RESERVED */
/* IP7_30_29 [2] */
FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
/* IP7_28_27 [2] */
@@ -5404,11 +5398,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
- GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
+ GROUP(-1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2),
GROUP(
- /* IP8_31 [1] */
- 0, 0,
+ /* IP8_31 [1] RESERVED */
/* IP8_30_29 [2] */
FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
/* IP8_28 [1] */
@@ -5482,10 +5475,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
- GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
+ GROUP(-2, 4, 3, 4, 4, 4, 4, 3, 4),
GROUP(
- /* IP10_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP10_31_30 [2] RESERVED */
/* IP10_29_26 [4] */
FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
@@ -5558,10 +5550,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
+ GROUP(-1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
GROUP(
- /* IP12_31 [1] */
- 0, 0,
+ /* IP12_31 [1] RESERVED */
/* IP12_30_28 [3] */
FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
@@ -5598,10 +5589,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
- GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
+ GROUP(-1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
GROUP(
- /* IP13_31 [1] */
- 0, 0,
+ /* IP13_31 [1] RESERVED */
/* IP13_30_29 [2] */
FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
/* IP13_28_26 [3] */
@@ -5635,10 +5625,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
- GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
+ GROUP(-1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
GROUP(
- /* IP14_30 [1] */
- 0, 0,
+ /* IP14_30 [1] RESERVED */
/* IP14_30_28 [3] */
FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
@@ -5674,10 +5663,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_REMOCON, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
- GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
+ GROUP(-2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
GROUP(
- /* IP15_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP15_31_30 [2] RESERVED */
/* IP15_29_28 [2] */
FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
/* IP15_27_26 [2] */
@@ -5710,26 +5698,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
- GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
+ GROUP(-24, 1, 1, 3, 3),
GROUP(
- /* IP16_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_23_20 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_19_16 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_15_12 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_11_8 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_31_8 [24] RESERVED */
/* IP16_7 [1] */
FN_USB1_OVC, FN_TCLK1_B,
/* IP16_6 [1] */
@@ -5743,7 +5714,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
- 1, 1, 1, 2, 1, 1, 2, 1, 1),
+ 1, 1, 1, 2, -1, 1, 2, 1, 1),
GROUP(
/* SEL_SCIF1 [3] */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
@@ -5782,7 +5753,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_TSIF1 [2] */
FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
/* RESERVED [1] */
- 0, 0,
/* SEL_LBS [1] */
FN_SEL_LBS_0, FN_SEL_LBS_1,
/* SEL_TSIF0 [2] */
@@ -5793,11 +5763,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
- 3, 3, 2, 3, 2, 2),
+ GROUP(-3, 1, 1, 1, 2, 1, 2, 1, -2, 1, 1, 1,
+ 3, 3, 2, -3, 2, 2),
GROUP(
/* RESERVED [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_TMU1 [1] */
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
/* SEL_HSCIF1 [1] */
@@ -5813,7 +5782,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_CAN1 [1] */
FN_SEL_CAN1_0, FN_SEL_CAN1_1,
/* RESERVED [2] */
- 0, 0, 0, 0,
/* SEL_SCIF2 [1] */
FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
/* SEL_ADI [1] */
@@ -5829,36 +5797,22 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_GPS [2] */
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
/* RESERVED [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_SIM [2] */
FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
/* SEL_SSI8 [2] */
FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
+ GROUP(1, 1, -12, 2, -6, 3, 2, 3, 2),
GROUP(
/* SEL_IICDVFS [1] */
FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
/* SEL_IIC0 [1] */
FN_SEL_IIC0_0, FN_SEL_IIC0_1,
- /* RESERVED [2] */
- 0, 0, 0, 0,
- /* RESERVED [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED [2] */
- 0, 0, 0, 0,
+ /* RESERVED [12] */
/* SEL_IEB [2] */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
- /* RESERVED [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED [2] */
- 0, 0, 0, 0,
+ /* RESERVED [6] */
/* SEL_IIC2 [3] */
FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
FN_SEL_IIC2_4, 0, 0, 0,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 09/50] pinctrl: renesas: r8a7791: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (7 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 08/50] pinctrl: renesas: r8a7790: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 10/50] pinctrl: renesas: r8a7792: " Geert Uytterhoeven
` (41 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 349 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a7791.c | 111 ++++++++------------------
1 file changed, 32 insertions(+), 79 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c
index 076a8b7d71de04d2..d57458504117daa3 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7791.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7791.c
@@ -5686,11 +5686,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_7_0_FN, FN_IP15_17_15 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
- GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
+ GROUP(-1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
- /* IP0_31 [1] */
- 0, 0,
+ /* IP0_31 [1] RESERVED */
/* IP0_30_29 [2] */
FN_A6, FN_MSIOF1_SCK,
0, 0,
@@ -5783,10 +5782,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
- GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
+ GROUP(-2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
GROUP(
- /* IP2_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP2_31_30 [2] RESERVED */
/* IP2_29_27 [3] */
FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
FN_ATAG0_N, 0, FN_EX_WAIT1,
@@ -5820,10 +5818,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
- GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
+ GROUP(-1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
GROUP(
- /* IP3_31 [1] */
- 0, 0,
+ /* IP3_31 [1] RESERVED */
/* IP3_30_28 [3] */
FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
@@ -5859,11 +5856,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
- GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
+ GROUP(-1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
3, 3, 2),
GROUP(
- /* IP4_31 [1] */
- 0, 0,
+ /* IP4_31 [1] RESERVED */
/* IP4_30_28 [3] */
FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
@@ -5943,10 +5939,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
+ GROUP(-2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
GROUP(
- /* IP6_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP6_31_30 [2] RESERVED */
/* IP6_29_27 [3] */
FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
FN_GPS_SIGN_C, FN_GPS_SIGN_D,
@@ -5984,10 +5979,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
+ GROUP(-2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
GROUP(
- /* IP7_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP7_31_30 [2] RESERVED */
/* IP7_29_27 [3] */
FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
FN_SCIFA1_SCK, FN_SSI_SCK78_B,
@@ -6026,10 +6020,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
- GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(-1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP8_31 [1] */
- 0, 0,
+ /* IP8_31 [1] RESERVED */
/* IP8_30_28 [3] */
FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
0, 0, 0,
@@ -6201,10 +6194,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_I2C1_SDA_D, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
+ GROUP(-2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
GROUP(
- /* IP12_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP12_31_30 [2] RESERVED */
/* IP12_29_27 [3] */
FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
@@ -6243,11 +6235,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
- GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
+ GROUP(-1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
1, 1, 1, 3, 2, 2, 3),
GROUP(
- /* IP13_31 [1] */
- 0, 0,
+ /* IP13_31 [1] RESERVED */
/* IP13_30_28 [3] */
FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
0, 0, 0, 0,
@@ -6340,10 +6331,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
- GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
+ GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
GROUP(
- /* IP15_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP15_31_30 [2] RESERVED */
/* IP15_29_27 [3] */
FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
FN_CAN0_TX_B, FN_VI1_DATA5_C,
@@ -6382,23 +6372,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
- GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3),
+ GROUP(-20, 2, 2, 2, 3, 3),
GROUP(
- /* IP16_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_23_20 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_19_16 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_15_12 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED [20] */
/* IP16_11_10 [2] */
FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
/* IP16_9_8 [2] */
@@ -6415,11 +6391,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2,
- 2, 2, 1, 2, 2, 2),
+ GROUP(-1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, -2,
+ 2, -2, 1, 2, 2, 2),
GROUP(
/* RESERVED [1] */
- 0, 0,
/* SEL_SCIF1 [2] */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
/* SEL_SCIFB [2] */
@@ -6446,11 +6421,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
0, 0, 0,
/* RESERVED [2] */
- 0, 0, 0, 0,
/* SEL_VI1 [2] */
FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
/* RESERVED [2] */
- 0, 0, 0, 0,
/* SEL_TMU [1] */
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
/* SEL_LBS [2] */
@@ -6461,15 +6434,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2,
- 1, 2, 2, 2, 1, 1, 1),
+ GROUP(3, -1, 1, 3, 2, -1, 1, 2, -2, 1, 3, 2,
+ -1, 2, 2, 2, 1, -1, 1),
GROUP(
/* SEL_SCIF0 [3] */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
0, 0, 0,
/* RESERVED [1] */
- 0, 0,
/* SEL_SCIF [1] */
FN_SEL_SCIF_0, FN_SEL_SCIF_1,
/* SEL_CAN0 [3] */
@@ -6479,13 +6451,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_CAN1 [2] */
FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
/* RESERVED [1] */
- 0, 0,
/* SEL_SCIFA2 [1] */
FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
/* SEL_SCIF4 [2] */
FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
/* RESERVED [2] */
- 0, 0, 0, 0,
/* SEL_ADG [1] */
FN_SEL_ADG_0, FN_SEL_ADG_1,
/* SEL_FM [3] */
@@ -6495,7 +6465,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_SCIFA5 [2] */
FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
/* RESERVED [1] */
- 0, 0,
/* SEL_GPS [2] */
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
/* SEL_SCIFA4 [2] */
@@ -6505,13 +6474,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_SIM [1] */
FN_SEL_SIM_0, FN_SEL_SIM_1,
/* RESERVED [1] */
- 0, 0,
/* SEL_SSI8 [1] */
FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2,
- 3, 2, 2, 2, 1),
+ GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, -2, 2,
+ 3, 2, -5),
GROUP(
/* SEL_HSCIF2 [2] */
FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
@@ -6536,7 +6504,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_SCIF5 [1] */
FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
/* RESERVED [2] */
- 0, 0, 0, 0,
/* SEL_I2C2 [2] */
FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
/* SEL_I2C1 [3] */
@@ -6545,16 +6512,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0,
/* SEL_I2C0 [2] */
FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
- /* RESERVED [2] */
- 0, 0, 0, 0,
- /* RESERVED [2] */
- 0, 0, 0, 0,
- /* RESERVED [1] */
- 0, 0, ))
+ /* RESERVED [5] */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
- GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1,
- 1, 1, 2, 2, 2, 2),
+ GROUP(3, 2, 2, -1, 1, 1, 1, 3, -4, 3, -1,
+ 1, 1, 2, -6),
GROUP(
/* SEL_SOF1 [3] */
FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
@@ -6565,7 +6527,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_DIS [2] */
FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
/* RESERVED [1] */
- 0, 0,
/* SEL_RAD [1] */
FN_SEL_RAD_0, FN_SEL_RAD_1,
/* SEL_RCN [1] */
@@ -6577,27 +6538,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
0, 0, 0,
/* RESERVED [2] */
- 0, 0, 0, 0,
/* RESERVED [2] */
- 0, 0, 0, 0,
/* SEL_SOF2 [3] */
FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
FN_SEL_SOF2_3, FN_SEL_SOF2_4,
0, 0, 0,
/* RESERVED [1] */
- 0, 0,
/* SEL_SSI1 [1] */
FN_SEL_SSI1_0, FN_SEL_SSI1_1,
/* SEL_SSI0 [1] */
FN_SEL_SSI0_0, FN_SEL_SSI0_1,
/* SEL_SSP [2] */
FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
- /* RESERVED [2] */
- 0, 0, 0, 0,
- /* RESERVED [2] */
- 0, 0, 0, 0,
- /* RESERVED [2] */
- 0, 0, 0, 0, ))
+ /* RESERVED [6] */ ))
},
{ },
};
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 10/50] pinctrl: renesas: r8a7792: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (8 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 09/50] pinctrl: renesas: r8a7791: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 11/50] pinctrl: renesas: r8a7794: " Geert Uytterhoeven
` (40 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 784 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a7792.c | 90 +++++----------------------
1 file changed, 16 insertions(+), 74 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c
index 3e101f63014825fe..282ff1dd58a7493e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7792.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7792.c
@@ -2374,15 +2374,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_11_0_FN, FN_IP7_1_0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
- GROUP(4, 4,
+ GROUP(-8,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
- /* IP0_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP0_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP0_31_24 [8] RESERVED */
/* IP0_23 [1] */
FN_DU0_DB7_C5, 0,
/* IP0_22 [1] */
@@ -2433,17 +2430,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DR0_DATA0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
- GROUP(4, 4,
- 1, 1, 1, 1, 1, 1, 1, 1,
+ GROUP(-9, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
- /* IP1_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP1_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP1_23 [1] */
- 0, 0,
+ /* IP1_31_23 [9] RESERVED */
/* IP1_22 [1] */
FN_A25, FN_SSL,
/* IP1_21 [1] */
@@ -2492,19 +2483,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
- GROUP(4, 4,
- 4, 3, 1,
+ GROUP(-15, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
- /* IP2_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP2_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP2_23_20 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP2_19_17 [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP2_31_17 [15] RESERVED */
/* IP2_16 [1] */
FN_VI2_FIELD, FN_AVB_TXD2,
/* IP2_15 [1] */
@@ -2541,21 +2524,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI2_CLK, FN_AVB_RX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
- GROUP(4, 4,
- 4, 4,
- 1, 1, 1, 1, 1, 1, 1, 1,
+ GROUP(-17, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
- /* IP3_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP3_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP3_23_20 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP3_19_16 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP3_15 [1] */
- 0, 0,
+ /* IP3_31_15 [17] RESERVED */
/* IP3_14 [1] */
FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
/* IP3_13 [1] */
@@ -2588,14 +2560,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI3_CLK, FN_AVB_TX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
- GROUP(4, 3, 1,
- 1, 1, 1, 2, 2, 2,
+ GROUP(-7, 1, 1, 1, 1, 2, 2, 2,
2, 2, 2, 2, 2, 1, 2, 1, 1),
GROUP(
- /* IP4_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP4_27_25 [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP4_31_25 [7] RESERVED */
/* IP4_24 [1] */
FN_VI4_FIELD, FN_VI3_D15_Y7,
/* IP4_23 [1] */
@@ -2630,21 +2598,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
- GROUP(4, 4,
- 4, 4,
- 4, 1, 1, 1, 1,
+ GROUP(-20, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
- /* IP5_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP5_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP5_23_20 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP5_19_16 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP5_15_12 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP5_31_12 [20] RESERVED */
/* IP5_11 [1] */
FN_VI5_D8_Y0, FN_VI1_D23_R7,
/* IP5_10 [1] */
@@ -2671,19 +2628,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
- GROUP(4, 4,
- 4, 1, 2, 1,
- 2, 2, 2, 2,
+ GROUP(-13, 2, 1, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
- /* IP6_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP6_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP6_23_20 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP6_19 [1] */
- 0, 0,
+ /* IP6_31_19 [13] RESERVED */
/* IP6_18_17 [2] */
FN_DREQ1_N, FN_RX3, 0, 0,
/* IP6_16 [1] */
@@ -2714,17 +2662,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_MSIOF0_SCK, FN_HSCK0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
- GROUP(4, 4,
- 3, 1, 1, 1, 1, 1,
+ GROUP(-11, 1, 1, 1, 1, 1,
2, 2, 2, 2,
1, 1, 2, 2, 2),
GROUP(
- /* IP7_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP7_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP7_23_21 [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP7_31_21 [11] RESERVED */
/* IP7_20 [1] */
FN_AUDIO_CLKB, 0,
/* IP7_19 [1] */
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 11/50] pinctrl: renesas: r8a7794: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (9 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 10/50] pinctrl: renesas: r8a7792: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 12/50] pinctrl: renesas: r8a77950: " Geert Uytterhoeven
` (39 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 201 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a7794.c | 97 ++++++---------------------
1 file changed, 21 insertions(+), 76 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c
index d1b0e651738249ca..668643553a70a71a 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7794.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7794.c
@@ -4867,7 +4867,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
- 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
+ 1, 1, 1, 1, 2, -7, 1),
GROUP(
/* IP0_31_30 [2] */
FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
@@ -4903,25 +4903,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_MMC_CLK, FN_SD2_CLK,
/* IP0_9_8 [2] */
FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
- /* IP0_7 [1] */
- 0, 0,
- /* IP0_6 [1] */
- 0, 0,
- /* IP0_5 [1] */
- 0, 0,
- /* IP0_4 [1] */
- 0, 0,
- /* IP0_3 [1] */
- 0, 0,
- /* IP0_2 [1] */
- 0, 0,
- /* IP0_1 [1] */
- 0, 0,
+ /* IP0_7_1 [7] RESERVED */
/* IP0_0 [1] */
FN_SD1_CD, FN_CAN0_RX, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
- GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
+ GROUP(2, 2, 1, 1, -1, 1, 2, 2, 2, 3, 2, 2,
3, 2, 2, 2, 2),
GROUP(
/* IP1_31_30 [2] */
@@ -4932,8 +4919,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_A4, FN_SCIFB0_TXD,
/* IP1_26 [1] */
FN_A3, FN_SCIFB0_SCK,
- /* IP1_25 [1] */
- 0, 0,
+ /* IP1_25 [1] RESERVED */
/* IP1_24 [1] */
FN_A1, FN_SCIFB1_TXD,
/* IP1_23_22 [2] */
@@ -5160,12 +5146,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(1, -1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP7_31 [1] */
FN_DREQ0_N, FN_SCIFB1_RXD,
- /* IP7_30 [1] */
- 0, 0,
+ /* IP7_30 [1] RESERVED */
/* IP7_29_27 [3] */
FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
@@ -5234,10 +5219,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
- GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
+ GROUP(-1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
GROUP(
- /* IP9_31 [1] */
- 0, 0,
+ /* IP9_31 [1] RESERVED */
/* IP9_30_28 [3] */
FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
FN_SSI_SDATA1_B, 0, 0, 0,
@@ -5307,10 +5291,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
+ GROUP(-2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
GROUP(
- /* IP11_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP11_31_30 [2] RESERVED */
/* IP11_29_27 [3] */
FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
0, 0, 0, 0,
@@ -5343,10 +5326,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
+ GROUP(-2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
GROUP(
- /* IP12_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP12_31_30 [2] RESERVED */
/* IP12_29_27 [3] */
FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
@@ -5379,18 +5361,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, FN_DREQ1_N_B, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
- GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(-5, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP13_31 [1] */
- 0, 0,
- /* IP13_30 [1] */
- 0, 0,
- /* IP13_29 [1] */
- 0, 0,
- /* IP13_28 [1] */
- 0, 0,
- /* IP13_27 [1] */
- 0, 0,
+ /* IP13_31_27 [5] RESERVED */
/* IP13_26_24 [3] */
FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
@@ -5420,23 +5393,21 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
+ GROUP(2, -1, 2, 3, -4, 1, -1,
+ 3, 3, 3, 3, 3, 2, -1),
GROUP(
/* SEL_ADG [2] */
FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
/* RESERVED [1] */
- 0, 0,
/* SEL_CAN [2] */
FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
/* SEL_DARC [3] */
FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
FN_SEL_DARC_4, 0, 0, 0,
/* RESERVED [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_ETH [1] */
FN_SEL_ETH_0, FN_SEL_ETH_1,
/* RESERVED [1] */
- 0, 0,
/* SEL_IC200 [3] */
FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
FN_SEL_I2C00_4, 0, 0, 0,
@@ -5454,12 +5425,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_I2C04_4, 0, 0, 0,
/* SEL_I2C05 [2] */
FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
- /* RESERVED [1] */
- 0, 0, ))
+ /* RESERVED [1] */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
- 2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
+ 2, 2, -1, 1, 2, 2, 2, 1, 1, -2),
GROUP(
/* SEL_IEB [2] */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
@@ -5493,7 +5463,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
FN_SEL_SCIFA5_3,
/* RESERVED [1] */
- 0, 0,
/* SEL_TMU [1] */
FN_SEL_TMU_0, FN_SEL_TMU_1,
/* SEL_TSIF0 [2] */
@@ -5506,12 +5475,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
/* SEL_HSCIF1 [1] */
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
- /* RESERVED [2] */
- 0, 0, 0, 0, ))
+ /* RESERVED [2] */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ 1, 1, -12),
GROUP(
/* SEL_SCIF0 [2] */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
@@ -5542,30 +5510,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SSI8_0, FN_SEL_SSI8_1,
/* SEL_SSI9 [1] */
FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0,
- /* RESERVED [1] */
- 0, 0, ))
+ /* RESERVED [12] */ ))
},
{ },
};
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 12/50] pinctrl: renesas: r8a77950: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (10 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 11/50] pinctrl: renesas: r8a7794: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 13/50] pinctrl: renesas: r8a77951: " Geert Uytterhoeven
` (38 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 232 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77950.c | 39 ++++++--------------------
1 file changed, 8 insertions(+), 31 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c
index 63c9f6d6468b3869..b573da6475c2c211 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77950.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77950.c
@@ -5164,10 +5164,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- GROUP(1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
- 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1),
+ GROUP(-1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
+ 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, -1),
GROUP(
- 0, 0, /* RESERVED 31 */
+ /* RESERVED 31 */
MOD_SEL0_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
@@ -5189,11 +5189,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_5_4
MOD_SEL0_3
MOD_SEL0_2_1
- 0, 0, /* RESERVED 0 */ ))
+ /* RESERVED 0 */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
- 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
+ 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
@@ -5210,7 +5210,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_11
MOD_SEL1_10
MOD_SEL1_9
- 0, 0, 0, 0, /* RESERVED 8, 7 */
+ /* RESERVED 8, 7 */
MOD_SEL1_6
MOD_SEL1_5
MOD_SEL1_4
@@ -5220,35 +5220,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
- GROUP(1, 1, 1, 1, 4, 4, 4, 4, 4, 4, 1, 2, 1),
+ GROUP(1, 1, 1, -28, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
- /* RESERVED 28 */
- 0, 0,
- /* RESERVED 27, 26, 25, 24 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 23, 22, 21, 20 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 19, 18, 17, 16 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 15, 14, 13, 12 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 11, 10, 9, 8 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 7, 6, 5, 4 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 3 */
- 0, 0,
- /* RESERVED 2, 1 */
- 0, 0, 0, 0,
+ /* RESERVED 28-1 */
MOD_SEL2_0 ))
},
{ },
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 13/50] pinctrl: renesas: r8a77951: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (11 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 12/50] pinctrl: renesas: r8a77950: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 14/50] pinctrl: renesas: r8a7796: " Geert Uytterhoeven
` (37 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 152 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77951.c | 32 ++++++++------------------
1 file changed, 9 insertions(+), 23 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c
index 9d6eef4e9d1885b9..ada84f5e8578cd9a 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77951.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
@@ -5612,8 +5612,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
- 1, 1, 1, 2, 2, 1, 2, 3),
+ GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
+ 1, 1, 1, 2, 2, 1, 2, -3),
GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
@@ -5625,7 +5625,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_19
MOD_SEL0_18_17
MOD_SEL0_16
- 0, 0, /* RESERVED 15 */
+ /* RESERVED 15 */
MOD_SEL0_14_13
MOD_SEL0_12
MOD_SEL0_11
@@ -5634,12 +5634,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_7_6
MOD_SEL0_5
MOD_SEL0_4_3
- /* RESERVED 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0 ))
+ /* RESERVED 2, 1, 0 */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
- 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
+ 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
@@ -5656,7 +5655,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_11
MOD_SEL1_10
MOD_SEL1_9
- 0, 0, 0, 0, /* RESERVED 8, 7 */
+ /* RESERVED 8, 7 */
MOD_SEL1_6
MOD_SEL1_5
MOD_SEL1_4
@@ -5666,8 +5665,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
- GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
- 1, 4, 4, 4, 3, 1),
+ GROUP(1, 1, 1, 2, 1, 3, -1, 1, 1, 1, 1, 1,
+ -16, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
@@ -5676,25 +5675,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL2_26
MOD_SEL2_25_24_23
/* RESERVED 22 */
- 0, 0,
MOD_SEL2_21
MOD_SEL2_20
MOD_SEL2_19
MOD_SEL2_18
MOD_SEL2_17
- /* RESERVED 16 */
- 0, 0,
- /* RESERVED 15, 14, 13, 12 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 11, 10, 9, 8 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 7, 6, 5, 4 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 3, 2, 1 */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 16-1 */
MOD_SEL2_0 ))
},
{ },
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 14/50] pinctrl: renesas: r8a7796: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (12 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 13/50] pinctrl: renesas: r8a77951: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 15/50] pinctrl: renesas: r8a77965: " Geert Uytterhoeven
` (36 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 148 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a7796.c | 29 ++++++++-------------------
1 file changed, 8 insertions(+), 21 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 75ea36829a70e024..ece673f0af5d5caa 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -5567,8 +5567,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
- 1, 1, 1, 2, 2, 1, 2, 3),
+ GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
+ 1, 1, 1, 2, 2, 1, 2, -3),
GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
@@ -5580,7 +5580,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_19
MOD_SEL0_18_17
MOD_SEL0_16
- 0, 0, /* RESERVED 15 */
+ /* RESERVED 15 */
MOD_SEL0_14_13
MOD_SEL0_12
MOD_SEL0_11
@@ -5589,12 +5589,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_7_6
MOD_SEL0_5
MOD_SEL0_4_3
- /* RESERVED 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0 ))
+ /* RESERVED 2, 1, 0 */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
- 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
+ 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
@@ -5611,7 +5610,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_11
MOD_SEL1_10
MOD_SEL1_9
- 0, 0, 0, 0, /* RESERVED 8, 7 */
+ /* RESERVED 8, 7 */
MOD_SEL1_6
MOD_SEL1_5
MOD_SEL1_4
@@ -5622,7 +5621,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
- 1, 4, 4, 4, 3, 1),
+ -16, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
@@ -5636,19 +5635,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL2_19
MOD_SEL2_18
MOD_SEL2_17
- /* RESERVED 16 */
- 0, 0,
- /* RESERVED 15, 14, 13, 12 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 11, 10, 9, 8 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 7, 6, 5, 4 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 3, 2, 1 */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 16-1 */
MOD_SEL2_0 ))
},
{ },
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 15/50] pinctrl: renesas: r8a77965: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (13 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 14/50] pinctrl: renesas: r8a7796: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 16/50] pinctrl: renesas: r8a77970: " Geert Uytterhoeven
` (35 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 148 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77965.c | 29 +++++++-------------------
1 file changed, 8 insertions(+), 21 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 6bb7f7543c37ca8d..b9cf1919f42e7f76 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -5808,8 +5808,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
- 1, 1, 1, 2, 2, 1, 2, 3),
+ GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
+ 1, 1, 1, 2, 2, 1, 2, -3),
GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
@@ -5821,7 +5821,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_19
MOD_SEL0_18_17
MOD_SEL0_16
- 0, 0, /* RESERVED 15 */
+ /* RESERVED 15 */
MOD_SEL0_14_13
MOD_SEL0_12
MOD_SEL0_11
@@ -5830,12 +5830,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_7_6
MOD_SEL0_5
MOD_SEL0_4_3
- /* RESERVED 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0 ))
+ /* RESERVED 2, 1, 0 */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
- 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
+ 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
@@ -5852,7 +5851,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_11
MOD_SEL1_10
MOD_SEL1_9
- 0, 0, 0, 0, /* RESERVED 8, 7 */
+ /* RESERVED 8, 7 */
MOD_SEL1_6
MOD_SEL1_5
MOD_SEL1_4
@@ -5863,7 +5862,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
- 1, 4, 4, 4, 3, 1),
+ -16, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
@@ -5877,19 +5876,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL2_19
MOD_SEL2_18
MOD_SEL2_17
- /* RESERVED 16 */
- 0, 0,
- /* RESERVED 15, 14, 13, 12 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 11, 10, 9, 8 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 7, 6, 5, 4 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 3, 2, 1 */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 16-1 */
MOD_SEL2_0 ))
},
{ },
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 16/50] pinctrl: renesas: r8a77970: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (14 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 15/50] pinctrl: renesas: r8a77965: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 17/50] pinctrl: renesas: r8a77980: " Geert Uytterhoeven
` (34 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 164 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77970.c | 14 ++------------
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c
index 94f90c13989eceb9..6c8b1e797b0822cb 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77970.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77970.c
@@ -2390,19 +2390,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1),
+ GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
- /* RESERVED 31, 30, 29, 28 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 27, 26, 25, 24 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 23, 22, 21, 20 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 19, 18, 17, 16 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 15, 14, 13, 12 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 31-12 */
MOD_SEL0_11
MOD_SEL0_10
MOD_SEL0_9
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 17/50] pinctrl: renesas: r8a77980: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (15 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 16/50] pinctrl: renesas: r8a77970: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 18/50] pinctrl: renesas: r8a77990: " Geert Uytterhoeven
` (33 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 168 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77980.c | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c
index c229a5d8fa573816..8d4d1dedaa18529e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77980.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77980.c
@@ -2832,19 +2832,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1),
+ GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, -1, 1, 1, 1),
GROUP(
- /* RESERVED 31, 30, 29, 28 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 27, 26, 25, 24 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 23, 22, 21, 20 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 19, 18, 17, 16 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 15, 14, 13, 12 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 31-12 */
MOD_SEL0_11
MOD_SEL0_10
MOD_SEL0_9
@@ -2853,7 +2843,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_6
MOD_SEL0_5
MOD_SEL0_4
- 0, 0,
+ /* RESERVED 3 */
MOD_SEL0_2
MOD_SEL0_1
MOD_SEL0_0 ))
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 18/50] pinctrl: renesas: r8a77990: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (16 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 17/50] pinctrl: renesas: r8a77980: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 19/50] pinctrl: renesas: r8a77995: " Geert Uytterhoeven
` (32 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 40 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77990.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index c273bb743d3bc098..d31b7c1d6606bd21 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -5012,11 +5012,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
+ GROUP(-1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
GROUP(
/* RESERVED 31 */
- 0, 0,
MOD_SEL0_30_29
MOD_SEL0_28
MOD_SEL0_27_26
@@ -5041,15 +5040,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
- 1, 2, 2, 2, 1, 1, 2, 1, 4),
+ GROUP(1, 1, 1, 1, -1, 1, 1, 3, 3, 1, 1, 1,
+ 1, 2, 2, 2, 1, 1, 2, 1, -4),
GROUP(
MOD_SEL1_31
MOD_SEL1_30
MOD_SEL1_29
MOD_SEL1_28
/* RESERVED 27 */
- 0, 0,
MOD_SEL1_26
MOD_SEL1_25
MOD_SEL1_24_23_22
@@ -5065,8 +5063,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_7
MOD_SEL1_6_5
MOD_SEL1_4
- /* RESERVED 3, 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
+ /* RESERVED 3, 2, 1, 0 */ ))
},
{ },
};
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 19/50] pinctrl: renesas: r8a77995: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (17 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 18/50] pinctrl: renesas: r8a77990: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 20/50] pinctrl: renesas: r8a779a0: " Geert Uytterhoeven
` (31 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 246 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77995.c | 24 ++++--------------------
1 file changed, 4 insertions(+), 20 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c
index 0cdf70dd9dea3c9c..71f6a4a79e3db95f 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -2875,11 +2875,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
- 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1),
+ GROUP(-1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, -1,
+ 1, 1, 1, 1, 1, 1, -4, 1, 1, 1, 1, 1, 1),
GROUP(
/* RESERVED 31 */
- 0, 0,
MOD_SEL0_30
MOD_SEL0_29
MOD_SEL0_28
@@ -2891,7 +2890,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_20_19
MOD_SEL0_18_17
/* RESERVED 16 */
- 0, 0,
MOD_SEL0_15
MOD_SEL0_14
MOD_SEL0_13
@@ -2899,7 +2897,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_11
MOD_SEL0_10
/* RESERVED 9, 8, 7, 6 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
MOD_SEL0_5
MOD_SEL0_4
MOD_SEL0_3
@@ -2908,7 +2905,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4),
+ GROUP(1, 1, 1, 1, 1, 1, -26),
GROUP(
MOD_SEL1_31
MOD_SEL1_30
@@ -2916,20 +2913,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_28
MOD_SEL1_27
MOD_SEL1_26
- /* RESERVED 25, 24 */
- 0, 0, 0, 0,
- /* RESERVED 23, 22, 21, 20 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 19, 18, 17, 16 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 15, 14, 13, 12 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 11, 10, 9, 8 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 7, 6, 5, 4 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 3, 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
+ /* RESERVED 25-0 */ ))
},
{ },
};
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 20/50] pinctrl: renesas: r8a779a0: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (18 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 19/50] pinctrl: renesas: r8a77995: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 21/50] pinctrl: renesas: r8a779f0: " Geert Uytterhoeven
` (30 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 140 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 4a668a04b7ca6820..081a14fbe5a4af87 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -3656,16 +3656,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32,
- GROUP(4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1),
+ GROUP(-16, 2, 2, 2, 2, 2, 2, 2, -2),
GROUP(
- /* RESERVED 31, 30, 29, 28 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 27, 26, 25, 24 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 23, 22, 21, 20 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 19, 18, 17, 16 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 31-16 */
MOD_SEL2_15_14
MOD_SEL2_13_12
MOD_SEL2_11_10
@@ -3673,8 +3666,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL2_7_6
MOD_SEL2_5_4
MOD_SEL2_3_2
- 0, 0,
- 0, 0, ))
+ /* RESERVED 1-0 */ ))
},
{ },
};
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 21/50] pinctrl: renesas: r8a779f0: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (19 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 20/50] pinctrl: renesas: r8a779a0: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 22/50] pinctrl: renesas: sh7734: " Geert Uytterhoeven
` (29 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 164 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a779f0.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index 91860608242c503b..6d7675e60cee0ab6 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1786,18 +1786,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6050900, 32,
- GROUP(4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2),
+ GROUP(-20, 2, 2, 2, 2, 2, 2),
GROUP(
- /* RESERVED 31, 30, 29, 28 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 27, 26, 25, 24 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 23, 22, 21, 20 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 19, 18, 17, 16 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 15, 14, 13, 12 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 31-12 */
MOD_SEL1_11_10
MOD_SEL1_9_8
MOD_SEL1_7_6
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 22/50] pinctrl: renesas: sh7734: Use shorthands for reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (20 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 21/50] pinctrl: renesas: r8a779f0: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 23/50] pinctrl: renesas: r8a73a4: Optimize fixed-width " Geert Uytterhoeven
` (28 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 174 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh7734.c | 94 +++++++---------------------
1 file changed, 22 insertions(+), 72 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh7734.c b/drivers/pinctrl/renesas/pfc-sh7734.c
index a4e02fc7ea34f1f5..54f60b37c211e039 100644
--- a/drivers/pinctrl/renesas/pfc-sh7734.c
+++ b/drivers/pinctrl/renesas/pfc-sh7734.c
@@ -1895,10 +1895,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
- GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3),
+ GROUP(-1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3),
GROUP(
- /* IP2_31 [1] */
- 0, 0,
+ /* IP2_31 [1] RESERVED */
/* IP2_30_28 [3] */
FN_D14, FN_TX2_B, 0, FN_FSE_A,
FN_ET0_TX_CLK_B, 0, 0, 0,
@@ -1932,10 +1931,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_FD4_A, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
- GROUP(2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2),
+ GROUP(-2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2),
GROUP(
- /* IP3_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP3_31_30 [2] RESERVED */
/* IP3_29_27 [3] */
FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A,
FN_ET0_ETXD7, 0, 0, 0,
@@ -2006,19 +2004,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ET0_ERXD7, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
- GROUP(1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3,
- 3, 3, 3),
+ GROUP(-5, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP5_31 [1] */
- 0, 0,
- /* IP5_30 [1] */
- 0, 0,
- /* IP5_29 [1] */
- 0, 0,
- /* IP5_28 [1] */
- 0, 0,
- /* IP5_27 [1] */
- 0, 0,
+ /* IP5_31_27 [5] RESERVED */
/* IP5_26_25 [2] */
FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 0,
/* IP5_24_23 [2] */
@@ -2048,25 +2036,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ET0_RX_CLK_B, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 2, 2,
- 2, 2, 2, 2, 3, 3),
+ GROUP(-8, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3),
GROUP(
- /* IP5_31 [1] */
- 0, 0,
- /* IP6_30 [1] */
- 0, 0,
- /* IP6_29 [1] */
- 0, 0,
- /* IP6_28 [1] */
- 0, 0,
- /* IP6_27 [1] */
- 0, 0,
- /* IP6_26 [1] */
- 0, 0,
- /* IP6_25 [1] */
- 0, 0,
- /* IP6_24 [1] */
- 0, 0,
+ /* IP5_31_24 [8] RESERVED */
/* IP6_23_21 [3] */
FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A,
FN_HIFD09, 0, 0, 0,
@@ -2093,10 +2065,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_TCLKA_A, FN_HIFD00, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
- GROUP(1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(-1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP7_31 [1] */
- 0, 0,
+ /* IP7_31 [1] RESERVED */
/* IP7_30_29 [2] */
FN_DU0_DB4, 0, FN_HIFINT, 0,
/* IP7_28_27 [2] */
@@ -2130,11 +2101,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_HIFD10, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
- GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2,
+ GROUP(-2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2),
GROUP(
- /* IP9_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP9_31_30 [2] RESERVED */
/* IP8_29_28 [2] */
FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
/* IP8_27_26 [2] */
@@ -2168,11 +2138,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DB5, 0, FN_HIFDREQ, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
- GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ GROUP(-2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2),
GROUP(
- /* IP9_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP9_31_30 [2] RESERVED */
/* IP9_29_28 [2] */
FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 0,
/* IP9_27_26 [2] */
@@ -2205,10 +2174,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32,
- GROUP(2, 2, 2, 1, 2, 1, 3, 3, 1, 3, 3, 3, 3, 3),
+ GROUP(-2, 2, 2, 1, 2, 1, 3, 3, 1, 3, 3, 3, 3, 3),
GROUP(
- /* IP9_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP9_31_30 [2] RESERVED */
/* IP10_29_28 [2] */
FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 0,
/* IP10_27_26 [2] */
@@ -2244,11 +2212,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_LCD_DATA15_B, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
- GROUP(3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3,
+ GROUP(-3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3,
1, 1, 1, 1),
GROUP(
- /* IP11_31_29 [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP11_31_29 [3] RESERVED */
/* IP11_28 [1] */
FN_PRESETOUT, FN_ST_CLKOUT,
/* IP11_27_26 [2] */
@@ -2286,11 +2253,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SCL1, FN_SCIF_CLK_C ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32,
- GROUP(3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2,
+ GROUP(-3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2,
2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
- /* SEL1_31_29 [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* SEL1_31_29 [3] RESERVED */
/* SEL1_28 [1] */
FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
/* SEL1_27 [1] */
@@ -2343,25 +2309,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_INTC_0, FN_SEL_INTC_1 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
- 2, 1, 2, 2, 3, 2, 3, 2, 2),
+ GROUP(-8, 1, 1, 1, 2, 2, 1, 2, 2, 3, 2, 3, 2, 2),
GROUP(
- /* SEL2_31 [1] */
- 0, 0,
- /* SEL2_30 [1] */
- 0, 0,
- /* SEL2_29 [1] */
- 0, 0,
- /* SEL2_28 [1] */
- 0, 0,
- /* SEL2_27 [1] */
- 0, 0,
- /* SEL2_26 [1] */
- 0, 0,
- /* SEL2_25 [1] */
- 0, 0,
- /* SEL2_24 [1] */
- 0, 0,
+ /* SEL2_31_24 [8] RESERVED */
/* SEL2_23 [1] */
FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
/* SEL2_22 [1] */
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 23/50] pinctrl: renesas: r8a73a4: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (21 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 22/50] pinctrl: renesas: sh7734: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 24/50] pinctrl: renesas: r8a7740: " Geert Uytterhoeven
` (27 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 126 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a73a4.c | 58 ++++++++-------------------
1 file changed, 16 insertions(+), 42 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a73a4.c b/drivers/pinctrl/renesas/pfc-r8a73a4.c
index ba3a1857f80a08c4..dbfc46fe2f277092 100644
--- a/drivers/pinctrl/renesas/pfc-r8a73a4.c
+++ b/drivers/pinctrl/renesas/pfc-r8a73a4.c
@@ -2270,15 +2270,17 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL1CR_00_0, MSEL1CR_00_1,
))
},
- { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
+ { PINMUX_CFG_REG_VAR("MSEL3CR", 0xe6058020, 32,
+ GROUP(1, -2, 1, 1, 1, -2, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, -2, 1, 1, 1, 1, -2, 1, -2, 1,
+ -1, 1, 1),
+ GROUP(
MSEL3CR_31_0, MSEL3CR_31_1,
- 0, 0,
- 0, 0,
+ /* RESERVED [2] */
MSEL3CR_28_0, MSEL3CR_28_1,
MSEL3CR_27_0, MSEL3CR_27_1,
MSEL3CR_26_0, MSEL3CR_26_1,
- 0, 0,
- 0, 0,
+ /* RESERVED [2] */
MSEL3CR_23_0, MSEL3CR_23_1,
MSEL3CR_22_0, MSEL3CR_22_1,
MSEL3CR_21_0, MSEL3CR_21_1,
@@ -2288,19 +2290,16 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL3CR_17_0, MSEL3CR_17_1,
MSEL3CR_16_0, MSEL3CR_16_1,
MSEL3CR_15_0, MSEL3CR_15_1,
- 0, 0,
- 0, 0,
+ /* RESERVED [2] */
MSEL3CR_12_0, MSEL3CR_12_1,
MSEL3CR_11_0, MSEL3CR_11_1,
MSEL3CR_10_0, MSEL3CR_10_1,
MSEL3CR_09_0, MSEL3CR_09_1,
- 0, 0,
- 0, 0,
+ /* RESERVED [2] */
MSEL3CR_06_0, MSEL3CR_06_1,
- 0, 0,
- 0, 0,
+ /* RESERVED [2] */
MSEL3CR_03_0, MSEL3CR_03_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL3CR_01_0, MSEL3CR_01_1,
MSEL3CR_00_0, MSEL3CR_00_1,
))
@@ -2375,37 +2374,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
))
},
- { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("MSEL8CR", 0xe6058034, 32,
+ GROUP(-15, 1, -14, 1, 1),
+ GROUP(
+ /* RESERVED [15] */
MSEL8CR_16_0, MSEL8CR_16_1,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [14] */
MSEL8CR_01_0, MSEL8CR_01_1,
MSEL8CR_00_0, MSEL8CR_00_1,
))
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 24/50] pinctrl: renesas: r8a7740: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (22 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 23/50] pinctrl: renesas: r8a73a4: Optimize fixed-width " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 25/50] pinctrl: renesas: r8a77470: " Geert Uytterhoeven
` (26 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 230 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a7740.c | 74 ++++++++++++++-------------
1 file changed, 39 insertions(+), 35 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7740.c b/drivers/pinctrl/renesas/pfc-r8a7740.c
index e8b9fb74a802ac03..6dcd39918daf96bc 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7740.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7740.c
@@ -3250,89 +3250,93 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(210, 0xe60530d2), /* PORT210CR */
PORTCR(211, 0xe60530d3), /* PORT211CR */
- { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
+ { PINMUX_CFG_REG_VAR("MSEL1CR", 0xe605800c, 32,
+ GROUP(1, 1, 1, 1, 1, 1, -9, 1, 1, 1, 1, 1,
+ -2, 1, -1, 1, 1, 1, 1, 1, 1, -1, 1),
+ GROUP(
MSEL1CR_31_0, MSEL1CR_31_1,
MSEL1CR_30_0, MSEL1CR_30_1,
MSEL1CR_29_0, MSEL1CR_29_1,
MSEL1CR_28_0, MSEL1CR_28_1,
MSEL1CR_27_0, MSEL1CR_27_1,
MSEL1CR_26_0, MSEL1CR_26_1,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED [9] */
MSEL1CR_16_0, MSEL1CR_16_1,
MSEL1CR_15_0, MSEL1CR_15_1,
MSEL1CR_14_0, MSEL1CR_14_1,
MSEL1CR_13_0, MSEL1CR_13_1,
MSEL1CR_12_0, MSEL1CR_12_1,
- 0, 0, 0, 0,
+ /* RESERVED [2] */
MSEL1CR_9_0, MSEL1CR_9_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL1CR_7_0, MSEL1CR_7_1,
MSEL1CR_6_0, MSEL1CR_6_1,
MSEL1CR_5_0, MSEL1CR_5_1,
MSEL1CR_4_0, MSEL1CR_4_1,
MSEL1CR_3_0, MSEL1CR_3_1,
MSEL1CR_2_0, MSEL1CR_2_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL1CR_0_0, MSEL1CR_0_1,
))
},
- { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("MSEL3CR", 0xE6058020, 32,
+ GROUP(-16, 1, -8, 1, -6),
+ GROUP(
+ /* RESERVED [16] */
MSEL3CR_15_0, MSEL3CR_15_1,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED [8] */
MSEL3CR_6_0, MSEL3CR_6_1,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0,
+ /* RESERVED [6] */
))
},
- { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("MSEL4CR", 0xE6058024, 32,
+ GROUP(-12, 1, 1, -2, 1, -4, 1, -3, 1, -1, 1, -2,
+ 1, -1),
+ GROUP(
+ /* RESERVED [12] */
MSEL4CR_19_0, MSEL4CR_19_1,
MSEL4CR_18_0, MSEL4CR_18_1,
- 0, 0, 0, 0,
+ /* RESERVED [2] */
MSEL4CR_15_0, MSEL4CR_15_1,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED [4] */
MSEL4CR_10_0, MSEL4CR_10_1,
- 0, 0, 0, 0, 0, 0,
+ /* RESERVED [3] */
MSEL4CR_6_0, MSEL4CR_6_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL4CR_4_0, MSEL4CR_4_1,
- 0, 0, 0, 0,
+ /* RESERVED [2] */
MSEL4CR_1_0, MSEL4CR_1_1,
- 0, 0,
+ /* RESERVED [1] */
))
},
- { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1, GROUP(
+ { PINMUX_CFG_REG_VAR("MSEL5CR", 0xE6058028, 32,
+ GROUP(1, 1, 1, -1, 1, -1, 1, -1, 1, -1, 1,
+ -1, 1, -1, 1, -1, 1, 1, 1, 1, 1, 1,
+ -1, 1, 1, 1, 1, 1, 1, 1, -1, 1),
+ GROUP(
MSEL5CR_31_0, MSEL5CR_31_1,
MSEL5CR_30_0, MSEL5CR_30_1,
MSEL5CR_29_0, MSEL5CR_29_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL5CR_27_0, MSEL5CR_27_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL5CR_25_0, MSEL5CR_25_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL5CR_23_0, MSEL5CR_23_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL5CR_21_0, MSEL5CR_21_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL5CR_19_0, MSEL5CR_19_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL5CR_17_0, MSEL5CR_17_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL5CR_15_0, MSEL5CR_15_1,
MSEL5CR_14_0, MSEL5CR_14_1,
MSEL5CR_13_0, MSEL5CR_13_1,
MSEL5CR_12_0, MSEL5CR_12_1,
MSEL5CR_11_0, MSEL5CR_11_1,
MSEL5CR_10_0, MSEL5CR_10_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL5CR_8_0, MSEL5CR_8_1,
MSEL5CR_7_0, MSEL5CR_7_1,
MSEL5CR_6_0, MSEL5CR_6_1,
@@ -3340,7 +3344,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL5CR_4_0, MSEL5CR_4_1,
MSEL5CR_3_0, MSEL5CR_3_1,
MSEL5CR_2_0, MSEL5CR_2_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL5CR_0_0, MSEL5CR_0_1,
))
},
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 25/50] pinctrl: renesas: r8a77470: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (23 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 24/50] pinctrl: renesas: r8a7740: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 26/50] pinctrl: renesas: r8a7779: " Geert Uytterhoeven
` (25 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 70 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77470.c | 56 +++++++++-----------------
1 file changed, 20 insertions(+), 36 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77470.c b/drivers/pinctrl/renesas/pfc-r8a77470.c
index 15a6dffdffcfd581..b5725c3ed2b60e88 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77470.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77470.c
@@ -2485,16 +2485,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR0", 0xE6060004, 32,
+ GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP0_31_23 RESERVED */
GP_0_22_FN, FN_MMC0_D7,
GP_0_21_FN, FN_MMC0_D6,
GP_0_20_FN, FN_IP1_7_4,
@@ -2519,16 +2514,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_1_FN, FN_USB0_OVC,
GP_0_0_FN, FN_USB0_PWEN, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
+ GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP1_31_23 RESERVED */
GP_1_22_FN, FN_IP4_3_0,
GP_1_21_FN, FN_IP3_31_28,
GP_1_20_FN, FN_IP3_27_24,
@@ -2587,22 +2577,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, FN_IP4_11_8,
GP_2_0_FN, FN_IP4_7_4, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR3", 0xE6060010, 32,
+ GROUP(-2, 1, 1, -10, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP3_31_30 RESERVED */
GP_3_29_FN, FN_IP10_19_16,
GP_3_28_FN, FN_IP10_15_12,
GP_3_27_FN, FN_IP10_11_8,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* GP3_26_17 RESERVED */
GP_3_16_FN, FN_IP10_7_4,
GP_3_15_FN, FN_IP10_3_0,
GP_3_14_FN, FN_IP9_31_28,
@@ -3139,9 +3122,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
0, 0, 0, 0, 0, 0, ))
},
- { PINMUX_CFG_REG("IPSR17", 0xE6060084, 32, 4, GROUP(
- /* IP17_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
+ GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
+ GROUP(
+ /* IP17_31_28 [4] RESERVED */
/* IP17_27_24 [4] */
FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 26/50] pinctrl: renesas: r8a7779: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (24 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 25/50] pinctrl: renesas: r8a77470: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 27/50] pinctrl: renesas: r8a7792: " Geert Uytterhoeven
` (24 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 81 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a7779.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7779.c b/drivers/pinctrl/renesas/pfc-r8a7779.c
index e674549193250b3b..fcc8ea48881fb961 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7779.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7779.c
@@ -3300,13 +3300,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_1_FN, FN_A2,
GP_5_0_FN, FN_A1 ))
},
- { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR6", 0xfffc001c, 32,
+ GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP6_31_9 RESERVED */
GP_6_8_FN, FN_IP3_20,
GP_6_7_FN, FN_IP3_19,
GP_6_6_FN, FN_IP3_18,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 27/50] pinctrl: renesas: r8a7792: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (25 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 26/50] pinctrl: renesas: r8a7779: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 28/50] pinctrl: renesas: r8a77950: " Geert Uytterhoeven
` (23 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 257 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a7792.c | 141 +++++++-------------------
1 file changed, 35 insertions(+), 106 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c
index 282ff1dd58a7493e..808a85d62415399f 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7792.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7792.c
@@ -1999,16 +1999,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_1_FN, FN_IP0_1,
GP_0_0_FN, FN_IP0_0 ))
},
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
+ GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP1_31_23 RESERVED */
GP_1_22_FN, FN_DU1_CDE,
GP_1_21_FN, FN_DU1_DISP,
GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
@@ -2101,22 +2096,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, FN_A17,
GP_3_0_FN, FN_A16 ))
},
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060014, 32,
+ GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP4_31_17 RESERVED */
GP_4_16_FN, FN_VI0_FIELD,
GP_4_15_FN, FN_VI0_D11_G3_Y3,
GP_4_14_FN, FN_VI0_D10_G2_Y2,
@@ -2135,22 +2119,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_1_FN, FN_VI0_CLKENB,
GP_4_0_FN, FN_VI0_CLK ))
},
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060018, 32,
+ GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP5_31_17 RESERVED */
GP_5_16_FN, FN_VI1_FIELD,
GP_5_15_FN, FN_VI1_D11_G3_Y3,
GP_5_14_FN, FN_VI1_D10_G2_Y2,
@@ -2169,22 +2142,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_1_FN, FN_VI1_CLKENB,
GP_5_0_FN, FN_VI1_CLK ))
},
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR6", 0xE606001C, 32,
+ GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP6_31_17 RESERVED */
GP_6_16_FN, FN_IP2_16,
GP_6_15_FN, FN_IP2_15,
GP_6_14_FN, FN_IP2_14,
@@ -2203,22 +2165,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, FN_IP2_1,
GP_6_0_FN, FN_IP2_0 ))
},
- { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR7", 0xE6060020, 32,
+ GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP7_31_17 RESERVED */
GP_7_16_FN, FN_VI3_FIELD,
GP_7_15_FN, FN_IP3_14,
GP_7_14_FN, FN_VI3_D10_Y2,
@@ -2237,22 +2188,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_7_1_FN, FN_IP3_1,
GP_7_0_FN, FN_IP3_0 ))
},
- { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR8", 0xE6060024, 32,
+ GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP8_31_17 RESERVED */
GP_8_16_FN, FN_IP4_24,
GP_8_15_FN, FN_IP4_23,
GP_8_14_FN, FN_IP4_22,
@@ -2271,22 +2211,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_8_1_FN, FN_IP4_0,
GP_8_0_FN, FN_VI4_CLK ))
},
- { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR9", 0xE6060028, 32,
+ GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP9_31_17 RESERVED */
GP_9_16_FN, FN_VI5_FIELD,
GP_9_15_FN, FN_VI5_D11_Y3,
GP_9_14_FN, FN_VI5_D10_Y2,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 28/50] pinctrl: renesas: r8a77950: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (26 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 27/50] pinctrl: renesas: r8a7792: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 29/50] pinctrl: renesas: r8a77951: " Geert Uytterhoeven
` (22 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 473 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77950.c | 131 ++++++-------------------
1 file changed, 28 insertions(+), 103 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c
index b573da6475c2c211..4c543ec3a8639393 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77950.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77950.c
@@ -4701,23 +4701,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
+ GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP0_31_16 RESERVED */
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
@@ -4769,24 +4757,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
+ GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1),
+ GROUP(
+ /* GP2_31_15 RESERVED */
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
@@ -4803,23 +4778,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
+ GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP3_31_16 RESERVED */
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
@@ -4837,21 +4800,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
+ GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP4_31_18 RESERVED */
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
@@ -4939,35 +4892,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
- { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
+ GROUP(-28, 1, 1, 1, 1),
+ GROUP(
+ /* GP7_31_4 RESERVED */
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
@@ -5148,13 +5076,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP16_7_4
IP16_3_0 ))
},
- { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
- /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("IPSR17", 0xe6060244, 32,
+ GROUP(-24, 4, 4),
+ GROUP(
+ /* IP17_31_8 RESERVED */
IP17_7_4
IP17_3_0 ))
},
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 29/50] pinctrl: renesas: r8a77951: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (27 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 28/50] pinctrl: renesas: r8a77950: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 30/50] pinctrl: renesas: r8a77965: " Geert Uytterhoeven
` (21 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 496 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77951.c | 137 ++++++-------------------
1 file changed, 32 insertions(+), 105 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c
index ada84f5e8578cd9a..d4d271dff055462d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77951.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
@@ -5139,23 +5139,11 @@ static const struct {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
+ GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP0_31_16 RESERVED */
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
@@ -5207,24 +5195,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
+ GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1),
+ GROUP(
+ /* GP2_31_15 RESERVED */
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
@@ -5241,23 +5216,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
+ GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP3_31_16 RESERVED */
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
@@ -5275,21 +5238,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
+ GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP4_31_18 RESERVED */
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
@@ -5377,35 +5330,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
- { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
+ GROUP(-28, 1, 1, 1, 1),
+ GROUP(
+ /* GP7_31_4 RESERVED */
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
@@ -5486,12 +5414,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_7_4
IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
+ { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
+ GROUP(4, 4, 4, 4, -4, 4, 4, 4),
+ GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_19_16
- /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP7_15_12 RESERVED */
IP7_11_8
IP7_7_4
IP7_3_0 ))
@@ -5596,13 +5526,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP17_7_4
IP17_3_0 ))
},
- { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
- /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
+ GROUP(-24, 4, 4),
+ GROUP(
+ /* IP18_31_8 RESERVED */
IP18_7_4
IP18_3_0 ))
},
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 30/50] pinctrl: renesas: r8a77965: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (28 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 29/50] pinctrl: renesas: r8a77951: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 31/50] pinctrl: renesas: r8a7796: " Geert Uytterhoeven
` (20 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 496 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77965.c | 137 ++++++-------------------
1 file changed, 32 insertions(+), 105 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c
index b9cf1919f42e7f76..acd0bdf1301844ef 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -5335,23 +5335,11 @@ static const struct {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
+ GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP0_31_16 RESERVED */
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
@@ -5403,24 +5391,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
+ GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1),
+ GROUP(
+ /* GP2_31_15 RESERVED */
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
@@ -5437,23 +5412,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
+ GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP3_31_16 RESERVED */
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
@@ -5471,21 +5434,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
+ GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP4_31_18 RESERVED */
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
@@ -5573,35 +5526,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
- { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
+ GROUP(-28, 1, 1, 1, 1),
+ GROUP(
+ /* GP7_31_4 RESERVED */
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
@@ -5682,12 +5610,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_7_4
IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
+ { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
+ GROUP(4, 4, 4, 4, -4, 4, 4, 4),
+ GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_19_16
- /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP7_15_12 RESERVED */
IP7_11_8
IP7_7_4
IP7_3_0 ))
@@ -5792,13 +5722,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP17_7_4
IP17_3_0 ))
},
- { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
- /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
+ GROUP(-24, 4, 4),
+ GROUP(
+ /* IP18_31_8 RESERVED */
IP18_7_4
IP18_3_0 ))
},
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 31/50] pinctrl: renesas: r8a7796: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (29 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 30/50] pinctrl: renesas: r8a77965: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 32/50] pinctrl: renesas: r8a77970: " Geert Uytterhoeven
` (19 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 496 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a7796.c | 137 ++++++--------------------
1 file changed, 32 insertions(+), 105 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
index ece673f0af5d5caa..a0096ef5e68dc6d6 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -5094,23 +5094,11 @@ static const struct {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
+ GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP0_31_16 RESERVED */
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
@@ -5162,24 +5150,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
+ GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1),
+ GROUP(
+ /* GP2_31_15 RESERVED */
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
@@ -5196,23 +5171,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
+ GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP3_31_16 RESERVED */
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
@@ -5230,21 +5193,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
+ GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP4_31_18 RESERVED */
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
@@ -5332,35 +5285,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
- { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
+ GROUP(-28, 1, 1, 1, 1),
+ GROUP(
+ /* GP7_31_4 RESERVED */
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
@@ -5441,12 +5369,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_7_4
IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
+ { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
+ GROUP(4, 4, 4, 4, -4, 4, 4, 4),
+ GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_19_16
- /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP7_15_12 RESERVED */
IP7_11_8
IP7_7_4
IP7_3_0 ))
@@ -5551,13 +5481,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP17_7_4
IP17_3_0 ))
},
- { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
- /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
+ GROUP(-24, 4, 4),
+ GROUP(
+ /* IP18_31_8 RESERVED */
IP18_7_4
IP18_3_0 ))
},
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 32/50] pinctrl: renesas: r8a77970: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (30 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 31/50] pinctrl: renesas: r8a7796: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 33/50] pinctrl: renesas: r8a77980: " Geert Uytterhoeven
` (18 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 268 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77970.c | 122 ++++++-------------------
1 file changed, 29 insertions(+), 93 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c
index 6c8b1e797b0822cb..4a7803eaafaa8abf 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77970.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77970.c
@@ -231,7 +231,6 @@
#define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define PINMUX_GPSR \
\
@@ -290,8 +289,7 @@ FM(IP8_11_8) IP8_11_8 \
FM(IP8_15_12) IP8_15_12 \
FM(IP8_19_16) IP8_19_16 \
FM(IP8_23_20) IP8_23_20 \
-FM(IP8_27_24) IP8_27_24 \
-FM(IP8_31_28) IP8_31_28
+FM(IP8_27_24) IP8_27_24
/* MOD_SEL0 */ /* 0 */ /* 1 */
#define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
@@ -2085,17 +2083,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
+ GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP0_31_22 RESERVED */
GP_0_21_FN, GPSR0_21,
GP_0_20_FN, GPSR0_20,
GP_0_19_FN, GPSR0_19,
@@ -2153,22 +2145,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
+ GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP2_31_17 RESERVED */
GP_2_16_FN, GPSR2_16,
GP_2_15_FN, GPSR2_15,
GP_2_14_FN, GPSR2_14,
@@ -2187,22 +2168,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
+ GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP3_31_17 RESERVED */
GP_3_16_FN, GPSR3_16,
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
@@ -2221,33 +2191,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
+ GROUP(-26, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP4_31_6 RESERVED */
GP_4_5_FN, GPSR4_5,
GP_4_4_FN, GPSR4_4,
GP_4_3_FN, GPSR4_3,
@@ -2255,24 +2202,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
+ GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1),
+ GROUP(
+ /* GP5_31_15 RESERVED */
GP_5_14_FN, GPSR5_14,
GP_5_13_FN, GPSR5_13,
GP_5_12_FN, GPSR5_12,
@@ -2374,8 +2308,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP7_7_4
IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
- IP8_31_28
+ { PINMUX_CFG_REG_VAR("IPSR8", 0xe6060220, 32,
+ GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
+ GROUP(
+ /* IP8_31_28 RESERVED */
IP8_27_24
IP8_23_20
IP8_19_16
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 33/50] pinctrl: renesas: r8a77980: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (31 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 32/50] pinctrl: renesas: r8a77970: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 34/50] pinctrl: renesas: r8a77990: " Geert Uytterhoeven
` (17 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 198 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77980.c | 91 ++++++++------------------
1 file changed, 28 insertions(+), 63 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c
index 8d4d1dedaa18529e..ac03309c5c0c9756 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77980.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77980.c
@@ -278,9 +278,6 @@
#define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define PINMUX_GPSR \
\
@@ -340,9 +337,9 @@ FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
-FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \
-FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \
-FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28
+FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 \
+FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 \
+FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28
/* MOD_SEL0 */ /* 0 */ /* 1 */
#define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
@@ -2507,17 +2504,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
+ GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP0_31_22 RESERVED */
GP_0_21_FN, GPSR0_21,
GP_0_20_FN, GPSR0_20,
GP_0_19_FN, GPSR0_19,
@@ -2609,22 +2600,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
+ GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP3_31_17 RESERVED */
GP_3_16_FN, GPSR3_16,
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
@@ -2643,14 +2623,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
+ GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1),
+ GROUP(
+ /* GP4_31_25 RESERVED */
GP_4_24_FN, GPSR4_24,
GP_4_23_FN, GPSR4_23,
GP_4_22_FN, GPSR4_22,
@@ -2677,24 +2655,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
+ GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1),
+ GROUP(
+ /* GP5_31_15 RESERVED */
GP_5_14_FN, GPSR5_14,
GP_5_13_FN, GPSR5_13,
GP_5_12_FN, GPSR5_12,
@@ -2816,10 +2781,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP9_7_4
IP9_3_0 ))
},
- { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
- IP10_31_28
- IP10_27_24
- IP10_23_20
+ { PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32,
+ GROUP(-12, 4, 4, 4, 4, 4),
+ GROUP(
+ /* IP10_31_20 RESERVED */
IP10_19_16
IP10_15_12
IP10_11_8
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 34/50] pinctrl: renesas: r8a77990: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (32 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 33/50] pinctrl: renesas: r8a77980: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 35/50] pinctrl: renesas: r8a77995: " Geert Uytterhoeven
` (16 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 226 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77990.c | 121 ++++++-------------------
1 file changed, 29 insertions(+), 92 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index d31b7c1d6606bd21..b0936962fad709f1 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -4603,21 +4603,11 @@ static const struct {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
+ GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP0_31_18 RESERVED */
GP_0_17_FN, GPSR0_17,
GP_0_16_FN, GPSR0_16,
GP_0_15_FN, GPSR0_15,
@@ -4637,16 +4627,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR1", 0xe6060104, 32,
+ GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP1_31_23 RESERVED */
GP_1_22_FN, GPSR1_22,
GP_1_21_FN, GPSR1_21,
GP_1_20_FN, GPSR1_20,
@@ -4705,23 +4690,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
+ GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP3_31_16 RESERVED */
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
@@ -4739,28 +4712,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
+ GROUP(-21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP4_31_11 RESERVED */
GP_4_10_FN, GPSR4_10,
GP_4_9_FN, GPSR4_9,
GP_4_8_FN, GPSR4_8,
@@ -4773,19 +4728,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
+ GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP5_31_20 RESERVED */
GP_5_19_FN, GPSR5_19,
GP_5_18_FN, GPSR5_18,
GP_5_17_FN, GPSR5_17,
@@ -4807,21 +4754,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,
+ GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP6_31_18 RESERVED */
GP_6_17_FN, GPSR6_17,
GP_6_16_FN, GPSR6_16,
GP_6_15_FN, GPSR6_15,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 35/50] pinctrl: renesas: r8a77995: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (33 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 34/50] pinctrl: renesas: r8a77990: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 36/50] pinctrl: renesas: r8a779a0: " Geert Uytterhoeven
` (15 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 422 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77995.c | 107 +++++--------------------
1 file changed, 22 insertions(+), 85 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c
index 71f6a4a79e3db95f..d949ae59c757924d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -2486,30 +2486,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
+ GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP0_31_9 RESERVED */
GP_0_8_FN, GPSR0_8,
GP_0_7_FN, GPSR0_7,
GP_0_6_FN, GPSR0_6,
@@ -2588,29 +2568,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
+ GROUP(-22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP3_31_10 RESERVED */
GP_3_9_FN, GPSR3_9,
GP_3_8_FN, GPSR3_8,
GP_3_7_FN, GPSR3_7,
@@ -2656,18 +2617,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
+ GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP5_31_21 RESERVED */
GP_5_20_FN, GPSR5_20,
GP_5_19_FN, GPSR5_19,
GP_5_18_FN, GPSR5_18,
@@ -2690,25 +2644,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,
+ GROUP(-18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1),
+ GROUP(
+ /* GP6_31_14 RESERVED */
GP_6_13_FN, GPSR6_13,
GP_6_12_FN, GPSR6_12,
GP_6_11_FN, GPSR6_11,
@@ -2859,13 +2799,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP12_7_4
IP12_3_0 ))
},
- { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
- /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("IPSR13", 0xe6060234, 32,
+ GROUP(-24, 4, 4),
+ GROUP(
+ /* IP13_31_8 RESERVED */
IP13_7_4
IP13_3_0 ))
},
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 36/50] pinctrl: renesas: r8a779a0: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (34 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 35/50] pinctrl: renesas: r8a77995: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 37/50] pinctrl: renesas: r8a779f0: " Geert Uytterhoeven
` (14 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 556 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 203 +++++++++----------------
1 file changed, 72 insertions(+), 131 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 081a14fbe5a4af87..70551ba8b524656d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -389,7 +389,6 @@
#define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -420,11 +419,8 @@
#define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
-#define IP0SR3_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR3_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -435,8 +431,6 @@
#define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -457,14 +451,10 @@
#define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
-#define IP2SR4_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR4_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR4_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR4_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -485,14 +475,10 @@
#define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
-#define IP2SR5_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR5_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR5_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR5_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define PINMUX_GPSR \
\
@@ -537,7 +523,7 @@ FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2
FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \
FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \
-FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \
+FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
\
FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
@@ -548,32 +534,32 @@ FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2
FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \
FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \
\
-FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 \
+ FM(IP1SR3_3_0) IP1SR3_3_0 \
FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \
FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \
-FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 \
-FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 \
+ FM(IP1SR3_15_12) IP1SR3_15_12 \
+ FM(IP1SR3_19_16) IP1SR3_19_16 \
FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \
-FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 \
-FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 \
+FM(IP0SR3_27_24) IP0SR3_27_24 \
+FM(IP0SR3_31_28) IP0SR3_31_28 \
\
-FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 \
+FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 \
FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
-FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
-FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
-FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
+FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 \
+FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 \
+FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 \
\
-FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
+FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 \
FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
-FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 FM(IP2SR5_23_20) IP2SR5_23_20 \
-FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2SR5_27_24 \
-FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28
+FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \
+FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \
+FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28
/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
#define MOD_SEL2_15_14 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3)
@@ -3223,14 +3209,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6050840, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR2", 0xe6050840, 32,
+ GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP2_31_25 RESERVED */
GP_2_24_FN, GPSR2_24,
GP_2_23_FN, GPSR2_23,
GP_2_22_FN, GPSR2_22,
@@ -3257,22 +3240,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe6058840, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR3", 0xe6058840, 32,
+ GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP3_31_17 RESERVED */
GP_3_16_FN, GPSR3_16,
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
@@ -3325,18 +3297,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060840, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060840, 32,
+ GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP5_31_21 RESERVED */
GP_5_20_FN, GPSR5_20,
GP_5_19_FN, GPSR5_19,
GP_5_18_FN, GPSR5_18,
@@ -3359,18 +3324,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6068040, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR6", 0xe6068040, 32,
+ GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP6_31_21 RESERVED */
GP_6_20_FN, GPSR6_20,
GP_6_19_FN, GPSR6_19,
GP_6_18_FN, GPSR6_18,
@@ -3393,18 +3351,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
- { PINMUX_CFG_REG("GPSR7", 0xe6068840, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR7", 0xe6068840, 32,
+ GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP7_31_21 RESERVED */
GP_7_20_FN, GPSR7_20,
GP_7_19_FN, GPSR7_19,
GP_7_18_FN, GPSR7_18,
@@ -3427,18 +3378,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_7_1_FN, GPSR7_1,
GP_7_0_FN, GPSR7_0, ))
},
- { PINMUX_CFG_REG("GPSR8", 0xe6069040, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR8", 0xe6069040, 32,
+ GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP8_31_21 RESERVED */
GP_8_20_FN, GPSR8_20,
GP_8_19_FN, GPSR8_19,
GP_8_18_FN, GPSR8_18,
@@ -3461,18 +3405,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_8_1_FN, GPSR8_1,
GP_8_0_FN, GPSR8_0, ))
},
- { PINMUX_CFG_REG("GPSR9", 0xe6069840, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR9", 0xe6069840, 32,
+ GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP9_31_21 RESERVED */
GP_9_20_FN, GPSR9_20,
GP_9_19_FN, GPSR9_19,
GP_9_18_FN, GPSR9_18,
@@ -3530,8 +3467,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP2SR1_7_4
IP2SR1_3_0))
},
- { PINMUX_CFG_REG("IP3SR1", 0xe605006c, 32, 4, GROUP(
- IP3SR1_31_28
+ { PINMUX_CFG_REG_VAR("IP3SR1", 0xe605006c, 32,
+ GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
+ GROUP(
+ /* IP3SR1_31_28 RESERVED */
IP3SR1_27_24
IP3SR1_23_20
IP3SR1_19_16
@@ -3570,19 +3509,21 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP2SR2_7_4
IP2SR2_3_0))
},
- { PINMUX_CFG_REG("IP0SR3", 0xe6058860, 32, 4, GROUP(
+ { PINMUX_CFG_REG_VAR("IP0SR3", 0xe6058860, 32,
+ GROUP(4, 4, 4, -8, 4, 4, -4),
+ GROUP(
IP0SR3_31_28
IP0SR3_27_24
IP0SR3_23_20
- IP0SR3_19_16
- IP0SR3_15_12
+ /* IP0SR3_19_12 RESERVED */
IP0SR3_11_8
IP0SR3_7_4
- IP0SR3_3_0))
+ /* IP0SR3_3_0 RESERVED */ ))
},
- { PINMUX_CFG_REG("IP1SR3", 0xe6058864, 32, 4, GROUP(
- IP1SR3_31_28
- IP1SR3_27_24
+ { PINMUX_CFG_REG_VAR("IP1SR3", 0xe6058864, 32,
+ GROUP(-8, 4, 4, 4, 4, 4, 4),
+ GROUP(
+ /* IP1SR3_31_24 RESERVED */
IP1SR3_23_20
IP1SR3_19_16
IP1SR3_15_12
@@ -3610,15 +3551,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP1SR4_7_4
IP1SR4_3_0))
},
- { PINMUX_CFG_REG("IP2SR4", 0xe6060068, 32, 4, GROUP(
- IP2SR4_31_28
- IP2SR4_27_24
- IP2SR4_23_20
+ { PINMUX_CFG_REG_VAR("IP2SR4", 0xe6060068, 32,
+ GROUP(-12, 4, 4, 4, 4, -4),
+ GROUP(
+ /* IP2SR4_31_20 RESERVED */
IP2SR4_19_16
IP2SR4_15_12
IP2SR4_11_8
IP2SR4_7_4
- IP2SR4_3_0))
+ /* IP2SR4_3_0 RESERVED */ ))
},
{ PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP(
IP0SR5_31_28
@@ -3640,15 +3581,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP1SR5_7_4
IP1SR5_3_0))
},
- { PINMUX_CFG_REG("IP2SR5", 0xe6060868, 32, 4, GROUP(
- IP2SR5_31_28
- IP2SR5_27_24
- IP2SR5_23_20
+ { PINMUX_CFG_REG_VAR("IP2SR5", 0xe6060868, 32,
+ GROUP(-12, 4, 4, 4, 4, -4),
+ GROUP(
+ /* IP2SR5_31_20 RESERVED */
IP2SR5_19_16
IP2SR5_15_12
IP2SR5_11_8
IP2SR5_7_4
- IP2SR5_3_0))
+ /* IP2SR5_3_0 RESERVED */ ))
},
#undef F_
#undef FM
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 37/50] pinctrl: renesas: r8a779f0: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (35 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 36/50] pinctrl: renesas: r8a779a0: " Geert Uytterhoeven
@ 2022-04-13 17:23 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 38/50] pinctrl: renesas: sh7203: " Geert Uytterhoeven
` (13 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:23 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 183 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a779f0.c | 87 ++++++++------------------
1 file changed, 27 insertions(+), 60 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index 6d7675e60cee0ab6..69f3abca1e22b2b5 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -144,9 +144,6 @@
#define IP2SR0_11_8 FM(IRQ1) F_(0, 0) F_(0, 0) FM(MSIOF1_SS2) F_(0, 0) FM(TSN0_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR0_15_12 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN1_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR0_19_16 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
#define IP0SR1_3_0 FM(GP1_00) FM(TCLK1) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -192,9 +189,9 @@ FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4
FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \
FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 FM(IP2SR0_15_12) IP2SR0_15_12 \
FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 FM(IP2SR0_19_16) IP2SR0_19_16 \
-FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 FM(IP2SR0_23_20) IP2SR0_23_20 \
-FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 FM(IP2SR0_27_24) IP2SR0_27_24 \
-FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 FM(IP2SR0_31_28) IP2SR0_31_28 \
+FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \
+FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
+FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \
\
FM(IP0SR1_3_0) IP0SR1_3_0 \
FM(IP0SR1_7_4) IP0SR1_7_4 \
@@ -1599,18 +1596,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6050040, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR0", 0xe6050040, 32,
+ GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP0_31_21 RESERVED */
GP_0_20_FN, GPSR0_20,
GP_0_19_FN, GPSR0_19,
GP_0_18_FN, GPSR0_18,
@@ -1633,14 +1623,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6050840, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR1", 0xe6050840, 32,
+ GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP1_31_25 RESERVED */
GP_1_24_FN, GPSR1_24,
GP_1_23_FN, GPSR1_23,
GP_1_22_FN, GPSR1_22,
@@ -1667,22 +1654,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6051040, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR2", 0xe6051040, 32,
+ GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP2_31_17 RESERVED */
GP_2_16_FN, GPSR2_16,
GP_2_15_FN, GPSR2_15,
GP_2_14_FN, GPSR2_14,
@@ -1701,20 +1677,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe6051840, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR3", 0xe6051840, 32,
+ GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP3_31_19 RESERVED */
GP_3_18_FN, GPSR3_18,
GP_3_17_FN, GPSR3_17,
GP_3_16_FN, GPSR3_16,
@@ -1760,10 +1727,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP1SR0_7_4
IP1SR0_3_0))
},
- { PINMUX_CFG_REG("IP2SR0", 0xe6050068, 32, 4, GROUP(
- IP2SR0_31_28
- IP2SR0_27_24
- IP2SR0_23_20
+ { PINMUX_CFG_REG_VAR("IP2SR0", 0xe6050068, 32,
+ GROUP(-12, 4, 4, 4, 4, 4),
+ GROUP(
+ /* IP2SR0_31_20 RESERVED */
IP2SR0_19_16
IP2SR0_15_12
IP2SR0_11_8
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 38/50] pinctrl: renesas: sh7203: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (36 preceding siblings ...)
2022-04-13 17:23 ` [PATCH 37/50] pinctrl: renesas: r8a779f0: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 39/50] pinctrl: renesas: sh7264: " Geert Uytterhoeven
` (12 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 281 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh7203.c | 53 +++++++++++-----------------
1 file changed, 21 insertions(+), 32 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh7203.c b/drivers/pinctrl/renesas/pfc-sh7203.c
index 3986802b448a265c..19735746b1bb2157 100644
--- a/drivers/pinctrl/renesas/pfc-sh7203.c
+++ b/drivers/pinctrl/renesas/pfc-sh7203.c
@@ -1072,31 +1072,20 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("PBIORL", 0xfffe3886, 16,
+ GROUP(-4, 1, 1, 1, 1, -8),
+ GROUP(
+ /* RESERVED [4] */
PB11_IN, PB11_OUT,
PB10_IN, PB10_OUT,
PB9_IN, PB9_OUT,
PB8_IN, PB8_OUT,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0 ))
+ /* RESERVED [8] */ ))
},
- { PINMUX_CFG_REG("PBCRL4", 0xfffe3890, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
+ { PINMUX_CFG_REG_VAR("PBCRL4", 0xfffe3890, 16,
+ GROUP(-12, 4),
+ GROUP(
+ /* RESERVED [12] */
PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
@@ -1139,13 +1128,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
- { PINMUX_CFG_REG("IFCR", 0xfffe38a2, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
+ { PINMUX_CFG_REG_VAR("IFCR", 0xfffe38a2, 16,
+ GROUP(-12, 4),
+ GROUP(
+ /* RESERVED [12] */
PB12IRQ_00, PB12IRQ_01, PB12IRQ_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
@@ -1167,9 +1153,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PC1_IN, PC1_OUT,
PC0_IN, PC0_OUT ))
},
- { PINMUX_CFG_REG("PCCRL4", 0xfffe3910, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
+ { PINMUX_CFG_REG_VAR("PCCRL4", 0xfffe3910, 16,
+ GROUP(-4, 4, 4, 4),
+ GROUP(
+ /* RESERVED [4] */
PC14MD_0, PC14MD_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1417,8 +1404,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF1_IN, PF1_OUT,
PF0_IN, PF0_OUT ))
},
- { PINMUX_CFG_REG("PFCRH4", 0xfffe3a88, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PFCRH4", 0xfffe3a88, 16,
+ GROUP(-4, 4, 4, 4),
+ GROUP(
+ /* RESERVED [4] */
PF30MD_0, PF30MD_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 39/50] pinctrl: renesas: sh7264: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (37 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 38/50] pinctrl: renesas: sh7203: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 40/50] pinctrl: renesas: sh7269: " Geert Uytterhoeven
` (11 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 572 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh7264.c | 104 +++++++++++++--------------
1 file changed, 52 insertions(+), 52 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh7264.c b/drivers/pinctrl/renesas/pfc-sh7264.c
index 7476b982101d6518..30096925a70c5d88 100644
--- a/drivers/pinctrl/renesas/pfc-sh7264.c
+++ b/drivers/pinctrl/renesas/pfc-sh7264.c
@@ -1464,19 +1464,20 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PAIOR0", 0xfffe3812, 16,
+ GROUP(-12, 1, 1, 1, 1),
+ GROUP(
+ /* RESERVED [12] */
PA3_IN, PA3_OUT,
PA2_IN, PA2_OUT,
PA1_IN, PA1_OUT,
PA0_IN, PA0_OUT ))
},
- { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PBCR5", 0xfffe3824, 16,
+ GROUP(-4, 4, 4, 4),
+ GROUP(
+ /* RESERVED [4] */
PB22MD_00, PB22MD_01, PB22MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PB21MD_0, PB21MD_1, 0, 0, 0, 0, 0, 0,
@@ -1525,21 +1526,22 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, PB4MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 ))
},
- { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4, GROUP(
+ { PINMUX_CFG_REG_VAR("PBCR0", 0xfffe382e, 16,
+ GROUP(4, 4, 4, -4),
+ GROUP(
0, PB3MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB2MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB1MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0 ))
+ /* RESERVED [4] */ ))
},
- { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("PBIOR1", 0xfffe3830, 16,
+ GROUP(-9, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* RESERVED [9] */
PB22_IN, PB22_OUT,
PB21_IN, PB21_OUT,
PB20_IN, PB20_OUT,
@@ -1568,9 +1570,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0 ))
},
- { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PCCR2", 0xfffe384a, 16,
+ GROUP(-4, 4, 4, 4),
+ GROUP(
+ /* RESERVED [4] */
PC10MD_0, PC10MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC9MD_0, PC9MD_1, 0, 0, 0, 0, 0, 0,
@@ -1599,8 +1602,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0 ))
},
- { PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PCIOR0", 0xfffe3852, 16,
+ GROUP(-5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* RESERVED [5] */
PC10_IN, PC10_OUT,
PC9_IN, PC9_OUT,
PC8_IN, PC8_OUT,
@@ -1675,11 +1680,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD0_IN, PD0_OUT ))
},
- { PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PECR1", 0xfffe388c, 16,
+ GROUP(-8, 4, 4),
+ GROUP(
+ /* RESERVED [8] */
PE5MD_00, PE5MD_01, 0, PE5MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PE4MD_00, PE4MD_01, 0, PE4MD_11, 0, 0, 0, 0,
@@ -1698,10 +1702,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0 ))
},
- { PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PEIOR0", 0xfffe3892, 16,
+ GROUP(-10, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* RESERVED [10] */
PE5_IN, PE5_OUT,
PE4_IN, PE4_OUT,
PE3_IN, PE3_OUT,
@@ -1710,10 +1714,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PE0_IN, PE0_OUT ))
},
- { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PFCR3", 0xfffe38a8, 16,
+ GROUP(-12, 4),
+ GROUP(
+ /* RESERVED [12] */
PF12MD_000, PF12MD_001, 0, PF12MD_011,
PF12MD_100, PF12MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 ))
@@ -1780,25 +1784,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF0_IN, PF0_OUT ))
},
- { PINMUX_CFG_REG("PGCR7", 0xfffe38c0, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PGCR7", 0xfffe38c0, 16,
+ GROUP(-12, 4),
+ GROUP(
+ /* RESERVED [12] */
PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
PG0MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 ))
},
- { PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PGCR6", 0xfffe38c2, 16,
+ GROUP(-12, 4),
+ GROUP(
+ /* RESERVED [12] */
PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 ))
},
@@ -1869,19 +1867,21 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 ))
},
- { PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4, GROUP(
+ { PINMUX_CFG_REG_VAR("PGCR0", 0xfffe38ce, 16,
+ GROUP(4, 4, 4, -4),
+ GROUP(
PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0 ))
+ /* RESERVED [4] */ ))
},
- { PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PGIOR1", 0xfffe38d0, 16,
+ GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* RESERVED [7] */
PG24_IN, PG24_OUT,
PG23_IN, PG23_OUT,
PG22_IN, PG22_OUT,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 40/50] pinctrl: renesas: sh7269: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (38 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 39/50] pinctrl: renesas: sh7264: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 41/50] pinctrl: renesas: sh73a0: " Geert Uytterhoeven
` (10 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 406 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh7269.c | 82 +++++++++++++++-------------
1 file changed, 43 insertions(+), 39 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh7269.c b/drivers/pinctrl/renesas/pfc-sh7269.c
index 733a2c114ca26ea0..f59f558d75ae253e 100644
--- a/drivers/pinctrl/renesas/pfc-sh7269.c
+++ b/drivers/pinctrl/renesas/pfc-sh7269.c
@@ -1966,15 +1966,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
* mode registers and modes are described in assending order [0..15]
*/
- { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, PA1_IN, PA1_OUT,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, PA0_IN, PA0_OUT ))
+ { PINMUX_CFG_REG_VAR("PAIOR0", 0xfffe3812, 16,
+ GROUP(-7, 1, -7, 1),
+ GROUP(
+ /* RESERVED [7] */
+ PA1_IN, PA1_OUT,
+ /* RESERVED [7] */
+ PA0_IN, PA0_OUT ))
},
- { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
+ { PINMUX_CFG_REG_VAR("PBCR5", 0xfffe3824, 16,
+ GROUP(-4, 4, 4, 4),
+ GROUP(
+ /* RESERVED [4] */
PB22MD_000, PB22MD_001, PB22MD_010, PB22MD_011,
PB22MD_100, PB22MD_101, PB22MD_110, PB22MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -2045,7 +2048,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 ))
},
- { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4, GROUP(
+ { PINMUX_CFG_REG_VAR("PBCR0", 0xfffe382e, 16,
+ GROUP(4, 4, 4, -4),
+ GROUP(
PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -2055,13 +2060,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
+ /* RESERVED [4] */ ))
},
- { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("PBIOR1", 0xfffe3830, 16,
+ GROUP(-9, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* RESERVED [9] */
PB22_IN, PB22_OUT,
PB21_IN, PB21_OUT,
PB20_IN, PB20_OUT,
@@ -2089,13 +2094,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0 ))
},
- { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
+ { PINMUX_CFG_REG_VAR("PCCR2", 0xfffe384a, 16,
+ GROUP(-12, 4),
+ GROUP(
+ /* RESERVED [12] */
PC8MD_000, PC8MD_001, PC8MD_010, PC8MD_011,
PC8MD_100, PC8MD_101, PC8MD_110, PC8MD_111,
0, 0, 0, 0, 0, 0, 0, 0 ))
@@ -2130,8 +2132,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0 ))
},
- { PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PCIOR0", 0xfffe3852, 16,
+ GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* RESERVED [7] */
PC8_IN, PC8_OUT,
PC7_IN, PC7_OUT,
PC6_IN, PC6_OUT,
@@ -2244,9 +2248,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 ))
},
- { PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PEIOR0", 0xfffe3892, 16,
+ GROUP(-8, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* RESERVED [8] */
PE7_IN, PE7_OUT,
PE6_IN, PE6_OUT,
PE5_IN, PE5_OUT,
@@ -2291,20 +2296,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF16MD_100, PF16MD_101, PF16MD_110, PF16MD_111,
0, 0, 0, 0, 0, 0, 0, 0 ))
},
- { PINMUX_CFG_REG("PFCR4", 0xfffe38a6, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
+ { PINMUX_CFG_REG_VAR("PFCR4", 0xfffe38a6, 16,
+ GROUP(-12, 4),
+ GROUP(
+ /* RESERVED [12] */
PF15MD_000, PF15MD_001, PF15MD_010, PF15MD_011,
PF15MD_100, PF15MD_101, PF15MD_110, PF15MD_111,
0, 0, 0, 0, 0, 0, 0, 0 ))
},
- { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
+ { PINMUX_CFG_REG_VAR("PFCR3", 0xfffe38a8, 16,
+ GROUP(-4, 4, 4, 4),
+ GROUP(
+ /* RESERVED [4] */
PF14MD_000, PF14MD_001, PF14MD_010, PF14MD_011,
PF14MD_100, PF14MD_101, PF14MD_110, PF14MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -2369,9 +2372,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0 ))
},
- { PINMUX_CFG_REG("PFIOR1", 0xfffe38b0, 16, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PFIOR1", 0xfffe38b0, 16,
+ GROUP(-8, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* RESERVED [8] */
PF23_IN, PF23_OUT,
PF22_IN, PF22_OUT,
PF21_IN, PF21_OUT,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 41/50] pinctrl: renesas: sh73a0: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (39 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 40/50] pinctrl: renesas: sh7269: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 42/50] pinctrl: renesas: sh7720: " Geert Uytterhoeven
` (9 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 154 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh73a0.c | 87 ++++++++++------------------
1 file changed, 30 insertions(+), 57 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh73a0.c b/drivers/pinctrl/renesas/pfc-sh73a0.c
index 5d8a0179fd60fee4..4f54dfd5a9674916 100644
--- a/drivers/pinctrl/renesas/pfc-sh73a0.c
+++ b/drivers/pinctrl/renesas/pfc-sh73a0.c
@@ -3798,24 +3798,16 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(308, 0xe6052134), /* PORT308CR */
PORTCR(309, 0xe6052135), /* PORT309CR */
- { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("MSEL2CR", 0xe605801c, 32,
+ GROUP(-12, 1, 1, 1, 1, -1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* RESERVED [12] */
MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
@@ -3833,60 +3825,43 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
))
},
- { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("MSEL3CR", 0xe6058020, 32,
+ GROUP(-3, 1, -12, 1, -3, 1, -1, 1, -2, 1, -3, 1,
+ -2),
+ GROUP(
+ /* RESERVED [3] */
MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [12] */
MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [3] */
MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
- 0, 0,
- 0, 0,
+ /* RESERVED [2] */
MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [3] */
MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
- 0, 0,
- 0, 0,
+ /* RESERVED [2] */
))
},
- { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("MSEL4CR", 0xe6058024, 32,
+ GROUP(-2, 1, -1, 1, 1, -3, 1, 1, 1, 1, -3, 1,
+ -1, 1, 1, 1, 1, 1, 1, 1, -2, 1, -2, 1,
+ -1),
+ GROUP(
+ /* RESERVED [2] */
MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [3] */
MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [3] */
MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
- 0, 0,
+ /* RESERVED [1] */
MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
@@ -3894,13 +3869,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
- 0, 0,
- 0, 0,
+ /* RESERVED [2] */
MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
- 0, 0,
- 0, 0,
+ /* RESERVED [2] */
MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
- 0, 0,
+ /* RESERVED [1] */
))
},
{ },
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 42/50] pinctrl: renesas: sh7720: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (40 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 41/50] pinctrl: renesas: sh73a0: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 43/50] pinctrl: renesas: sh7722: " Geert Uytterhoeven
` (8 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 128 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh7720.c | 57 ++++++++++++++--------------
1 file changed, 28 insertions(+), 29 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh7720.c b/drivers/pinctrl/renesas/pfc-sh7720.c
index 7071ef52449d6ccf..6eedcc5bbb4d6705 100644
--- a/drivers/pinctrl/renesas/pfc-sh7720.c
+++ b/drivers/pinctrl/renesas/pfc-sh7720.c
@@ -1014,25 +1014,24 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN ))
},
- { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PKCR", 0xa4050112, 16,
+ GROUP(-8, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [8] */
PTK3_FN, PTK3_OUT, 0, PTK3_IN,
PTK2_FN, PTK2_OUT, 0, PTK2_IN,
PTK1_FN, PTK1_OUT, 0, PTK1_IN,
PTK0_FN, PTK0_OUT, 0, PTK0_IN ))
},
- { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
+ { PINMUX_CFG_REG_VAR("PLCR", 0xa4050114, 16,
+ GROUP(2, 2, 2, 2, 2, -6),
+ GROUP(
PTL7_FN, PTL7_OUT, 0, PTL7_IN,
PTL6_FN, PTL6_OUT, 0, PTL6_IN,
PTL5_FN, PTL5_OUT, 0, PTL5_IN,
PTL4_FN, PTL4_OUT, 0, PTL4_IN,
PTL3_FN, PTL3_OUT, 0, PTL3_IN,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0 ))
+ /* RESERVED [6] */ ))
},
{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
PTM7_FN, PTM7_OUT, 0, PTM7_IN,
@@ -1044,10 +1043,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTM1_FN, PTM1_OUT, 0, PTM1_IN,
PTM0_FN, PTM0_OUT, 0, PTM0_IN ))
},
- { PINMUX_CFG_REG("PPCR", 0xa4050118, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PPCR", 0xa4050118, 16,
+ GROUP(-6, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [6] */
PTP4_FN, PTP4_OUT, 0, PTP4_IN,
PTP3_FN, PTP3_OUT, 0, PTP3_IN,
PTP2_FN, PTP2_OUT, 0, PTP2_IN,
@@ -1064,40 +1063,40 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTR1_FN, PTR1_OUT, 0, PTR1_IN,
PTR0_FN, PTR0_OUT, 0, PTR0_IN ))
},
- { PINMUX_CFG_REG("PSCR", 0xa405011c, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PSCR", 0xa405011c, 16,
+ GROUP(-6, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [6] */
PTS4_FN, PTS4_OUT, 0, PTS4_IN,
PTS3_FN, PTS3_OUT, 0, PTS3_IN,
PTS2_FN, PTS2_OUT, 0, PTS2_IN,
PTS1_FN, PTS1_OUT, 0, PTS1_IN,
PTS0_FN, PTS0_OUT, 0, PTS0_IN ))
},
- { PINMUX_CFG_REG("PTCR", 0xa405011e, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PTCR", 0xa405011e, 16,
+ GROUP(-6, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [6] */
PTT4_FN, PTT4_OUT, 0, PTT4_IN,
PTT3_FN, PTT3_OUT, 0, PTT3_IN,
PTT2_FN, PTT2_OUT, 0, PTT2_IN,
PTT1_FN, PTT1_OUT, 0, PTT1_IN,
PTT0_FN, PTT0_OUT, 0, PTT0_IN ))
},
- { PINMUX_CFG_REG("PUCR", 0xa4050120, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PUCR", 0xa4050120, 16,
+ GROUP(-6, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [6] */
PTU4_FN, PTU4_OUT, 0, PTU4_IN,
PTU3_FN, PTU3_OUT, 0, PTU3_IN,
PTU2_FN, PTU2_OUT, 0, PTU2_IN,
PTU1_FN, PTU1_OUT, 0, PTU1_IN,
PTU0_FN, PTU0_OUT, 0, PTU0_IN ))
},
- { PINMUX_CFG_REG("PVCR", 0xa4050122, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PVCR", 0xa4050122, 16,
+ GROUP(-6, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [6] */
PTV4_FN, PTV4_OUT, 0, PTV4_IN,
PTV3_FN, PTV3_OUT, 0, PTV3_IN,
PTV2_FN, PTV2_OUT, 0, PTV2_IN,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 43/50] pinctrl: renesas: sh7722: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (41 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 42/50] pinctrl: renesas: sh7720: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 44/50] pinctrl: renesas: sh7723: " Geert Uytterhoeven
` (7 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 396 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh7722.c | 202 +++++++++++----------------
1 file changed, 80 insertions(+), 122 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh7722.c b/drivers/pinctrl/renesas/pfc-sh7722.c
index 635e3dca27038890..4b82ac2c5e91d787 100644
--- a/drivers/pinctrl/renesas/pfc-sh7722.c
+++ b/drivers/pinctrl/renesas/pfc-sh7722.c
@@ -1255,14 +1255,16 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
HPD49, PTB1_OUT, 0, PTB1_IN,
HPD48, PTB0_OUT, 0, PTB0_IN ))
},
- { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
+ { PINMUX_CFG_REG_VAR("PCCR", 0xa4050104, 16,
+ GROUP(2, -2, 2, 2, 2, 2, -2, 2),
+ GROUP(
0, 0, 0, PTC7_IN,
- 0, 0, 0, 0,
+ /* RESERVED [2] */
IOIS16, 0, 0, PTC5_IN,
HPDQM7, PTC4_OUT, 0, PTC4_IN,
HPDQM6, PTC3_OUT, 0, PTC3_IN,
HPDQM5, PTC2_OUT, 0, PTC2_IN,
- 0, 0, 0, 0,
+ /* RESERVED [2] */
HPDQM4, PTC0_OUT, 0, PTC0_IN ))
},
{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
@@ -1275,13 +1277,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
SDHICMD, PTD1_OUT, 0, PTD1_IN,
SDHICLK, PTD0_OUT, 0, 0 ))
},
- { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
+ { PINMUX_CFG_REG_VAR("PECR", 0xa4050108, 16,
+ GROUP(2, 2, 2, 2, -4, 2, 2),
+ GROUP(
A25, PTE7_OUT, 0, PTE7_IN,
A24, PTE6_OUT, 0, PTE6_IN,
A23, PTE5_OUT, 0, PTE5_IN,
A22, PTE4_OUT, 0, PTE4_IN,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ /* RESERVED [4] */
IRQ5, PTE1_OUT, 0, PTE1_IN,
IRQ4_BS, PTE0_OUT, 0, PTE0_IN ))
},
@@ -1295,10 +1298,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
SIORXD_SIUBISLD, 0, 0, PTF1_IN,
SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 ))
},
- { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PGCR", 0xa405010c, 16,
+ GROUP(-6, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [6] */
AUDSYNC, PTG4_OUT, 0, 0,
AUDATA3, PTG3_OUT, 0, 0,
AUDATA2, PTG2_OUT, 0, 0,
@@ -1315,13 +1318,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
LCDD17_DV_HSYNC, PTH1_OUT, 0, PTH1_IN,
LCDD16_DV_VSYNC, PTH0_OUT, 0, PTH0_IN ))
},
- { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
+ { PINMUX_CFG_REG_VAR("PJCR", 0xa4050110, 16,
+ GROUP(2, 2, 2, -6, 2, 2),
+ GROUP(
STATUS0, PTJ7_OUT, 0, 0,
0, PTJ6_OUT, 0, 0,
PDSTATUS, PTJ5_OUT, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ /* RESERVED [6] */
IRQ1, PTJ1_OUT, 0, PTJ1_IN,
IRQ0, PTJ0_OUT, 0, PTJ0_IN ))
},
@@ -1375,50 +1378,50 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTQ1, PTQ1_OUT, 0, 0,
PTQ0, PTQ0_OUT, 0, PTQ0_IN ))
},
- { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PRCR", 0xa405011c, 16,
+ GROUP(-6, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [6] */
LCDRD, PTR4_OUT, 0, 0,
CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0,
WAIT, 0, 0, PTR2_IN,
LCDDCK_LCDWR, PTR1_OUT, 0, 0,
LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 ))
},
- { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PSCR", 0xa405011e, 16,
+ GROUP(-6, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [6] */
SCIF0_CTS_SIUAISPD, 0, 0, PTS4_IN,
SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0,
SCIF0_SCK_TPUTO, PTS2_OUT, 0, PTS2_IN,
SCIF0_RXD, 0, 0, PTS1_IN,
SCIF0_TXD, PTS0_OUT, 0, 0 ))
},
- { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PTCR", 0xa4050140, 16,
+ GROUP(-6, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [6] */
FOE_VIO_VD2, PTT4_OUT, 0, PTT4_IN,
FWE, PTT3_OUT, 0, PTT3_IN,
FSC, PTT2_OUT, 0, PTT2_IN,
DREQ0, 0, 0, PTT1_IN,
FCDE, PTT0_OUT, 0, 0 ))
},
- { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PUCR", 0xa4050142, 16,
+ GROUP(-6, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [6] */
NAF2_VIO_D10, PTU4_OUT, 0, PTU4_IN,
NAF1_VIO_D9, PTU3_OUT, 0, PTU3_IN,
NAF0_VIO_D8, PTU2_OUT, 0, PTU2_IN,
FRB_VIO_CLK2, 0, 0, PTU1_IN,
FCE_VIO_HD2, PTU0_OUT, 0, PTU0_IN ))
},
- { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PVCR", 0xa4050144, 16,
+ GROUP(-6, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [6] */
NAF7_VIO_D15, PTV4_OUT, 0, PTV4_IN,
NAF6_VIO_D14, PTV3_OUT, 0, PTV3_IN,
NAF5_VIO_D13, PTV2_OUT, 0, PTV2_IN,
@@ -1445,9 +1448,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
LCDD19_DV_CLKI, PTX1_OUT, 0, PTX1_IN,
LCDD18_DV_CLK, PTX0_OUT, 0, PTX0_IN ))
},
- { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PYCR", 0xa405014a, 16,
+ GROUP(-4, 2, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [4] */
KEYOUT5_IN5, PTY5_OUT, 0, PTY5_IN,
KEYOUT4_IN6, PTY4_OUT, 0, PTY4_IN,
KEYOUT3, PTY3_OUT, 0, PTY3_IN,
@@ -1455,33 +1459,27 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
KEYOUT1, PTY1_OUT, 0, 0,
KEYOUT0, PTY0_OUT, 0, PTY0_IN ))
},
- { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PZCR", 0xa405014c, 16,
+ GROUP(-4, 2, 2, 2, 2, 2, -2),
+ GROUP(
+ /* RESERVED [4] */
KEYIN4_IRQ7, 0, 0, PTZ5_IN,
KEYIN3, 0, 0, PTZ4_IN,
KEYIN2, 0, 0, PTZ3_IN,
KEYIN1, 0, 0, PTZ2_IN,
KEYIN0_IRQ6, 0, 0, PTZ1_IN,
- 0, 0, 0, 0 ))
+ /* RESERVED [2] */ ))
},
- { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1, GROUP(
+ { PINMUX_CFG_REG_VAR("PSELA", 0xa405014e, 16,
+ GROUP(1, 1, -4, 1, -4, 1, -4),
+ GROUP(
PSA15_KEYIN0, PSA15_IRQ6,
PSA14_KEYIN4, PSA14_IRQ7,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [4] */
PSA9_IRQ4, PSA9_BS,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [4] */
PSA4_IRQ2, PSA4_SDHID2,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0 ))
+ /* RESERVED [4] */ ))
},
{ PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1, GROUP(
PSB15_SIOTXD, PSB15_SIUBOSLD,
@@ -1501,22 +1499,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PSB1_SIUMCKA, PSB1_SIOF1_MCK,
PSB0_SIUAOSLD, PSB0_SIOF1_TXD ))
},
- { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1, GROUP(
+ { PINMUX_CFG_REG_VAR("PSELC", 0xa4050152, 16,
+ GROUP(1, 1, 1, 1, 1, -10, 1),
+ GROUP(
PSC15_SIUAISLD, PSC15_SIOF1_RXD,
PSC14_SIUAOBT, PSC14_SIOF1_SCK,
PSC13_SIUAOLR, PSC13_SIOF1_SYNC,
PSC12_SIUAIBT, PSC12_SIOF1_SS1,
PSC11_SIUAILR, PSC11_SIOF1_SS2,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [10] */
PSC0_NAF, PSC0_VIO ))
},
{ PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1, GROUP(
@@ -1537,61 +1528,45 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
PSD0_LCDD19_LCDD0, PSD0_DV ))
},
- { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1, GROUP(
+ { PINMUX_CFG_REG_VAR("PSELE", 0xa4050156, 16,
+ GROUP(1, 1, 1, 1, 1, -7, 1, 1, 1, 1),
+ GROUP(
PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D,
PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK,
PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT,
PSE12_LCDVSYN2, PSE12_DACK,
PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [7] */
PSE3_FLCTL, PSE3_VIO,
PSE2_NAF2, PSE2_VIO_D10,
PSE1_NAF1, PSE1_VIO_D9,
PSE0_NAF0, PSE0_VIO_D8 ))
},
- { PINMUX_CFG_REG("HIZCRA", 0xa4050158, 16, 1, GROUP(
- 0, 0,
+ { PINMUX_CFG_REG_VAR("HIZCRA", 0xa4050158, 16,
+ GROUP(-1, 1, -3, 1, 1, 1, 1, 1, -6),
+ GROUP(
+ /* RESERVED [1] */
HIZA14_KEYSC, HIZA14_HIZ,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [3] */
HIZA10_NAF, HIZA10_HIZ,
HIZA9_VIO, HIZA9_HIZ,
HIZA8_LCDC, HIZA8_HIZ,
HIZA7_LCDC, HIZA7_HIZ,
HIZA6_LCDC, HIZA6_HIZ,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0 ))
+ /* RESERVED [6] */ ))
},
- { PINMUX_CFG_REG("HIZCRB", 0xa405015a, 16, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("HIZCRB", 0xa405015a, 16,
+ GROUP(-11, 1, -2, 1, 1),
+ GROUP(
+ /* RESERVED [11] */
HIZB4_SIUA, HIZB4_HIZ,
- 0, 0,
- 0, 0,
+ /* RESERVED [2] */
HIZB1_VIO, HIZB1_HIZ,
HIZB0_VIO, HIZB0_HIZ ))
},
- { PINMUX_CFG_REG("HIZCRC", 0xa405015c, 16, 1, GROUP(
+ { PINMUX_CFG_REG_VAR("HIZCRC", 0xa405015c, 16,
+ GROUP(1, 1, 1, 1, 1, 1, 1, 1, -8),
+ GROUP(
HIZC15_IRQ7, HIZC15_HIZ,
HIZC14_IRQ6, HIZC14_HIZ,
HIZC13_IRQ5, HIZC13_HIZ,
@@ -1600,32 +1575,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
HIZC10_IRQ2, HIZC10_HIZ,
HIZC9_IRQ1, HIZC9_HIZ,
HIZC8_IRQ0, HIZC8_HIZ,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0 ))
+ /* RESERVED [8] */ ))
},
- { PINMUX_CFG_REG("MSELCRB", 0xa4050182, 16, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("MSELCRB", 0xa4050182, 16,
+ GROUP(-6, 1, 1, -8),
+ GROUP(
+ /* RESERVED [6] */
MSELB9_VIO, MSELB9_VIO2,
MSELB8_RGB, MSELB8_SYS,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0 ))
+ /* RESERVED [8] */ ))
},
{}
};
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 44/50] pinctrl: renesas: sh7723: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (42 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 43/50] pinctrl: renesas: sh7722: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 45/50] pinctrl: renesas: sh7724: " Geert Uytterhoeven
` (6 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 105 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh7723.c | 70 ++++++++++++++++------------
1 file changed, 39 insertions(+), 31 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh7723.c b/drivers/pinctrl/renesas/pfc-sh7723.c
index 94c7acf591d68a29..95344281966e6eb0 100644
--- a/drivers/pinctrl/renesas/pfc-sh7723.c
+++ b/drivers/pinctrl/renesas/pfc-sh7723.c
@@ -1546,9 +1546,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTD1_FN, PTD1_OUT, 0, PTD1_IN,
PTD0_FN, PTD0_OUT, 0, PTD0_IN ))
},
- { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PECR", 0xa4050108, 16,
+ GROUP(-4, 2, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [4] */
PTE5_FN, PTE5_OUT, 0, PTE5_IN,
PTE4_FN, PTE4_OUT, 0, PTE4_IN,
PTE3_FN, PTE3_OUT, 0, PTE3_IN,
@@ -1566,9 +1567,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTF1_FN, PTF1_OUT, 0, PTF1_IN,
PTF0_FN, PTF0_OUT, 0, PTF0_IN ))
},
- { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PGCR", 0xa405010c, 16,
+ GROUP(-4, 2, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [4] */
PTG5_FN, PTG5_OUT, 0, 0,
PTG4_FN, PTG4_OUT, 0, 0,
PTG3_FN, PTG3_OUT, 0, 0,
@@ -1586,11 +1588,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTH1_FN, PTH1_OUT, 0, PTH1_IN,
PTH0_FN, PTH0_OUT, 0, PTH0_IN ))
},
- { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
+ { PINMUX_CFG_REG_VAR("PJCR", 0xa4050110, 16,
+ GROUP(2, -2, 2, -2, 2, 2, 2, 2),
+ GROUP(
PTJ7_FN, PTJ7_OUT, 0, 0,
- 0, 0, 0, 0,
+ /* RESERVED [2] */
PTJ5_FN, PTJ5_OUT, 0, 0,
- 0, 0, 0, 0,
+ /* RESERVED [2] */
PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
@@ -1636,11 +1640,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTN1_FN, PTN1_OUT, 0, PTN1_IN,
PTN0_FN, PTN0_OUT, 0, PTN0_IN ))
},
- { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PQCR", 0xa405011a, 16,
+ GROUP(-8, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [8] */
PTQ3_FN, 0, 0, PTQ3_IN,
PTQ2_FN, 0, 0, PTQ2_IN,
PTQ1_FN, 0, 0, PTQ1_IN,
@@ -1666,9 +1669,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTS1_FN, PTS1_OUT, 0, PTS1_IN,
PTS0_FN, PTS0_OUT, 0, PTS0_IN ))
},
- { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PTCR", 0xa4050140, 16,
+ GROUP(-4, 2, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [4] */
PTT5_FN, PTT5_OUT, 0, PTT5_IN,
PTT4_FN, PTT4_OUT, 0, PTT4_IN,
PTT3_FN, PTT3_OUT, 0, PTT3_IN,
@@ -1676,9 +1680,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTT1_FN, PTT1_OUT, 0, PTT1_IN,
PTT0_FN, PTT0_OUT, 0, PTT0_IN ))
},
- { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PUCR", 0xa4050142, 16,
+ GROUP(-4, 2, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [4] */
PTU5_FN, PTU5_OUT, 0, PTU5_IN,
PTU4_FN, PTU4_OUT, 0, PTU4_IN,
PTU3_FN, PTU3_OUT, 0, PTU3_IN,
@@ -1736,35 +1741,38 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN,
PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN ))
},
- { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 2, GROUP(
+ { PINMUX_CFG_REG_VAR("PSELA", 0xa405014e, 16,
+ GROUP(2, 2, 2, -4, 2, 2, -2),
+ GROUP(
PSA15_PSA14_FN1, PSA15_PSA14_FN2, 0, 0,
PSA13_PSA12_FN1, PSA13_PSA12_FN2, 0, 0,
PSA11_PSA10_FN1, PSA11_PSA10_FN2, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ /* RESERVED [4] */
PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3, 0,
PSA3_PSA2_FN1, PSA3_PSA2_FN2, 0, 0,
- 0, 0, 0, 0 ))
+ /* RESERVED [2] */ ))
},
- { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 2, GROUP(
+ { PINMUX_CFG_REG_VAR("PSELB", 0xa4050150, 16,
+ GROUP(2, 2, -2, 2, 2, 2, 2, -2),
+ GROUP(
PSB15_PSB14_FN1, PSB15_PSB14_FN2, 0, 0,
PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS, 0, 0,
- 0, 0, 0, 0,
+ /* RESERVED [2] */
PSB9_PSB8_FN1, PSB9_PSB8_FN2, PSB9_PSB8_FN3, 0,
PSB7_PSB6_FN1, PSB7_PSB6_FN2, 0, 0,
PSB5_PSB4_FN1, PSB5_PSB4_FN2, 0, 0,
PSB3_PSB2_FN1, PSB3_PSB2_FN2, 0, 0,
- 0, 0, 0, 0 ))
+ /* RESERVED [2] */ ))
},
- { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 2, GROUP(
+ { PINMUX_CFG_REG_VAR("PSELC", 0xa4050152, 16,
+ GROUP(2, 2, 2, 2, 2, -6),
+ GROUP(
PSC15_PSC14_FN1, PSC15_PSC14_FN2, 0, 0,
PSC13_PSC12_FN1, PSC13_PSC12_FN2, 0, 0,
PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3, 0,
PSC9_PSC8_FN1, PSC9_PSC8_FN2, 0, 0,
PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0 ))
+ /* RESERVED [3] */ ))
},
{ PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 2, GROUP(
PSD15_PSD14_FN1, PSD15_PSD14_FN2, 0, 0,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 45/50] pinctrl: renesas: sh7724: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (43 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 44/50] pinctrl: renesas: sh7723: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 46/50] pinctrl: renesas: sh7734: " Geert Uytterhoeven
` (5 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 8 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh7724.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh7724.c b/drivers/pinctrl/renesas/pfc-sh7724.c
index 551da3113ce348b8..26517ad26a0fd1b8 100644
--- a/drivers/pinctrl/renesas/pfc-sh7724.c
+++ b/drivers/pinctrl/renesas/pfc-sh7724.c
@@ -1798,9 +1798,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTF1_FN, PTF1_OUT, 0, PTF1_IN,
PTF0_FN, PTF0_OUT, 0, PTF0_IN ))
},
- { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PGCR", 0xa405010c, 16,
+ GROUP(-4, 2, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [4] */
PTG5_FN, PTG5_OUT, 0, 0,
PTG4_FN, PTG4_OUT, 0, 0,
PTG3_FN, PTG3_OUT, 0, 0,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 46/50] pinctrl: renesas: sh7734: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (44 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 45/50] pinctrl: renesas: sh7724: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 47/50] pinctrl: renesas: sh7757: " Geert Uytterhoeven
` (4 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 161 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh7734.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh7734.c b/drivers/pinctrl/renesas/pfc-sh7734.c
index 54f60b37c211e039..106a500ad13d160e 100644
--- a/drivers/pinctrl/renesas/pfc-sh7734.c
+++ b/drivers/pinctrl/renesas/pfc-sh7734.c
@@ -1805,16 +1805,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_1_FN, FN_IP9_21_20,
GP_4_0_FN, FN_IP9_19_18 ))
},
- { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* 19 - 16 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
+ { PINMUX_CFG_REG_VAR("GPSR5", 0xFFFC0018, 32,
+ GROUP(-20, 1, 1, -6, 1, 1, 1, 1),
+ GROUP(
+ /* GP5_31_12 RESERVED */
GP_5_11_FN, FN_IP10_29_28,
GP_5_10_FN, FN_IP10_27_26,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 9 - 6 */
- 0, 0, 0, 0, /* 5, 4 */
+ /* GP5_9_4 RESERVED */
GP_5_3_FN, FN_IRQ3_B,
GP_5_2_FN, FN_IRQ2_B,
GP_5_1_FN, FN_IP11_3,
@@ -2352,10 +2349,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1, GROUP(GP_INOUTSEL(4)))
},
- { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
+ { PINMUX_CFG_REG_VAR("INOUTSEL5", 0xffc45004, 32,
+ GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP5_31_12 RESERVED */
GP_5_11_IN, GP_5_11_OUT,
GP_5_10_IN, GP_5_10_OUT,
GP_5_9_IN, GP_5_9_OUT,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 47/50] pinctrl: renesas: sh7757: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (45 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 46/50] pinctrl: renesas: sh7734: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 48/50] pinctrl: renesas: sh7785: " Geert Uytterhoeven
` (3 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 115 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh7757.c | 95 +++++++++++-----------------
1 file changed, 38 insertions(+), 57 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh7757.c b/drivers/pinctrl/renesas/pfc-sh7757.c
index 79cf7c42c35d87dd..0d7857d7efefb47b 100644
--- a/drivers/pinctrl/renesas/pfc-sh7757.c
+++ b/drivers/pinctrl/renesas/pfc-sh7757.c
@@ -1963,43 +1963,35 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
0, 0, ))
},
- { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("PSEL1", 0xffec0072, 16,
+ GROUP(-5, 1, 1, 1, -5, 1, -2),
+ GROUP(
+ /* RESERVED [5] */
PS1_10_FN1, PS1_10_FN2,
PS1_9_FN1, PS1_9_FN2,
PS1_8_FN1, PS1_8_FN2,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [5] */
PS1_2_FN1, PS1_2_FN2,
- 0, 0,
- 0, 0, ))
+ /* RESERVED [2] */ ))
},
- { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1, GROUP(
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("PSEL2", 0xffec0074, 16,
+ GROUP(-2, 1, 1, -4, 1, 1, 1, 1, -1, 1, -2),
+ GROUP(
+ /* RESERVED [2] */
PS2_13_FN1, PS2_13_FN2,
PS2_12_FN1, PS2_12_FN2,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [4] */
PS2_7_FN1, PS2_7_FN2,
PS2_6_FN1, PS2_6_FN2,
PS2_5_FN1, PS2_5_FN2,
PS2_4_FN1, PS2_4_FN2,
- 0, 0,
+ /* RESERVED [1] */
PS2_2_FN1, PS2_2_FN2,
- 0, 0,
- 0, 0, ))
+ /* RESERVED [2] */ ))
},
- { PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1, GROUP(
+ { PINMUX_CFG_REG_VAR("PSEL3", 0xffec0076, 16,
+ GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, -4, 1, 1, -1),
+ GROUP(
PS3_15_FN1, PS3_15_FN2,
PS3_14_FN1, PS3_14_FN2,
PS3_13_FN1, PS3_13_FN2,
@@ -2009,38 +2001,35 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PS3_9_FN1, PS3_9_FN2,
PS3_8_FN1, PS3_8_FN2,
PS3_7_FN1, PS3_7_FN2,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [4] */
PS3_2_FN1, PS3_2_FN2,
PS3_1_FN1, PS3_1_FN2,
- 0, 0, ))
+ /* RESERVED [1] */ ))
},
- { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1, GROUP(
- 0, 0,
+ { PINMUX_CFG_REG_VAR("PSEL4", 0xffec0078, 16,
+ GROUP(-1, 1, 1, 1, -1, 1, 1, 1, -3, 1, 1, 1,
+ 1, 1),
+ GROUP(
+ /* RESERVED [1] */
PS4_14_FN1, PS4_14_FN2,
PS4_13_FN1, PS4_13_FN2,
PS4_12_FN1, PS4_12_FN2,
- 0, 0,
+ /* RESERVED [1] */
PS4_10_FN1, PS4_10_FN2,
PS4_9_FN1, PS4_9_FN2,
PS4_8_FN1, PS4_8_FN2,
- 0, 0,
- 0, 0,
- 0, 0,
+ /* RESERVED [3] */
PS4_4_FN1, PS4_4_FN2,
PS4_3_FN1, PS4_3_FN2,
PS4_2_FN1, PS4_2_FN2,
PS4_1_FN1, PS4_1_FN2,
PS4_0_FN1, PS4_0_FN2, ))
},
- { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("PSEL5", 0xffec007a, 16,
+ GROUP(-4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -2),
+ GROUP(
+ /* RESERVED [4] */
PS5_11_FN1, PS5_11_FN2,
PS5_10_FN1, PS5_10_FN2,
PS5_9_FN1, PS5_9_FN2,
@@ -2051,8 +2040,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PS5_4_FN1, PS5_4_FN2,
PS5_3_FN1, PS5_3_FN2,
PS5_2_FN1, PS5_2_FN2,
- 0, 0,
- 0, 0, ))
+ /* RESERVED [2] */ ))
},
{ PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1, GROUP(
PS6_15_FN1, PS6_15_FN2,
@@ -2072,7 +2060,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PS6_1_FN1, PS6_1_FN2,
PS6_0_FN1, PS6_0_FN2, ))
},
- { PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1, GROUP(
+ { PINMUX_CFG_REG_VAR("PSEL7", 0xffec0082, 16,
+ GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -5),
+ GROUP(
PS7_15_FN1, PS7_15_FN2,
PS7_14_FN1, PS7_14_FN2,
PS7_13_FN1, PS7_13_FN2,
@@ -2084,13 +2074,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PS7_7_FN1, PS7_7_FN2,
PS7_6_FN1, PS7_6_FN2,
PS7_5_FN1, PS7_5_FN2,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0, ))
+ /* RESERVED [5] */ ))
},
- { PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1, GROUP(
+ { PINMUX_CFG_REG_VAR("PSEL8", 0xffec0084, 16,
+ GROUP(1, 1, 1, 1, 1, 1, 1, 1, -8),
+ GROUP(
PS8_15_FN1, PS8_15_FN2,
PS8_14_FN1, PS8_14_FN2,
PS8_13_FN1, PS8_13_FN2,
@@ -2099,14 +2087,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PS8_10_FN1, PS8_10_FN2,
PS8_9_FN1, PS8_9_FN2,
PS8_8_FN1, PS8_8_FN2,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0, ))
+ /* RESERVED [8] */ ))
},
{}
};
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 48/50] pinctrl: renesas: sh7785: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (46 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 47/50] pinctrl: renesas: sh7757: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 49/50] pinctrl: renesas: sh7786: " Geert Uytterhoeven
` (2 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 150 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh7785.c | 60 +++++++++++-----------------
1 file changed, 24 insertions(+), 36 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh7785.c b/drivers/pinctrl/renesas/pfc-sh7785.c
index 62389f7a1de14aec..126b663bb6eb3abe 100644
--- a/drivers/pinctrl/renesas/pfc-sh7785.c
+++ b/drivers/pinctrl/renesas/pfc-sh7785.c
@@ -1024,9 +1024,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD1_FN, PD1_OUT, PD1_IN, 0,
PD0_FN, PD0_OUT, PD0_IN, 0 ))
},
- { PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PECR", 0xffe70008, 16,
+ GROUP(-4, 2, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [4] */
PE5_FN, PE5_OUT, PE5_IN, 0,
PE4_FN, PE4_OUT, PE4_IN, 0,
PE3_FN, PE3_OUT, PE3_IN, 0,
@@ -1094,13 +1095,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PL1_FN, PL1_OUT, PL1_IN, 0,
PL0_FN, PL0_OUT, PL0_IN, 0 ))
},
- { PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PMCR", 0xffe70016, 16,
+ GROUP(-12, 2, 2),
+ GROUP(
+ /* RESERVED [12] */
PM1_FN, PM1_OUT, PM1_IN, 0,
PM0_FN, PM0_OUT, PM0_IN, 0 ))
},
@@ -1114,9 +1112,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PN1_FN, PN1_OUT, PN1_IN, 0,
PN0_FN, PN0_OUT, PN0_IN, 0 ))
},
- { PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PPCR", 0xffe7001a, 16,
+ GROUP(-4, 2, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [4] */
PP5_FN, PP5_OUT, PP5_IN, 0,
PP4_FN, PP4_OUT, PP4_IN, 0,
PP3_FN, PP3_OUT, PP3_IN, 0,
@@ -1124,21 +1123,20 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PP1_FN, PP1_OUT, PP1_IN, 0,
PP0_FN, PP0_OUT, PP0_IN, 0 ))
},
- { PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PQCR", 0xffe7001c, 16,
+ GROUP(-6, 2, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [6] */
PQ4_FN, PQ4_OUT, PQ4_IN, 0,
PQ3_FN, PQ3_OUT, PQ3_IN, 0,
PQ2_FN, PQ2_OUT, PQ2_IN, 0,
PQ1_FN, PQ1_OUT, PQ1_IN, 0,
PQ0_FN, PQ0_OUT, PQ0_IN, 0 ))
},
- { PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2, GROUP(
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("PRCR", 0xffe7001e, 16,
+ GROUP(-8, 2, 2, 2, 2),
+ GROUP(
+ /* RESERVED [8] */
PR3_FN, PR3_OUT, PR3_IN, 0,
PR2_FN, PR2_OUT, PR2_IN, 0,
PR1_FN, PR1_OUT, PR1_IN, 0,
@@ -1162,20 +1160,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
P1MSEL1_0, P1MSEL1_1,
P1MSEL0_0, P1MSEL0_1 ))
},
- { PINMUX_CFG_REG("P2MSELR", 0xffe70082, 16, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("P2MSELR", 0xffe70082, 16,
+ GROUP(-13, 1, 1, 1),
+ GROUP(
+ /* RESERVED [13] */
P2MSEL2_0, P2MSEL2_1,
P2MSEL1_0, P2MSEL1_1,
P2MSEL0_0, P2MSEL0_1 ))
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 49/50] pinctrl: renesas: sh7786: Optimize fixed-width reserved fields
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (47 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 48/50] pinctrl: renesas: sh7785: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 50/50] pinctrl: renesas: checker: Add reserved field checks Geert Uytterhoeven
2022-05-05 10:50 ` [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 79 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-sh7786.c | 21 ++++++++-------------
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-sh7786.c b/drivers/pinctrl/renesas/pfc-sh7786.c
index 4ed31d78fe30f35f..f09f4a76901088b4 100644
--- a/drivers/pinctrl/renesas/pfc-sh7786.c
+++ b/drivers/pinctrl/renesas/pfc-sh7786.c
@@ -666,15 +666,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD1_FN, PD1_OUT, PD1_IN, 0,
PD0_FN, PD0_OUT, PD0_IN, 0 ))
},
- { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2, GROUP(
+ { PINMUX_CFG_REG_VAR("PECR", 0xffcc0008, 16,
+ GROUP(2, 2, -12),
+ GROUP(
PE7_FN, PE7_OUT, PE7_IN, 0,
PE6_FN, PE6_OUT, PE6_IN, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0, ))
+ /* RESERVED [12] */ ))
},
{ PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2, GROUP(
PF7_FN, PF7_OUT, PF7_IN, 0,
@@ -686,15 +683,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF1_FN, PF1_OUT, PF1_IN, 0,
PF0_FN, PF0_OUT, PF0_IN, 0 ))
},
- { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2, GROUP(
+ { PINMUX_CFG_REG_VAR("PGCR", 0xffcc000c, 16,
+ GROUP(2, 2, 2, -10),
+ GROUP(
PG7_FN, PG7_OUT, PG7_IN, 0,
PG6_FN, PG6_OUT, PG6_IN, 0,
PG5_FN, PG5_OUT, PG5_IN, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0, ))
+ /* RESERVED [10] */ ))
},
{ PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2, GROUP(
PH7_FN, PH7_OUT, PH7_IN, 0,
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 50/50] pinctrl: renesas: checker: Add reserved field checks
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (48 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 49/50] pinctrl: renesas: sh7786: " Geert Uytterhoeven
@ 2022-04-13 17:24 ` Geert Uytterhoeven
2022-05-05 10:50 ` [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-04-13 17:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Add checks for discovering registers with reserved fields that could
benefit from being described using variable-width reserved field
shorthands, reducing kernel size.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/core.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c
index 356325df9c18f2ea..340835551466235f 100644
--- a/drivers/pinctrl/renesas/core.c
+++ b/drivers/pinctrl/renesas/core.c
@@ -878,7 +878,7 @@ static const struct sh_pfc_pin __init *sh_pfc_find_pin(
static void __init sh_pfc_check_cfg_reg(const char *drvname,
const struct pinmux_cfg_reg *cfg_reg)
{
- unsigned int i, n, rw;
+ unsigned int i, n, rw, r;
int fw;
sh_pfc_check_reg(drvname, cfg_reg->reg,
@@ -887,6 +887,15 @@ static void __init sh_pfc_check_cfg_reg(const char *drvname,
if (cfg_reg->field_width) {
fw = cfg_reg->field_width;
n = (cfg_reg->reg_width / fw) << fw;
+ for (i = 0, r = 0; i < n; i += 1 << fw) {
+ if (is0s(&cfg_reg->enum_ids[i], 1 << fw))
+ r++;
+ }
+
+ if ((r << fw) * sizeof(u16) > cfg_reg->reg_width / fw)
+ sh_pfc_warn("reg 0x%x can be described with variable-width reserved fields\n",
+ cfg_reg->reg);
+
/* Skip field checks (done at build time) */
goto check_enum_ids;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* Re: [PATCH 00/50] pinctrl: renesas: Reserved field optimizations
2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
` (49 preceding siblings ...)
2022-04-13 17:24 ` [PATCH 50/50] pinctrl: renesas: checker: Add reserved field checks Geert Uytterhoeven
@ 2022-05-05 10:50 ` Geert Uytterhoeven
50 siblings, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2022-05-05 10:50 UTC (permalink / raw)
To: Linus Walleij; +Cc: open list:GPIO SUBSYSTEM, Linux-Renesas, Geert Uytterhoeven
On Wed, Apr 13, 2022 at 7:24 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> Lots of register in pin control subdrivers for Renesas SoCs contain
> reserved or unused fields. As the macros for describing these registers
> (PINMUX_CFG_REG() and PINMUX_CFG_REG_VAR() for registers with
> fixed-width resp. variable-width fields) require describing all fields,
> the resulting data structures contain lots of dummy (zero) values: 2^N
> values for a field of N-bits wide. To reduce data size, reserved bit
> fields wider than 3 bits were typically split in multiple 2-bit fields.
> This patch series aims to improve this by introducing a shorthand for
> describing reserved variable-width register fields without dummy values.
>
> - Patch 1 converts a few register definitions for registers with
> fixed-width fields that accidentally used the equivalent but larger
> description format intended for registers with variable-width
> fields,
> - Patch 2 introduces a shorthand for describing reserved register
> fields,
> - Patches 3-22 convert reserved field descriptions in the various
> SoC-specific pin control subdrivers to the new shorthands,
> - Patches 23-49 convert register definitions for registers with
> reserved fixed-width fields to the equivalent definitions with
> variable-width fields where it makes sense,
> - Patch 50 updates the checker to flag possible conversions to
> variable-width reserved fields.
>
> The total kernel size reduction due to patches 3-49 is:
> - 12685 bytes on ARM32 SoCs (multi-platform),
> - 5416 bytes on ARM64 SoCs (multi-platform),
> - 2575 bytes on SH SoCs (sum of mutually-exclusive single platforms).
>
> I've been running with these changes on R-Mobile APE6 and A1, R-Car
> M2-W, H3 ES1.x, H3 ES2.0, M3-W, M3-N, V3M, E3, D3, V3U, and S4, and
> SH-Mobile AG5 during the past six weeks, without any issues.
>
> I plan to queue these in renesas-pinctrl-for-v5.19.
Done.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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2022-04-13 17:23 [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 01/50] pinctrl: renesas: r8a77470: Use fixed-width description for IPSR regs Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 02/50] pinctrl: renesas: Add shorthand for reserved register fields Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 03/50] pinctrl: renesas: rmobile: Mark unused PORTCR bits reserved Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 04/50] pinctrl: renesas: emev2: Use shorthands for reserved fields Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 05/50] pinctrl: renesas: r8a77470: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 06/50] pinctrl: renesas: r8a7778: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 07/50] pinctrl: renesas: r8a7779: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 08/50] pinctrl: renesas: r8a7790: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 09/50] pinctrl: renesas: r8a7791: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 10/50] pinctrl: renesas: r8a7792: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 11/50] pinctrl: renesas: r8a7794: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 12/50] pinctrl: renesas: r8a77950: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 13/50] pinctrl: renesas: r8a77951: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 14/50] pinctrl: renesas: r8a7796: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 15/50] pinctrl: renesas: r8a77965: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 16/50] pinctrl: renesas: r8a77970: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 17/50] pinctrl: renesas: r8a77980: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 18/50] pinctrl: renesas: r8a77990: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 19/50] pinctrl: renesas: r8a77995: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 20/50] pinctrl: renesas: r8a779a0: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 21/50] pinctrl: renesas: r8a779f0: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 22/50] pinctrl: renesas: sh7734: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 23/50] pinctrl: renesas: r8a73a4: Optimize fixed-width " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 24/50] pinctrl: renesas: r8a7740: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 25/50] pinctrl: renesas: r8a77470: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 26/50] pinctrl: renesas: r8a7779: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 27/50] pinctrl: renesas: r8a7792: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 28/50] pinctrl: renesas: r8a77950: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 29/50] pinctrl: renesas: r8a77951: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 30/50] pinctrl: renesas: r8a77965: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 31/50] pinctrl: renesas: r8a7796: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 32/50] pinctrl: renesas: r8a77970: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 33/50] pinctrl: renesas: r8a77980: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 34/50] pinctrl: renesas: r8a77990: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 35/50] pinctrl: renesas: r8a77995: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 36/50] pinctrl: renesas: r8a779a0: " Geert Uytterhoeven
2022-04-13 17:23 ` [PATCH 37/50] pinctrl: renesas: r8a779f0: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 38/50] pinctrl: renesas: sh7203: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 39/50] pinctrl: renesas: sh7264: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 40/50] pinctrl: renesas: sh7269: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 41/50] pinctrl: renesas: sh73a0: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 42/50] pinctrl: renesas: sh7720: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 43/50] pinctrl: renesas: sh7722: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 44/50] pinctrl: renesas: sh7723: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 45/50] pinctrl: renesas: sh7724: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 46/50] pinctrl: renesas: sh7734: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 47/50] pinctrl: renesas: sh7757: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 48/50] pinctrl: renesas: sh7785: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 49/50] pinctrl: renesas: sh7786: " Geert Uytterhoeven
2022-04-13 17:24 ` [PATCH 50/50] pinctrl: renesas: checker: Add reserved field checks Geert Uytterhoeven
2022-05-05 10:50 ` [PATCH 00/50] pinctrl: renesas: Reserved field optimizations Geert Uytterhoeven
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