From: Alexander Stein <alexander.stein@ew.tq-group.com> To: Tim Harvey <tharvey@gateworks.com> Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, NXP Linux Team <linux-imx@nxp.com>, Fabio Estevam <festevam@gmail.com>, Pengutronix Kernel Team <kernel@pengutronix.de>, Sascha Hauer <s.hauer@pengutronix.de>, Shawn Guo <shawnguo@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org>, Tim Harvey <tharvey@gateworks.com> Subject: Re: [PATCH] arm64: dts: imx8mp-venice-gw74xx: add PCIe support Date: Fri, 09 Sep 2022 07:59:52 +0200 [thread overview] Message-ID: <2530681.Lt9SDvczpP@steina-w> (raw) In-Reply-To: <20220908154903.4100386-1-tharvey@gateworks.com> Hi Tim, Am Donnerstag, 8. September 2022, 17:49:03 CEST schrieb Tim Harvey: > Add PCIe support on the Gateworks GW74xx board. While at it, > fix the related gpio line names from the previous incorrect values. > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> > --- > .../dts/freescale/imx8mp-venice-gw74xx.dts | 40 +++++++++++++++++-- > 1 file changed, 37 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index > e0fe356b662d..7644db61d631 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > @@ -8,6 +8,7 @@ > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/input/linux-event-codes.h> > #include <dt-bindings/leds/common.h> > +#include <dt-bindings/phy/phy-imx8-pcie.h> > > #include "imx8mp.dtsi" > > @@ -100,6 +101,12 @@ led-1 { > }; > }; > > + pcie0_refclk: pcie0-refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + }; > + > pps { > compatible = "pps-gpio"; > pinctrl-names = "default"; > @@ -215,8 +222,8 @@ &gpio1 { > &gpio2 { > gpio-line-names = > "", "", "", "", "", "", "", "", > - "", "", "", "", "", "", "", "", > - "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "", > + "", "", "", "", "", "", "pcie3_wdis#", "", > + "", "", "pcie2_wdis#", "", "", "", "", "", > "", "", "", "", "", "", "", ""; > }; > > @@ -562,6 +569,28 @@ &i2c4 { > status = "okay"; > }; > > +&pcie_phy { > + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; > + fsl,clkreq-unsupported; > + clocks = <&pcie0_refclk>; > + clock-names = "ref"; > + status = "okay"; > +}; > + > +&pcie { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie0>; > + reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>; > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > + <&clk IMX8MP_CLK_PCIE_ROOT>, > + <&clk IMX8MP_CLK_HSIO_AXI>; > + clock-names = "pcie", "pcie_aux", "pcie_bus"; With the still pending dt-binding patch at [1] the clock order shall be "pcie", "pcie_bus", "pcie_phy". Best regards, Alexander [1] https://lore.kernel.org/lkml/20220822184701.25246-2-Sergey.Semin@baikalelectronics.ru/ > + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; > + assigned-clock-rates = <10000000>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; > + status = "okay"; > +}; > + > /* GPS / off-board header */ > &uart1 { > pinctrl-names = "default"; > @@ -694,7 +723,6 @@ pinctrl_hog: hoggrp { > MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ > MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ > MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 / * M2SKT_OFF# */ > - MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000150 /* PCIE1_WDIS# */ > MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ > MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 / * PCIE3_WDIS# */ > MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ > @@ -807,6 +835,12 @@ MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 > > >; > > }; > > + pinctrl_pcie0: pciegrp { > + fsl,pins = < > + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110 > + >; > + }; > + > pinctrl_pmic: pmicgrp { > fsl,pins = < > MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
WARNING: multiple messages have this Message-ID (diff)
From: Alexander Stein <alexander.stein@ew.tq-group.com> To: Tim Harvey <tharvey@gateworks.com> Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, NXP Linux Team <linux-imx@nxp.com>, Fabio Estevam <festevam@gmail.com>, Pengutronix Kernel Team <kernel@pengutronix.de>, Sascha Hauer <s.hauer@pengutronix.de>, Shawn Guo <shawnguo@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org>, Tim Harvey <tharvey@gateworks.com> Subject: Re: [PATCH] arm64: dts: imx8mp-venice-gw74xx: add PCIe support Date: Fri, 09 Sep 2022 07:59:52 +0200 [thread overview] Message-ID: <2530681.Lt9SDvczpP@steina-w> (raw) In-Reply-To: <20220908154903.4100386-1-tharvey@gateworks.com> Hi Tim, Am Donnerstag, 8. September 2022, 17:49:03 CEST schrieb Tim Harvey: > Add PCIe support on the Gateworks GW74xx board. While at it, > fix the related gpio line names from the previous incorrect values. > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> > --- > .../dts/freescale/imx8mp-venice-gw74xx.dts | 40 +++++++++++++++++-- > 1 file changed, 37 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index > e0fe356b662d..7644db61d631 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > @@ -8,6 +8,7 @@ > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/input/linux-event-codes.h> > #include <dt-bindings/leds/common.h> > +#include <dt-bindings/phy/phy-imx8-pcie.h> > > #include "imx8mp.dtsi" > > @@ -100,6 +101,12 @@ led-1 { > }; > }; > > + pcie0_refclk: pcie0-refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + }; > + > pps { > compatible = "pps-gpio"; > pinctrl-names = "default"; > @@ -215,8 +222,8 @@ &gpio1 { > &gpio2 { > gpio-line-names = > "", "", "", "", "", "", "", "", > - "", "", "", "", "", "", "", "", > - "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "", > + "", "", "", "", "", "", "pcie3_wdis#", "", > + "", "", "pcie2_wdis#", "", "", "", "", "", > "", "", "", "", "", "", "", ""; > }; > > @@ -562,6 +569,28 @@ &i2c4 { > status = "okay"; > }; > > +&pcie_phy { > + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; > + fsl,clkreq-unsupported; > + clocks = <&pcie0_refclk>; > + clock-names = "ref"; > + status = "okay"; > +}; > + > +&pcie { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie0>; > + reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>; > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > + <&clk IMX8MP_CLK_PCIE_ROOT>, > + <&clk IMX8MP_CLK_HSIO_AXI>; > + clock-names = "pcie", "pcie_aux", "pcie_bus"; With the still pending dt-binding patch at [1] the clock order shall be "pcie", "pcie_bus", "pcie_phy". Best regards, Alexander [1] https://lore.kernel.org/lkml/20220822184701.25246-2-Sergey.Semin@baikalelectronics.ru/ > + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; > + assigned-clock-rates = <10000000>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; > + status = "okay"; > +}; > + > /* GPS / off-board header */ > &uart1 { > pinctrl-names = "default"; > @@ -694,7 +723,6 @@ pinctrl_hog: hoggrp { > MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ > MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ > MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 / * M2SKT_OFF# */ > - MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000150 /* PCIE1_WDIS# */ > MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ > MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 / * PCIE3_WDIS# */ > MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ > @@ -807,6 +835,12 @@ MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 > > >; > > }; > > + pinctrl_pcie0: pciegrp { > + fsl,pins = < > + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110 > + >; > + }; > + > pinctrl_pmic: pmicgrp { > fsl,pins = < > MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-09-09 6:00 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-08 15:49 [PATCH] arm64: dts: imx8mp-venice-gw74xx: add PCIe support Tim Harvey 2022-09-08 15:49 ` Tim Harvey 2022-09-09 5:59 ` Alexander Stein [this message] 2022-09-09 5:59 ` Alexander Stein 2022-09-09 17:42 ` Tim Harvey 2022-09-09 17:42 ` Tim Harvey 2022-09-14 17:09 ` Tim Harvey 2022-09-14 17:09 ` Tim Harvey 2022-09-16 10:03 ` Shawn Guo 2022-09-16 10:03 ` Shawn Guo
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