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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [Qemu-devel] [PATCH v1 4/9] target/riscv: Set privledge spec 1.11.0 as default
Date: Mon, 17 Jun 2019 18:31:11 -0700	[thread overview]
Message-ID: <313968903b6233d286c32bb0f52ac1620033a761.1560821342.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1560821342.git.alistair.francis@wdc.com>

Set the priv spec version 1.11.0 as the default and allow selecting it
via the command line.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a4dd7ae6fc..a23d83921a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -111,7 +111,7 @@ static void riscv_any_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
+    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_11_0);
     set_resetvec(env, DEFAULT_RSTVEC);
 }
 
@@ -316,7 +316,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     RISCVCPU *cpu = RISCV_CPU(dev);
     CPURISCVState *env = &cpu->env;
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
-    int priv_version = PRIV_VERSION_1_10_0;
+    int priv_version = PRIV_VERSION_1_11_0;
     int user_version = USER_VERSION_2_02_0;
     target_ulong target_misa = 0;
     Error *local_err = NULL;
@@ -328,7 +328,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     }
 
     if (cpu->cfg.priv_spec) {
-        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
+        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
+            priv_version = PRIV_VERSION_1_11_0;
+        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
             priv_version = PRIV_VERSION_1_10_0;
         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
             priv_version = PRIV_VERSION_1_09_1;
-- 
2.22.0



WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@sifive.com, alistair.francis@wdc.com, alistair23@gmail.com
Subject: [Qemu-riscv] [PATCH v1 4/9] target/riscv: Set privledge spec 1.11.0 as default
Date: Mon, 17 Jun 2019 18:31:11 -0700	[thread overview]
Message-ID: <313968903b6233d286c32bb0f52ac1620033a761.1560821342.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1560821342.git.alistair.francis@wdc.com>

Set the priv spec version 1.11.0 as the default and allow selecting it
via the command line.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a4dd7ae6fc..a23d83921a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -111,7 +111,7 @@ static void riscv_any_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
+    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_11_0);
     set_resetvec(env, DEFAULT_RSTVEC);
 }
 
@@ -316,7 +316,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     RISCVCPU *cpu = RISCV_CPU(dev);
     CPURISCVState *env = &cpu->env;
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
-    int priv_version = PRIV_VERSION_1_10_0;
+    int priv_version = PRIV_VERSION_1_11_0;
     int user_version = USER_VERSION_2_02_0;
     target_ulong target_misa = 0;
     Error *local_err = NULL;
@@ -328,7 +328,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     }
 
     if (cpu->cfg.priv_spec) {
-        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
+        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
+            priv_version = PRIV_VERSION_1_11_0;
+        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
             priv_version = PRIV_VERSION_1_10_0;
         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
             priv_version = PRIV_VERSION_1_09_1;
-- 
2.22.0



  parent reply	other threads:[~2019-06-18  1:37 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-18  1:31 [Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions Alistair Francis
2019-06-18  1:31 ` [Qemu-riscv] " Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 1/9] target/riscv: Restructure deprecatd CPUs Alistair Francis
2019-06-18  1:31   ` [Qemu-riscv] " Alistair Francis
2019-06-18  5:23   ` [Qemu-devel] " Philippe Mathieu-Daudé
2019-06-18  5:23     ` [Qemu-riscv] " Philippe Mathieu-Daudé
2019-06-18 15:59     ` Alistair Francis
2019-06-18 15:59       ` [Qemu-riscv] " Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 2/9] target/riscv: Add the privledge spec version 1.11.0 Alistair Francis
2019-06-18  1:31   ` [Qemu-riscv] " Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit CSR Alistair Francis
2019-06-18  1:31   ` [Qemu-riscv] " Alistair Francis
2019-06-24  9:31   ` [Qemu-devel] " Palmer Dabbelt
2019-06-24  9:31     ` [Qemu-riscv] " Palmer Dabbelt
2019-06-24 20:14     ` [Qemu-devel] " Alistair Francis
2019-06-24 20:14       ` [Qemu-riscv] " Alistair Francis
2019-06-18  1:31 ` Alistair Francis [this message]
2019-06-18  1:31   ` [Qemu-riscv] [PATCH v1 4/9] target/riscv: Set privledge spec 1.11.0 as default Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 5/9] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 Alistair Francis
2019-06-18  1:31   ` [Qemu-riscv] " Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 6/9] target/riscv: Require either I or E base extension Alistair Francis
2019-06-18  1:31   ` [Qemu-riscv] " Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 7/9] target/riscv: Remove user version information Alistair Francis
2019-06-18  1:31   ` [Qemu-riscv] " Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 8/9] target/riscv: Add support for disabling/enabling Counters Alistair Francis
2019-06-18  1:31   ` [Qemu-riscv] " Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 9/9] target/riscv: Add Zifencei and Zicsr as command line options Alistair Francis
2019-06-18  1:31   ` [Qemu-riscv] " Alistair Francis
2019-06-24  9:31   ` [Qemu-devel] " Palmer Dabbelt
2019-06-24  9:31     ` [Qemu-riscv] " Palmer Dabbelt
2019-06-24 23:16     ` [Qemu-devel] " Alistair Francis
2019-06-24 23:16       ` [Qemu-riscv] " Alistair Francis
2019-06-25 10:08       ` [Qemu-devel] " Palmer Dabbelt
2019-06-25 10:08         ` [Qemu-riscv] " Palmer Dabbelt
2019-06-19 10:58 ` [Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions Palmer Dabbelt
2019-06-19 10:58   ` [Qemu-riscv] " Palmer Dabbelt
2019-06-19 14:19   ` [Qemu-devel] " Alistair Francis
2019-06-19 14:19     ` [Qemu-riscv] " Alistair Francis
2019-06-21  2:49     ` [Qemu-devel] " Palmer Dabbelt
2019-06-21  2:49       ` [Qemu-riscv] " Palmer Dabbelt
2019-06-22  0:23       ` [Qemu-devel] " Alistair Francis
2019-06-22  0:23         ` [Qemu-riscv] " Alistair Francis
2019-06-23 14:40         ` [Qemu-devel] " Palmer Dabbelt
2019-06-23 14:40           ` [Qemu-riscv] " Palmer Dabbelt
2019-06-24  9:33 ` [Qemu-devel] " Palmer Dabbelt
2019-06-24  9:33   ` [Qemu-riscv] " Palmer Dabbelt
2019-06-24 20:13   ` [Qemu-devel] " Alistair Francis
2019-06-24 20:13     ` [Qemu-riscv] " Alistair Francis

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