From: Michael Walle <michael@walle.cc> To: Andrea Zanotti <andreazanottifo@gmail.com> Cc: Tudor Ambarus <tudor.ambarus@microchip.com>, Pratyush Yadav <p.yadav@ti.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mtd: spi-nor: micron-st: added support for np8p128ax60 Date: Tue, 31 Aug 2021 10:39:27 +0200 [thread overview] Message-ID: <3462300528bbe71207ef2164411e34d2@walle.cc> (raw) In-Reply-To: <20210831081329.27420-1-andrea.zanotti@tyvak.eu> Hi Andrea, Am 2021-08-31 10:13, schrieb Andrea Zanotti: > From: Andrea Zanotti <andreazanottifo@gmail.com> > > Added support for P8P Parallel Phase Change Memory. Please use present tense, eg "add support..." Is there a public datasheet? If so, please include it above your SoB like so: Datasheet: https://... > Added memory information (page size and sector size) as per data- > sheet information, after typos corrections. After typos corrections? > At page 37, paragraph 'SPI Memory Organization', it is written > down that the memory is organized as: > * 16.772.216 bytes (typo here, there 16.777.216 bytes) > * 128 sectors of 128 Kbytes each (correct) > * 131.072 pages of 64 bytes each (typo here, as the total would be > 64Mbit, but the total memory is actually 128Mbit, correct value > is 262.144 pages) > > Patch tested against the aforementioned PCM memory. What SPI host controller was used? > No known regressions inserted, as the patch only adds the possibility > to recognize said PCM memory inside the common spi-nor driver. Please drop this. If there were any regressions, the patch wouldn't be picked up anyway. > > Signed-off-by: Andrea Zanotti <andreazanottifo@gmail.com> > --- > drivers/mtd/spi-nor/micron-st.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mtd/spi-nor/micron-st.c > b/drivers/mtd/spi-nor/micron-st.c > index c224e59820a1..c78331451082 100644 > --- a/drivers/mtd/spi-nor/micron-st.c > +++ b/drivers/mtd/spi-nor/micron-st.c > @@ -128,6 +128,7 @@ static const struct flash_info micron_parts[] = { > { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048, > SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | > SPI_NOR_4B_OPCODES) }, > + { "np8p128ax60", {0x89, 0xda, 0x18}, 3, 128 * 1024, 128, 64, 0, 0 }, Eh? Please use INFO(). And why isn't this 0x20 for micron. I found this datasheet: https://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/NP8P128Ax60E_Rev_K.pdf According to that datasheet, the manuf id is 0x20. And the device id should be either 0x88e1 or 0x8821. > }; > > static const struct flash_info st_parts[] = { -- -michael
WARNING: multiple messages have this Message-ID (diff)
From: Michael Walle <michael@walle.cc> To: Andrea Zanotti <andreazanottifo@gmail.com> Cc: Tudor Ambarus <tudor.ambarus@microchip.com>, Pratyush Yadav <p.yadav@ti.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mtd: spi-nor: micron-st: added support for np8p128ax60 Date: Tue, 31 Aug 2021 10:39:27 +0200 [thread overview] Message-ID: <3462300528bbe71207ef2164411e34d2@walle.cc> (raw) In-Reply-To: <20210831081329.27420-1-andrea.zanotti@tyvak.eu> Hi Andrea, Am 2021-08-31 10:13, schrieb Andrea Zanotti: > From: Andrea Zanotti <andreazanottifo@gmail.com> > > Added support for P8P Parallel Phase Change Memory. Please use present tense, eg "add support..." Is there a public datasheet? If so, please include it above your SoB like so: Datasheet: https://... > Added memory information (page size and sector size) as per data- > sheet information, after typos corrections. After typos corrections? > At page 37, paragraph 'SPI Memory Organization', it is written > down that the memory is organized as: > * 16.772.216 bytes (typo here, there 16.777.216 bytes) > * 128 sectors of 128 Kbytes each (correct) > * 131.072 pages of 64 bytes each (typo here, as the total would be > 64Mbit, but the total memory is actually 128Mbit, correct value > is 262.144 pages) > > Patch tested against the aforementioned PCM memory. What SPI host controller was used? > No known regressions inserted, as the patch only adds the possibility > to recognize said PCM memory inside the common spi-nor driver. Please drop this. If there were any regressions, the patch wouldn't be picked up anyway. > > Signed-off-by: Andrea Zanotti <andreazanottifo@gmail.com> > --- > drivers/mtd/spi-nor/micron-st.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mtd/spi-nor/micron-st.c > b/drivers/mtd/spi-nor/micron-st.c > index c224e59820a1..c78331451082 100644 > --- a/drivers/mtd/spi-nor/micron-st.c > +++ b/drivers/mtd/spi-nor/micron-st.c > @@ -128,6 +128,7 @@ static const struct flash_info micron_parts[] = { > { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048, > SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | > SPI_NOR_4B_OPCODES) }, > + { "np8p128ax60", {0x89, 0xda, 0x18}, 3, 128 * 1024, 128, 64, 0, 0 }, Eh? Please use INFO(). And why isn't this 0x20 for micron. I found this datasheet: https://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/NP8P128Ax60E_Rev_K.pdf According to that datasheet, the manuf id is 0x20. And the device id should be either 0x88e1 or 0x8821. > }; > > static const struct flash_info st_parts[] = { -- -michael ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2021-08-31 8:39 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-31 8:13 [PATCH] mtd: spi-nor: micron-st: added support for np8p128ax60 Andrea Zanotti 2021-08-31 8:13 ` Andrea Zanotti 2021-08-31 8:39 ` Michael Walle [this message] 2021-08-31 8:39 ` Michael Walle [not found] ` <CAGiusB1JvHkX7GSvD2JsqKWwC5xBePX_ruWk9nU9gugoroLnKA@mail.gmail.com> 2021-08-31 10:11 ` Andrea Zanotti 2021-08-31 10:11 ` Andrea Zanotti 2021-08-31 15:05 ` Michael Walle 2021-08-31 15:05 ` Michael Walle 2021-09-01 11:20 ` Andrea Zanotti 2021-09-01 11:20 ` Andrea Zanotti 2021-09-03 11:47 ` Michael Walle 2021-09-03 11:47 ` Michael Walle
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